Analog Devices AD5532HSABC Datasheet

32-Channel 14-Bit DAC with

a

FEATURES
High Integration: 32-Channel DAC in 12 ⴛ 12 mm
Guaranteed Monotonic
DSP-/Microcontroller-Compatible Serial Interface
Channel Update Rate 1.1 MHz
Output Impedance 0.5 ⍀
Selectable Output Voltage 0 V to 5 V or –2.5 V to +2.5 V
Asynchronous RESET Facility
Temperature Range –40ⴗC to +85ⴗC

APPLICATIONS
Optical Networks
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

CC

High-Speed 3-Wire Serial Interface

AD5532HS*

2

LFBGA

REF_IN OFFS_IN

GENERAL DESCRIPTION

The AD5532HS is a 32-channel voltage-output 14-bit DAC
with a high-speed serial interface. The selected DAC register is
written to via the 3-wire interface. The serial interface operates
at clock rates up to 30 MHz and is compatible with DSP and
microcontroller interface standards. The output voltage range is
0 V to 5 V or –2.5 V to +2.5 V and is determined by the offset
voltage at the OFFS_IN pin. It is restricted to a range from

+ 2 V to VDD – 2 V because of the headroom of the out-

V

SS

put amplifier.

The device is operated with AV
to 5.25 V, V

= –4.75 V to –12 V and VDD = +4.75 V to +12 V

SS

= 5 V ± 5%, DVCC = 2.7 V

CC

and requires a stable 2.5 V reference on REF_IN.

PRODUCT HIGHLIGHTS

1. 32 14-bit DACs in one package, guaranteed monotonic.

2. The AD5532HS is available in a 74-ball LFBGA package
with a body size of 12 mm by 12 mm.

VDDV

SS

AD5532HS

RESET

DAC_GND

AGND

DGND

INTERFACE

CONTROL

LOGIC

D

SCLK

IN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

14-BIT BUS

SYNC

DAC

DAC

DAC

DAC

R

R

R

R

R

R

R

R

V

0

OUT

V

1

OUT

30

V

OUT

31

V

OUT

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

AD5532HS–SPECIFICATIONS

(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN =

2.5 V; OFFS_IN = 0 V; All outputs unloaded. All specifications T

Parameter

D

AC DC PERFORMANCE

1

A Version
Min Typ Max Unit Conditions/Comments

Resolution 14 Bits
Integral Nonlinearity (INL) –0.39 ±0.1 +0.39 % of FSR See TPC 7
Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Monotonic
Offset Error –10 +15 +50 mV See TPC 8
Full-Scale Error –1 –0.3 +0.5 % of FSR See TPC 9

VOLTAGE REFERENCE REF_IN

Input Voltage Range

3

2.375 2.5 2.625 V

Input Current ±0.001 ±1 µA

ANALOG INPUT OFFS_IN

Input Voltage Range

3, 4

0V

Input Current ±0.1 ±1 µA

ANALOG OUTPUTS (V

Output Temperature Coefficient
DC Output Impedance
Output Range

4

OUT

3

0–V

OUT

3, 5

31)

OFFS_IN = 0 0 – 2REF_IN V

OFFS_IN = REF_IN –REF_IN to +REF_IN V
Resistive Load
Capacitive Load
Short-Circuit Current
DC Power-Supply Rejection Ratio

DC Crosstalk

DIGITAL INPUTS

3

3

3

3

3

3

5kΩ

Input Current ±5 ±10 µA
Input Low Voltage 0.8 V DV

Input High Voltage 2.4 V DV

2.0 V DV

Input Hysteresis (SCLK and SYNC Only) 200 mV
Input Capacitance 10 pF

POWER SUPPLY VOLTAGES

V

DD

V

SS

AV

CC

DV

CC

POWER SUPPLY CURRENTS

I

DD

I

SS

AI

CC

DI

CC

POWER DISSIPATION

NOTES

1

See Terminology

2

A Version: Industrial temperature range –40°C to +85°C; typical at 25°C.

3

Guaranteed by design and characterization, not production tested.

4

Output range is restricted from VSS + 2 V to VDD – 2 V.

5

AD780 as reference for the AD5532HS.

6

Outputs unloaded.

Specifications subject to change without notice.

6

6

+4.75 +12 V
–4.75 –12 V

4.75 5.25 V

2.7 5.25 V

to T

MIN

unless otherwise noted.)

MAX

2

– 1.5 V

DD

20 ppm/°C

0.5 Ω

100 pF
7mA
–70 dB VDD = +10 V ± 5%
–70 dB V

= –10 V ± 5%

SS

120 µV

= 5 V ± 5%

0.4 V DV

CC

= 3 V ± 10%

CC

= 5 V ± 5%

CC

= 3 V ± 10%

CC

9 12 mA All Channels Full Scale
9 12 mA All Channels Full Scale

6.5 10 mA

0.1 0.5 mA VIH = DVCC and VIL = DGND

123 mW VDD = +5 V, VSS = –5 V

–2–

REV. 0

AD5532HS

AC CHARACTERISTICS

DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications T

Parameter1,

Output Voltage Settling Time

2

(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =

to T

MIN

A Version

4

10 µs max 100 pF, 5 kΩ Load; Full-Scale Change

3

Unit Conditions/Comments

unless otherwise noted.)

MAX

Slew Rate 0.85 V/µs typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk 1 nV-s typ
Digital Feedthrough 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 170 nV/√Hz typ

NOTES

1

See Terminology

2

Guaranteed by design and characterization, not production tested

3

B Version: Industrial temperature range –40°C to +85°C.

4

Timed from the end of a write sequence.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

AGND = DGND = DAC_GND = 0 V; All specifications T

Limit at T

Parameter1, 2,

f

UPDATE

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

NOTES

1

See Timing Diagrams in Figure 1.

2

Guaranteed by design and characterization, not production tested.

3

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

Specifications subject to change without notice.

3

(A Version) Unit Conditions/Comments

1.1 MHz max Channel Update Rate
30 MHz max SCLK Frequency
13 ns min SCLK High Pulsewidth
13 ns min SCLK Low Pulsewidth
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min SYNC High Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
280 ns min 19th SCLK Falling Edge to SYNC Falling Edge for Next Write
20 ns min RESET Pulsewidth

MIN

(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

to T

unless otherwise noted.)

MAX

, T

MIN

MAX

SCLK

SYNC

D

IN

RESET

REV. 0

t

1

1

t

3

t

5

MSB

t

9

2345

t

2

t

4

t

6

t

7

16 17 18 19

LSB

1

t

8

Figure 1. Serial Interface Timing Diagram

–3–

AD5532HS

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS1,

(TA = 25°C unless otherwise noted)

2

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

V

SS

AV

to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V

CC

DV

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

CC

Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV

+ 0.3 V

CC

REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V

V

0–V

OUT

0–V

V

OUT

OFFS_IN to AGND . . . . . . . . . . . V

31 to AGND . . . . . . . VSS – 0.3 V to VDD + 0.3 V

OUT

31 to VSS . . . . . . . . . . . . . . . . . . –0.3 V to +24 V

OUT

– 0.3 V to VDD + 0.3 V

SS

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T
74-Lead LFBGA Package, θ

max) . . . . . . . . . . . . . . . . . . 150°C

J

Thermal Impedance . . . 41°C/W

JA

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

Max Power Dissipation at T

= 70°C,

A

Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW

(for TA > 70°C, derate at 26 mW for each °C over 70°C)

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

3

This limit includes load power and applies only when there is a resistive load on
V

outputs.

OUT

ORDERING GUIDE

Output Package Package

Model Function Voltage Span Description Option

AD5532HSABC 32 DACs 5 V 74-Ball LFBGA BC-74

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

3

ACT UAL

IDEAL

OUTPUT VOLTAGE

OFFSET

ERROR

0

DAC CODE

16k

Figure 2. DAC Transfer Function (OFFS_IN = 0)

–4–

FULL-SCALE
ERROR

REV. 0