Analog Devices AD5532 c Datasheet

32-Channel, 14-Bit

FEATURES

High integration:

32-channel DAC in 12 mm × 12 mm CSPBGA
Adjustable voltage output range
Guaranteed monotonic
Readback capability
DSP/microcontroller compatible serial interface
Output impedance:

0.5 Ω (AD5532-1, AD5532-2)

500 Ω (AD5532-3)

1 kΩ (AD5532-5)
Output voltage span:

10 V (AD5532-1, AD5532-3, AD5532-5)

20 V (AD5532-2)
Infinite sample-and-hold capability to ±0.018% accuracy
Temperature range −40°C to +85°C

APPLICATIONS

Automatic test equipment
Optical networks
Level setting
Instrumentation
Industrial control systems
Data acquisition
Low cost I/O

AV

DV

CC

CC

GENERAL DESCRIPTION

The AD55321 is a 32-channel, 14-bit voltage-output DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface; V
DAC is then updated to reflect the new contents of the DAC
register. DAC selection is accomplished via Address Bits A0–A4.
The output voltage range is determined by the offset voltage at
the OFFS_IN pin and the gain of the output amplifier. It is
restricted to a range from V
headroom of the output amplifier.

The device is operated with AV

5.25 V; V

= −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The

SS

AD5532 requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed

monotonic.

2. Available in a 74-lead CSPBGA package with a body size of

12 mm ×12 mm.

3. Droopless/infinite sample-and-hold mode.

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

REF_IN REF_OUT OFFS_IN VDDV

Voltage-Output DAC

AD5532

for this

OUT

+ 2 V to VDD – 2 V because of the

SS

= 5 V ± 5%; DVCC = 2.7 V to

CC

SS

AD5532

V

TRACK/RESET

BUSY

DAC_GND

AGND

DGND

SER/PAR

IN

ADC

MUX DAC

MODE

INTERFACE

CONTROL

LOGIC

SCLK DIND

OUT

Figure 1. Functional Block Diagram

14-BIT BUS

Rev. C

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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DAC

DAC

SYNC/CS

V

0

OUT

31

V

OUT

OFFS_OUT

ADDRESS INPUT REGISTER

A4–A0 CAL OFFSET_SEL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

WR

00939-C-001

AD5532

TABLE OF CONTENTS

Specifications..................................................................................... 3

Offset Voltage Channel.............................................................. 14

ISHA Mode.................................................................................... 5

Timing Characteristics..................................................................... 6

Parallel Interface ........................................................................... 6

Parallel Interface Timing Diagrams........................................... 6

Serial Interface.............................................................................. 7

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Function Descriptions............................. 9

Te r m in o l o g y .................................................................................... 11

Dac Mode ....................................................................................11

ISHA Mode.................................................................................. 11

Typical Performance Characteristics........................................... 12

Functional Description ..................................................................14

Output Buffer Stage—Gain and Offset.................................... 14

REVISION HISTORY

Reset Function............................................................................ 14

ISHA Mode ................................................................................. 14

Analog Input (ISHA Mode) ......................................................14

TRACK

Modes of Operation ................................................................... 15

Serial Interface............................................................................ 16

Parallel Interface (ISHA Mode Only) ......................................17

Microprocessor Interfacing....................................................... 17

Application Circuits................................................................... 18

Power Supply Decoupling .........................................................19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Function (ISHA Mode) .............................................. 15

6/04—Data Sheet Changed from Rev. B to Rev. C

Updated Format........................................................... Universal

Changed LFBGA to CSPBGA.................................... Universal

Changes to Outline Dimensions.............................................24

Changes to Ordering Guide....................................................24

6/02—Data Sheet Changed from Rev. A to Rev. B

Term SHA changed to ISHA........................................... Global

Changes to Absolute Maximum Ratings.................................6

Changes to Ordering Guide......................................................6

Changes to Functional Description .......................................11

Changes to Table 8....................................................................11

Changes to ISHA Mode ...........................................................11

Added Figure 27 and accompanying text..............................15

Changes to Power Supply Decoupling Section.....................15

Rev. C | Page 2 of 20

AD5532

SPECIFICATIONS

VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V;
REF_IN = 3 V; output range from V

+ 2 V to VDD − 2 V. All outputs unloaded. All specifications T

SS

MIN

to T

, unless otherwise noted.

MAX

Table 1.

A Version

1

Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

DAC DC PERFORMANCE

Resolution 14 14 Bits
Integral Nonlinearity (INL) ±0.39 ±0.39 % of FSR max ±0.15% typ
Differential Nonlinearity (DNL) ±1 ±1 LSB max ±0.5 LSB typ, monotonic
Offset 90/170/250 180/350/500 mV min/typ/max See Figure 8

Gain 3.52 7 typ
Full Scale Error ±2 ±2 % of FSR max
VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 3.0 V typ
Input Voltage Range3 2.85/3.15 2.85/3.15 V min/max
Input Current 1 1 µA max < 1 nA typ

REF_OUT

Output Voltage 3 3 V typ
Output Impedance3 280 280 kΩ typ
Reference Temperature Coefficient3 60 60 ppm/°C typ

ANALOG OUTPUTS (V

0–31)

OUT

Output Temperature Coefficient3, 4 10 10 ppm/°C typ

DC Output Impedance3

AD5532-1 0.5 0.5 Ω typ
AD5532-3 500 Ω typ
AD5532-5 1 kΩ typ

Output Range

V

+ 2/VDD − 2 VSS + 2 /VDD − 2

SS

V min/max
Resistive Load3, 5 5 5 kΩ min
Capacitive Load3, 5

AD5532-1 500 500 pF max
AD5532-3 15 nF max

AD5532-5 40 nF max
Short-Circuit Current3 7 7 mA typ
DC Power-Supply Rejection Ratio3

−70 −70

−70 −70

dB typ VDD = +15 V ±5%
dB typ

V

= −15 V ±5%

SS

DC Crosstalk3 250 1800 µV max

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient3, 4 10 10 ppm/°C typ
DC Output Impedance3 1.3 1.3 kΩ typ
Output Range

50 to REF_IN−12 50 to REF_IN−12

mV typ
Output Current 10 10 µA max Source current
Capacitive Load 100 100 pF max

DIGITAL INPUTS3

Input Current ±10 ±10 µA max ±5 µA typ
Input Low Voltage 0.8 0.8 V max DVCC = 5 V ±5%

0.4 0.4 V max DVCC = 3 V ±10%
Input High Voltage 2.4 2.4 V min DVCC = 5 V ±5%

2.0 2.0 V min DVCC = 3 V ±10%
Input Hysteresis (SCLK and CS Only)

200 200 mV typ

Rev. C | Page 3 of 20

AD5532

A Version

1

Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

Input Capacitance 10 10 pF max

DIGITAL OUTPUTS (BUSY, D

OUT

)3
Output Low Voltage, DVCC = 5 V 0.4 0.4 V max Sinking 200 µA.
Output High Voltage, DVCC = 5 V 4.0 4.0 V min Sourcing 200 µA.
Output Low Voltage, DVCC = 3 V 0.4 0.4 V max Sinking 200 µA.
Output High Voltage, DVCC = 3 V 2.4 2.4 V min Sourcing 200 µA.
High Impedance Leakage Current ±1 ±1 µA max D
High Impedance Output Capacitance 15 15 pF typ D

OUT

OUT

only.

only.

POWER REQUIREMENTS

Power-Supply Voltages
VDD 8/16.5 8/16.5 V min/max
VSS

−4.75/−16.5 −4.75/−16.5

V min/max
AVCC 4.75/5.25 4.75/5.25 V min/max
DVCC 2.7/5.25 2.7/5.25 V min/max
Power-Supply Currents

IDD 15 15 mA max

6

10 mA typ. All channels
full scale.

ISS 15 15 mA max

10 mA typ. All channels

full scale.
AICC 33 33 mA max 26 mA typ.
DICC 1.5 1.5 mA max 1 mA typ.

Power Dissipation6 280 280 mW typ

V

= 10 V, VSS = −5 V.

DD

AC CHARACTERISTICS3

Output Voltage Settling Time 22 30 µs max

OFFS_IN Settling Time 10 25

µs max

Digital-to-Analog Glitch Impulse 1 1 nV-s typ

500 pF, 5 kΩ load. Full-scale

change.

500 pF, 5 kΩ load; 0 V to 3 V

step.

1 LSB change around. Major

carry.

Digital Crosstalk 5 5 nV-s typ
Analog Crosstalk 1 1 nV-s typ
Digital Feedthrough 0.2 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 400 400 nV/(√Hz) typ

1

A version: Industrial temperature range -40°C to +85°C; typical at +25°C.

2

See section. Terminology

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5532.

5

Ensure that you do not exceed TJ (max). See Ab section. solute Maximum Ratings

6

Output unloaded.

Rev. C | Page 4 of 20

AD5532

ISHA MODE

Table 2.

A Version
Parameter

2

AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

1

ANALOG CHANNEL

VIN to V

Nonlinearity

OUT

3

±0.018 ±0.018 % max ±0.006% typ after offset and gain adjustment.
Offset Error ±50 ±75 mV max ±10 mV typ. See Figure 9.
Gain 3.46/3.52/3.6 6.96/7/7.02 min/typ/max See Figure 9

ANALOG INPUT (VIN)

Input Voltage Range 0 to 3 0 to 3 V Nominal input range.
Input Lower Dead Band 70 70 mV max 50 mV typ. Referred to VIN. See Figure 9.
Input Upper Dead Band 40 40 mV max 12 mV typ. Referred to VIN. See Figure 9.
Input Current 1 1 µA max 100 nA typ.
V

acquired on 1 channel.

IN

Input Capacitance4 20 20 pF typ

ANALOG INPUT (OFFS_IN)

Input Current 1 1 µA max 100 nA typ.
Input Voltage Range 0/4 0/4 Vmin/max

Output range restricted from V

+ 2 V to VDD − 2 V.

SS

AC CHARACTERISTICS

Output Settling Time4 3 3 µs max Output unloaded.
Acquisition Time 16 16 µs max
AC Crosstalk4 5 5 nV-s typ

1

A version: Industrial temperature range -40°C to +85°C; typical at +25°C.

2

See section. Terminology

3

Input range 100 mV to 2.96 V.

4

Guaranteed by design and characterization, not production tested.

Rev. C | Page 5 of 20

AD5532

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Table 3.

Parameter1,

2

Limit at T

MIN

, T

(A Version) Unit Conditions/Comments

MAX

t1 0 ns min
t2 0 ns min
t3 50 ns min
t4 50 ns min
t5 20 ns min
t6 7 ns min

1

See and , the parallel interface timing diagrams. Figure 2 Figure 3

2

Guaranteed by design and characterization, not production tested.

PARALLEL INTERFACE TIMING DIAGRAMS

t

2

t

6

00939-C-002

CS

WR

A4–A0, CAL,

OFFS_SEL

t

1

t

3

t

4

t

5

Figure 2. Parallel Write (ISHA Mode Only)

CS to WR setup time
CS to WR hold time
CS pulse width low
WR pulse width low
A4–A0, CAL, OFFS_SEL to
A4–A0, CAL, OFFS_SEL to

200µAI

TO OUTPUT

PIN

C

L

50pF

200µAI

Figure 3. Load Circuit for D

OUT

WR setup time
WR hold time

OL

1.6V

OH

Timing Specifications

00939-C-003

Rev. C | Page 6 of 20