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AD5532B a
Datasheet
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Analog Devices AD5532B a Datasheet

32-Channel, 14-Bit DAC with Precision
a
FEATURES High Integration:
32-Channel DAC in 12 mm  12 mm CSPBGA Guaranteed Monotonic to 14 Bits Infinite Sample-and-Hold Capability to 0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error 2.5 mV Adjustable Voltage Output Range Readback Capability DSP/Microcontroller Compatible Serial Interface Output Impedance 0.5 Output Voltage Span 10 V Temperature Range –40C to +85C
APPLICATIONS Automatic Test Equipment Optical Networks Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O
Infinite Sample-and-Hold Mode
+ 2 V to
SS
*
AD5532B

GENERAL DESCRIPTION

The AD5532B is a 32-channel, voltage output, 14-bit DAC with an additional precision infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial inter­face and V contents of the DAC register. DAC selection is accomplished via address bits A0–A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from V V
– 2 V because of the headroom of the output amplifier.
DD
The device is operated with AV to +5.25 V, V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed monotonic.
2. The AD5532B is available in a 74-lead CSPBGA with a body size of 12 mm 12 mm.
3. In infinite sample-and-hold mode, a total unadjusted error of ±2.5 mV is achieved by laser-trimming on-chip resistors.
for this DAC is then updated to reflect the new
OUT
= +5 V ± 5%, DVCC = +2.7 V
= –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V
SS
CC

FUNCTIONAL BLOCK DIAGRAM

DV
AV
CC
AD5532B
V
IN
TRACK / RESET
BUSY
DAC
GND
AGND
DGND
SER / PAR
*Protected by U.S. Patent No. 5,969,657; other patents pending.
ADC
MUX DAC
INTERFACE
CONTROL
LOGIC
DIND
REF IN REF OUT OFFS IN
CC
14-BIT BUS
MODE
OUT
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
VDDV
SS
V
0
OUT
DAC
V
31
OUT
OFFS
DAC
ADDRESS INPUT REGISTER
SYNC / CS
A4–A0SCLK
CAL
OFFSET_SEL
OUT
WR
AD5532B–SPECIFICATIONS
OFFS_IN = OV; Output Range from V
+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T
SS
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V;
to T
MIN
, unless otherwise noted.)
MAX
Parameter
1
AD5532B-1
B Version
2
Unit Conditions/ Comments
DAC DC PERFORMANCE
Resolution 14 Bits Integral Nonlinearity (INL) ±0.39 % of FSR max ±0.15% typ Differential Nonlinearity (DNL) ±1 LSB max ±0.5 LSB typ Monotonic Offset 90/170/250 mV min/typ/max See Figure 6. Gain 3.52 typ Full-Scale Error –1/+0.5 % of FSR max
ISHA DC PERFORMANCE
V
IN
to V
Nonlinearity
OUT
3
±0.006 % typ After Offset and Gain Adjustment ±0.018 % max
Total Unadjusted Error (TUE) ±2.5 mV typ See TPC 6.
±12 mV max
Offset Error ±1 mV typ
±10 mV max
Gain 3.51/3.52/3.53 min/typ/max
ISHA ANALOG INPUT (V
)
IN
Input Voltage Range 0 to 3 V Nominal Input Range Input Lower Dead Band 70 mV max 50 mV typ. Referred to V
IN
See Figure 7.
Input Upper Dead Band 40 mV max 12 mV typ. Referred to V
IN
See Figure 7.
Input Current 1 µA max 100 nA typ. V
on one channel.
Input Capacitance
4
20 pF typ
acquired
IN
ANALOG INPUT (OFFS_IN)
Input Current 1 µA max 100 nA typ Input Voltage Range 0/4 V min/max Output Range Restricted from
VSS + 2 V to VDD – 2 V
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage 3.0 V typ Input Voltage Range
4
2.85/3.15 V min/max
Input Current 1 µA max <1 nA typ
REF_OUT
Output Voltage 3 V typ Output Impedance Reference Temperature Coefficient
ANALOG OUTPUTS (V
Output Temperature Coefficient DC Output Impedance Output Range V Resistive Load Capacitive Load Short-Circuit Current DC Power-Supply Rejection Ratio
DC Crosstalk
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient DC Output Impedance
4
4
0–31)
OUT
4
4, 6
4, 6
4
4
4
4, 5
4
4, 5
280 kΩ typ 60 ppm/°C typ
10 ppm/°C typ
0.5 Ω typ
+ 2/VDD – 2 V min/max 100 µA Output Load
SS
5kΩ min 100 pF max 7 mA typ –70 dB VDD = +15 V ± 5% –70 dB V
= ⫺15 V ± 5%
SS
250 µV max Outputs Loaded
10 ppm/°C typ
1.3 kΩ typ
Output Range 50 to REF_IN – 12 mV typ Output Current 10 µA max Source Current Capacitive Load 100 pF max
.
.
–2–
REV. A
AD5532B
Parameter
1
DIGITAL INPUTS
7
AD5532B-1 B Version
2
Unit Conditions/Comments
Input Current ±10 µA max ±5 µA typ Input Low Voltage
0.8 V max DV
0.4 V max DV
= 5 V ± 5%
CC
= 3 V ± 10%
CC
Input High Voltage
2.4 V min DV
2.0 V min DV
= 5 V ± 5%
CC
= 3 V ± 10%
CC
Input Hysteresis (SCLK and CS Only) 200 mV typ Input Capacitance 10 pF max
DIGITAL OUTPUTS (BUSY, D
OUT
7
) Output Low Voltage, DVCC = 5 V 0.4 V max Sinking 200 µA Output High Voltage, DV Output Low Voltage, DV Output High Voltage, DV High Impedance Leakage Current ± 1 µA max D High Impedance Output Capacitance 15 pF typ D
= 5 V 4.0 V min Sourcing 200 µA
CC
= 3 V 0.4 V max Sinking 200 µA
CC
= 3 V 2.4 V min Sourcing 200 µA
CC
OUT
OUT
Only Only
POWER REQUIREMENTS
Power Supply Voltages
V
DD
V
SS
AV
CC
DV
CC
Power Supply Currents
I
DD
I
SS
8
8/16.5 V min/max –4.75/–16.5 V min/max
4.75/5.25 V min/max
2.7/5.25 V min/max
15 mA max 10 mA typ. All channels full-scale.
15 mA max 10 mA typ. All channels full-scale. AICC 33 mA max 26 mA typ DICC 1.5 mA max 1 mA typ
Power Dissipation
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Input range 100 mV to 2.96 V.
4
Guaranteed by design and characterization, not production tested.
5
AD780 as reference for the AD5532B.
6
Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings section.
7
Guaranteed by design and characterization, not production tested.
8
Output unloaded.
Specifications subject to change without notice.
8
280 mW typ VDD = +10 V, VSS = –5 V
REV. A
–3–
AD5532B AC CHARACTERISTICS
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T
Parameter
DAC AC CHARACTERISTICS
1
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;
to T
MIN
AD5532B-1 B Version
3
2
Unit Conditions/Comments
, unless otherwise noted.)
MAX
Output Voltage Settling Time 22 µs max 500 pF, 5 kΩ Load Full-Scale Change OFFS_IN Settling Time 10 µs max 500 pF, 5 kΩ Load; 0 V to 3 V Step Digital-to-Analog Glitch Impulse 1 nV-s Digital Crosstalk 5 nV-s Analog Crosstalk 1 nV-s Digital Feedthrough 0.2 nV-s
typ 1 LSB Change Around Major Carry typ typ typ
Output Noise Spectral Density @ 1 kHz 400 nV/√Hz typ
ISHA AC CHARACTERISTICS
Output Voltage Settling Time Acquisition Time 16 µs max AC Crosstalk
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change
3
without notice.
3
3 µs max Outputs Unloaded
5nV-s
typ

TIMING CHARACTERISTICS

PARALLEL INTERFACE
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
See Parallel Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
1, 2
Limit at T (B Version) Unit Conditions/Comments
0 ns min CS to WR Setup Time 0 ns min CS to WR Hold Time 50 ns min CS Pulsewidth Low 50 ns min WR Pulsewidth Low 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time
SERIAL INTERFACE
Parameter
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
4
t
8
4
t
9
t
10
t
11
5
t
12
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4
These numbers are measured with the load circuit of Figure 2.
5
SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
1, 2
3
Limit at T (B Version) Unit Conditions/Comments
14 MHz max SCLK Frequency 28 ns min SCLK High Pulsewidth 28 ns min SCLK Low Pulsewidth 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 50 ns min SYNC Low Time 15 ns min DIN Setup Time 5 ns min DIN Hold Time 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback 20 ns max SCLK Rising Edge to D 60 ns max SCLK Falling Edge to D 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback 400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write 7 ns min SCLK Falling Edge to SYNC Falling Edge for Readback
MIN
MIN
, T
, T
MAX
MAX
–4–
Valid
OUT
High Impedance
OUT
REV. A
S

PARALLEL INTERFACE TIMING DIAGRAM

AD5532B
CS
WR
A4–A0, CAL,
SEL
OFFS
Figure 1. Parallel Write (ISHA Mode Only)

SERIAL INTERFACE TIMING DIAGRAMS

t
1
SCLK
SYNC
D
IN
12 34567 8910
t
3
MSB LSB
t
2
t
4
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
I
200A
TO
OUTPUT
PIN
C
L
50pF
200A
Figure 2. Load Circuit for D
t
5
t
6
OL
1.6V
I
OH
Timing Specifications
OUT
SCLK
SYNC
D
IN
SCLK
YNC
D
OUT
t
1
1
t
MSB
2345
t
3
2
t
4
t
5
t
6
21 22 23 24
LSB
1
t
11
Figure 4. 24-Bit Write (DAC Mode)
t
7
10
t
12
t
10
t
1
213456789
t
2
t
4
t
8
MSB
10
11
12 13 14
t
9
LSB
Figure 5. 14-Bit Read (Both Readback Modes)
REV. A
–5–
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