Analog Devices AD5532 Datasheet

32-Channel, 14-Bit

a

FEATURES
High Integration: 32-Channel DAC in 12 ⴛ 12 mm
Adjustable Voltage Output Range
Guaranteed Monotonic
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Output Impedance

0.5 ⍀ (AD5532-1, AD5532-2)
500 ⍀ (AD5532-3)
1 k⍀ (AD5532-5)

Output Voltage Span

10 V (AD5532-1, AD5532-3, AD5532-5)

20 V (AD5532-2)
Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy
Temperature Range –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O

2

LFBGA

Voltage-Output DAC

AD5532*

GENERAL DESCRIPTION

The AD5532 is a 32-channel voltage-output 14-bit DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface and V
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via address bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from V

SS

+ 2 V to V

– 2 V because

DD

of the headroom of the output amplifier.

The device is operated with AV
to 5.25 V, V

= –4.75 V to –16.5 V and VDD = 8 V to 16.5 V

SS

= 5 V ± 5%, DVCC = 2.7 V

CC

and requires a stable +3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.

2. The AD5532 is available in a 74-lead LFBGA package with
a body size of 12 mm × 12 mm.

3. Droopless/Infinite Sample-and-Hold Mode.

OUT

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

AD5532

V

IN

TRACK /RESET

BUSY

GND

DAC

AGND

DGND

SER / PAR

*Protected by U.S. Patent No. 5,969,657; other patents pending.

ADC

MUX DAC

MODE

INTERFACE

CONTROL

LOGIC

SCLK

DIND

REF IN REF OUT

CC

14-BIT BUS

OUT

DAC

DAC

SYNC / CS

OFFS IN

ADDRESS INPUT REGISTER

CALA4– A0

VDDV

OFFSET SEL

SS

V

0

OUT

V

31

OUT

OFFS OUT

WR

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD5532–SPECIFICATIONS

5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from V
to T

unless otherwise noted.)

MAX

Parameter

1

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to

+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T

SS

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

2

Conditions/

DAC DC PERFORMANCE

Resolution 14 14 Bits
Integral Nonlinearity (INL) ±0.39 ±0.39 % of FSR max ±0.15% typ
Differential Nonlinearity (DNL) ±1 ±1 LSB max ±0.5% typ, Monotonic
Offset 90/170/250 180/350/500 mV min/typ/max See Figure 6
Gain 3.52 7 typ
Full-Scale Error ±2 ±2 % of FSR max

VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 3.0 V
Input Voltage Range

3

2.85/3.15 2.85/3.15 V min/max

Input Current 1 1 µA max < 1 nA typ

REF_OUT

Output Voltage 3 3 V typ
Output Impedance
Reference Temperature Coefficient

ANALOG OUTPUTS (V

Output Temperature Coefficient
DC Output Impedance

3

3

0–31)

OUT

3

3, 4

280 280 kΩ typ
60 60 ppm/°C typ

20 20 ppm/°C typ

AD5532-1 0.5 0.5 Ω typ
AD5532-3 500 Ω typ
AD5532-5 1 kΩ typ

Output Range V
Resistive Load
Capacitive Load

3, 5

3, 5

+ 2/VDD – 2 VSS + 2 /VDD – 2 V min/max 100 µA Output Load

SS

55 kΩ min

AD5532-1 500 500 pF max
AD5532-3 15 nF max

AD5532-5 40 nF max
Short-Circuit Current
DC Power-Supply Rejection Ratio

DC Crosstalk

3

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient
DC Output Impedance

3

3

10 10 mA typ
–70 –70 dB typ VDD = +15 V ± 5%
–70 –70 dB typ V

= –15 V ± 5%

SS

250 250 µV max

3, 4

3

20 20 ppm/°C typ

1.3 1.3 kΩ typ

Output Range 50 to REF_IN–12 50 to REF_IN–12 mV typ
Output Current 10 10 µA max Source Current
Capacitive Load 100 100 pF max

DIGITAL INPUTS

3

Input Current ± 10 ±10 µA max ± 5 µA typ
Input Low Voltage 0.8 0.8 V max DVCC = 5 V ± 5%

0.4 0.4 V max DV

= 3 V ± 10%

CC

Input High Voltage 2.4 2.4 V min DVCC = 5 V ± 5%

2.0 2.0 V min DV

= 3 V ± 10%

CC

Input Hysteresis (SCLK and CS Only) 200 200 mV typ
Input Capacitance 10 10 pF max

DIGITAL OUTPUTS (BUSY, D

OUT

3

)
Output Low Voltage, DVCC = 5 V 0.4 0.4 V max Sinking 200 µA
Output High Voltage, DVCC = 5 V 4.0 4.0 V min Sourcing 200 µA
Output Low Voltage, DV

= 3 V 0.4 0.4 V max Sinking 200 µA

CC

Output High Voltage, DVCC = 3 V 2.4 2.4 V min Sourcing 200 µA
High Impedance Leakage Current ±1 ±1 µA max D
High Impedance Output Capacitance 15 15 pF typ D

OUT

OUT

Only
Only

MIN

–2–

REV. 0

AD5532

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

Parameter

1

POWER REQUIREMENTS

Power-Supply Voltages

V

DD

V

SS

AV

CC

DV

CC

Power-Supply Currents

I

DD

I

SS

6

8/16.5 8/16.5 V min/max
–4.75/–16.5 –4.75/–16.5 V min/max

4.75/5.25 4.75/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max

15 15 mA max 10 mA typ.

15 15 mA max 10 mA typ.

AICC 33 33 mA max 26 mA typ
DICC 1.5 1.5 mA max 1 mA typ

Power Dissipation

AC CHARACTERISTICS

6

3

280 280 mW typ VDD = 10 V, VSS = –5 V

Output Voltage Settling Time 22 30 µs max 500 pF, 5 kΩ Load

OFFS_IN Settling Time 10 20 µs max 500 pF, 5 kΩ Load;

Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around

Digital Crosstalk 5 5 nV-s typ
Analog Crosstalk 1 1 nV-s typ
Digital Feedthrough 0.2 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 400 400 nV/(√Hz) typ

NOTES

1

See Terminology.

2

A Version: Industrial temperature range –40°C to +85°C; typical at +25° C.

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5532.

2

Conditions/

All Channels Full-Scale

All Channels Full-Scale

Full-Scale Change

0 V–3 V Step

Major Carry

5

Ensure that you do not exceed TJ (max). See Maximum Ratings.

6

Output unloaded.

Specifications subject to change without noti

ce.

SHA MODE

Parameter

1

ANALOG CHANNEL

to V

V

IN

Nonlinearity

OUT

3

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

±0.018 ± 0.018 % max ±0.006% typ after Offset and

Offset Error ± 50 ±100 mV max ±10 mV typ. See Figure 7
Gain 3.46/3.52/3.6 6.88/7/7.12 min/typ/max See Figure 7

ANALOG INPUT (V

)

IN

Input Voltage Range 0 to 3 0 to 3 V Nominal Input Range
Input Lower Deadband 70 70 mV max 50 mV typ. Referred to V

Input Upper Deadband 40 40 mV max 12 mV typ. Referred to V

Input Current 1 1 µA max 100 nA typ.

Input Capacitance

4

20 20 pF typ

ANALOG INPUT (OFFS_IN)

Input Current 1 1 µA max 100 nA typ

AC CHARACTERISTICS

Output Settling Time
Acquisition Time 16 16 µs max
AC Crosstalk

NOTES

1

S

ee Terminology.

2

A version: Industrial temperature range –40°C to +85°C; typical at +25°C.

3

Input range 100 mV to 2.96 V.

4

Guaranteed by design and characterization, not production tested.

Specifications subject to change

4

4

without notice.

33 µs max Output Unloaded

5 5 nV-s typ

2

Conditions/

Gain Adjustment

See Figure 7

See Figure 7

V

Acquired on 1 Channel

IN

.

IN

.

IN

REV. 0

–3–

AD5532

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Parameter

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

See Interface Timing Diagram.

2

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
50 ns min CS Pulsewidth Low
50 ns min WR Pulsewidth Low
20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time
0 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time

SERIAL INTERFACE

Parameter

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

4

t

8

4

t

9

t

10

t

11

NOTES

1

See Serial Interface Timing Diagrams.

2

Guaranteed by design and characterization, not production tested.

3

In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.

4

These numbers are measured with the load circuit of Figure 2.

Specifications subject to change without notice.

1, 2

3

Limit at T
(A Version) Unit Conditions/Comments

14 MHz max SCLK Frequency
28 ns min SCLK High Pulsewidth
28 ns min SCLK Low Pulsewidth
10 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time
20 ns max SCLK Rising Edge to D
60 ns max SCLK Falling Edge to D
400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback
400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write

MIN

MIN

, T

, T

MAX

MAX

Valid

OUT

High Impedance

OUT

PARALLEL INTERFACE TIMING DIAGRAMS

CS

WR

A4– A0, CAL,

SEL

OFFS

Figure 1. Parallel Write (SHA Mode Only)

OUTPUT

Figure 2. Load Circuit for D

–4–

TO

PIN

C

L

50pF

200␮A

200␮A

I

OL

1.6V

I

OH

Timing Specifications

OUT

REV. 0

SERIAL INTERFACE TIMING DIAGRAMS

t

1

SCLK

SYNC

D

IN

12345678910

t

3

MSB LSB

t

2

t

4

Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)

t

1

SCLK

SYNC

D

IN

1

t

MSB

2345

t

3

2

t

4

Figure 4. 24-Bit Write (DAC Mode)

AD5532

t

5

t

6

21 22 23 24

t

5

t

6

LSB

t

11

1

SCLK

SYNC

D

OUT

t

1

2

10

t

10

1 34567

t

7

MSB

t

2

t

4

t

8

8

9

10

11

12 13 14

t

9

LSB

Figure 5. 14-Bit Read (Both Readback Modes)

REV. 0

–5–