Analog Devices AD524SE-883B, AD524SD-883B, AD524SD, AD524SCHIPS, AD524CD Datasheet

Precision

AD524

20kV

–INPUT

G = 10

+INPUT

G = 100

G = 1000

RG

2

RG

1

4.44kV

404V

40V

PROTECTION

20kV

20kV

20kV

20kV

20kV

SENSE

REFERENCE

V

b

V

OUT

PROTECTION

a

FEATURES
Low Noise: 0.3 ␮V p-p 0.1 Hz to 10 Hz
Low Nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
Low Offset Voltage: 50 ␮V
Low Offset Voltage Drift: 0.5 ␮V/ⴗC
Gain Bandwidth Product: 25 MHz
Pin Programmable Gains of 1, 10, 100, 1000
Input Protection, Power On–Power Off
No External Components Required
Internally Compensated
MIL-STD-883B and Chips Available
16-Lead Ceramic DIP and SOIC Packages and
20-Terminal Leadless Chip Carriers Available
Available in Tape and Reel in Accordance
with EIA-481A Standard
Standard Military Drawing Also Available

PRODUCT DESCRIPTION

The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu­racy under worst-case operating conditions. An outstanding
combination of high linearity, high common mode rejection, low
offset voltage drift and low noise makes the AD524 suitable for
use in many data acquisition systems.

The AD524 has an output offset voltage drift of less than 25 µV/°C,
input offset voltage drift of less than 0.5 µV/°C, CMR above

90 dB at unity gain (120 dB at G = 1000) and maximum non­linearity of 0.003% at G = 1. In addition to the outstanding dc
specifications, the AD524 also has a 25 kHz gain bandwidth
product (G = 1000). To make it suitable for high speed data
acquisition systems the AD524 has an output slew rate of 5 V/µs
and settles in 15 µs to 0.01% for gains of 1 to 100.

As a complete amplifier the AD524 does not require any exter­nal components for fixed gains of 1, 10, 100 and 1000. For
other gain settings between 1 and 1000 only a single resistor is
required. The AD524 input is fully protected for both power-on
and power-off fault conditions.

The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical “A” grade, the low drift “B” grade and lower

drift, higher linearity “C” grade are specified from –25°C to
+85°C. The “S” grade guarantees performance to specification
over the extended temperature range –55°C to +125°C. Devices

are available in 16-lead ceramic DIP and SOIC packages and a
20-terminal leadless chip carrier.

Instrumentation Amplifier

AD524

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. The AD524 has guaranteed low offset voltage, offset voltage
drift and low noise for precision high gain applications.

2. The AD524 is functionally complete with pin programmable
gains of 1, 10, 100 and 1000, and single resistor program­mable for any gain.

3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset volt­age changes in gain ranging applications.

4. The AD524 is input protected for both power-on and power­off fault conditions.

5. The AD524 offers superior dynamic performance with a gain
bandwidth product of 25 MHz, full power response of 75 kHz
and a settling time of 15 µs to 0.01% of a 20 V step (G = 100).

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD524–SPECIFICATIONS

(@ VS = ⴞ15 V, RL = 2 k⍀ and TA = +25ⴗC unless otherwise noted)

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

GAIN

Gain Equation

(External Resistor Gain

Programming)

Gain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000
Gain Error

Nonlinearity

Gain vs. Temperature

VOLTAGE OFFSET (May be Nulled)

Input Offset Voltage 250 100 50 100 µV

Output Offset Voltage 5 3 2.0 3.0 mV

Offset Referred to the

INPUT CURRENT

Input Bias Current ⴞ50 ⴞ25 ⴞ15 ⴞ50 nA

Input Offset Current ⴞ35 ⴞ15 ⴞ10 ⴞ35 nA

INPUT

Input Impedance

Input Voltage Range

Common-Mode Rejection dc to
60 Hz with 1 kΩ Source Imbalance

OUTPUT RATING

V

DYNAMIC RESPONSE

Small Signal – 3 dB

Slew Rate 5.0 5.0 5.0 5.0 V/µs
Settling Time to 0.01%, 20 V Step

NOISE

Voltage Noise, 1 kHz

R.T.I., 0.1 Hz to 10 Hz

Current Noise

1

G = 1 ⴞ0.05 ⴞ0.03 ⴞ0.02 ⴞ0.05 %
G = 10 ⴞ0.25 ⴞ0.15 ⴞ0.1 ⴞ0.25 %
G = 100 ⴞ0.5 ⴞ0.35 ⴞ0.25 ⴞ0.5 %
G = 1000

G = 1 ±0.01 ±0.005 ±0.003 ±0.01 %
G = 10,100 ±0.01 ±0.005 ±0.003 ±0.01 %
G = 1000 ±0.01 ±0.01 ±0.01 ±0.01 %

G = 1 5555ppm/°C
G = 10 15 10 10 10 ppm/°C
G = 100 35 25 25 25 ppm/°C
G = 1000 100 50 50 50 ppm/°C

vs. Temperature 2 0.75 0.5 2.0 µV/°C
vs. Temperature 100 50 25 50 µV/°C

Input vs. Supply

G = 1 70 75 80 75 dB
G = 10 85 95 100 95 dB
G = 100 95 105 110 105 dB
G = 1000 100 110 115 110 dB

vs. Temperature ±100 ±100 ±100 ±100 pA/°C
vs. Temperature ±100 ±100 ±100 ± 100 pA/°C

Differential Resistance 10
Differential Capacitance 10 10 10 10 pF
Common-Mode Resistance 10
Common-Mode Capacitance 10 10 10 10 pF

2

Max Differ. Input Linear (V

Max Common-Mode Linear (V

G = 1 70 75 80 70 dB
G = 10 90 95 100 90 dB
G = 100 100 105 110 100 dB
G = 1000 110 115 120 110 dB

, R

= 2 kΩ±10 ±10 ±10 ±10 V

OUT

L

G = 1 1111MHz
G = 10 400 400 400 400 kHz
G = 100 150 150 150 150 kHz
G = 1000 25 25 25 25 kHz

G = 1 to 100 15 15 15 15 µs
G = 1000 75 75 75 75 µs

R.T.I. 7777nV/√Hz
R.T.O. 90 90 90 90 nV√Hz

G = 1 15151515µV p-p
G = 10 2222µV p-p
G = 100, 1000 0.3 0.3 0.3 0.3 µV p-p

0.1 Hz to 10 Hz 60 60 60 60 pA p-p

)

DL

)

CM

AD524A AD524B AD524C AD524S



40, 000






R



+ 1

± 20%






G

±

9

9

±10 ±10 ±10 ±10 V

12 V –



G

× V



D

2





40, 000



R





2.0 ⴞ1.0 ⴞ0.5 ⴞ2.0 %






12 V –



+ 1

± 20%






G

9

10

9

10








G

× V



D

2





40, 000






12 V –



+ 1

± 20%

R






G

9

10

9

10








G

× V



D

2





40, 000






R

G

12 V –

10

10



+ 1

± 20%






9

9








G

× V



D

2



Ω
Ω

V

–2–

REV. E

AD524

Model Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

AD524A AD524B AD524C AD524S

SENSE INPUT

R

IN

I

IN

Voltage Range ±10 ±10 ±10 ±10 V
Gain to Output l l 1 l %

REFERENCE INPUT

R

IN

I

IN

Voltage Range ±10 ±10 10 10 V
Gain to Output l 1 l 1 %

20 20 20 20 kΩ ±20%
15 15 15 15 µA

40 40 40 40 kΩ ±20%
15 15 15 15 µA

TEMPERATURE RANGE

Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 –65 +150 °C

POWER SUPPLY

Power Supply Range ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 ⴞ6 ±15 ⴞ18 V
Quiescent Current 3.5 5.0 3.5 5.0 3.5 5.0 3.5 5.0 mA

NOTES

1

Does not include effects of external resistor RG.

2

VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.

at the maximum = 10 V/G.

V

DL

= Actual differential input voltage.

V

D

Example: G = 10, V

= 12 V – (10/2 × 0.50 V) = 9.5 V.

V

CM

Specification subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to
calculate outgoing quality levels.

= 0.50.

D

REV. E –3–

AD524

TOP VIEW

4
5
6
7
8

14

15

16

17

18

1232019

9 10111213

RG

2

INPUT NULL

NC

INPUT NULL

REFERENCE

+INPUT

–INPUTNCRG

1

OUTPUT

–V

S+VS

NC

SENSE

OUTPUT NULL

G = 100

G = 10

SHORT TO
RG

2

FOR

DESIRED
GAIN

OUTPUT

NULL

NC

G = 1000

AD524

NC = NO CONNECT

719

518

–V

S

+V

S

OUTPUT
OFFSET NULL

INPUT

OFFSET NULL

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

l

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 450 mW

Input Voltage

2

(Either Input Simultaneously) |VIN| + |VS| . . . . . . . . <36 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

(D, E) . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

AD524A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

AD524S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead Temperature (Soldering 60 secs) . . . . . . . . . . . . +300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Max input voltage specification refers to maximum voltage to which either input
terminal may be raised with or without device power applied. For example, with ±18

volt supplies max V

is ±18 volts, with zero supply voltage max VIN is ±36 volts.

IN

METALIZATION PHOTOGRAPH

Contact factory for latest dimensions.

Dimensions shown in inches and (mm).

OUTPUT

NULL

RG

–INPUT
+INPUT

RG

OUTPUT

NULL

14 13

15

16

1

1
2

3

2

PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE

G = 100 G = 1000 SENSE

G = 10

4

INPUT

INPUT

NULL

NULL

D-16 AND R-16 16-PIN CERAMIC PACKAGES.

11 10

12

5

0.170 (4.33)

REFERENCE

OUTPUT

9
8

+V

S

0.103
(2.61)

–V

7

S

6

CONNECTION DIAGRAMS

Ceramic (D) and

SOIC (R) Packages

415

514

16

RG

15

OUTPUT NULL

14

OUTPUT NULL

13

G = 10

12

G = 100

11

G = 1000

10

SENSE

9

OUTPUT

–V

OUTPUT
OFFSET NULL

– INPUT

+ INPUT

RG
INPUT NULL
INPUT NULL

REFERENCE

–V
+V

+V

INPUT

OFFSET NULL

2

S
S

S

1

2

3

AD524

4

TOP VIEW

5

(Not to Scale)

6

7

8

Leadless Chip Carrier

1

SHORT TO
RG

FOR

2

DESIRED
GAIN

S

ORDERING GUIDE

Model Temperature Ranges Package Descriptions Package Options

AD524AD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524AE –40°C to +85°C 20-Terminal Leadless Chip Carrier E-20A
AD524AR-16 –40°C to +85°C 16-Lead Gull-Wing SOIC R-16
AD524AR-16-REEL –40°C to +85°C Tape & Reel Packaging 13"
AD524AR-16-REEL7 –40°C to +85°C Tape & Reel Packaging 7"
AD524BD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524BE –40°C to +85°C 20-Terminal Leadless Chip Carrier E-20A
AD524CD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD524SD –55°C to +125°C 16-Lead Ceramic DIP D-16
AD524SD/883B –55°C to +125°C 16-Lead Ceramic DIP D-16
5962-8853901EA* –55°C to +125°C 16-Lead Ceramic DIP D-16
AD524SE/883B –55°C to +125°C 20-Terminal Leadless Chip Carrier E-20A
AD524SCHIPS –55°C to +125°C Die

*

Refer to official DESC drawing for tested specifications.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD524 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

REV. E–4–

LOAD RESISTANCE – V

OUTPUT VOLTAGE SWING – V

p-p

30

20

0

10 100 10k

1k

10

AD524–Typical Characteristics

20

15

10

+258C

INPUT VOLTAGE – 6V

5

0

05 20

SUPPLY VOLTAGE – 6V

10 15

Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1

8.0

6.0

4.0

2.0

QUIESCENT CURRENT – mA

0

05 2010 15

SUPPLY VOLTAGE – 6V

Figure 4. Quiescent Current vs.
Supply Voltage

20

15

10

5

OUTPUT VOLTAGE SWING – 6V

0

05 2010 15

SUPPLY VOLTAGE – 6V

Figure 2. Output Voltage Swing vs.
Supply Voltage

16

14

12

10

8

6

4

2

INPUT BIAS CURRENT – 6nA

0

05 20

SUPPLY VOLTAGE – 6V

10 15

Figure 5. Input Bias Current vs.
Supply Voltage

Figure 3. Output Voltage Swing vs.
Load Resistance

40

30

20

10

0

–10

–20

INPUT BIAS CURRENT – nA

–30

–40

–75 125

–25 25 75

TEMPERATURE – 8C

Figure 6. Input Bias Current vs.
Temperature

16

14

12

10

8

6

4

INPUT BIAS CURRENT – 6nA

2

0

05 2010 15

INPUT VOLTAGE – 6V

Figure 7. Input Bias Current vs. Input
Voltage

0

1

2

3

4

5

FROM FINAL VALUE – mV

OS

6

DV

0 1.0 8.02.0 3.0 4.0 5.0 6.0 7.0

WARM-UP TIME – Minutes

Figure 8. Offset Voltage, RTI, Turn
On Drift

1000

100

10

GAIN – V/V

1

0 10 10M100 1k 10k 100k 1M

FREQUENCY – Hz

Figure 9. Gain vs. Frequency

REV. E

–5–

AD524

FREQUENCY – Hz

VOLT NSD – nV/ Hz

1000

100

0.1
1 10 100k

100 1k 10k

10

1

G = 1

G = 10

G = 100, 1000

G = 1000

–140

G = 1000
G = 100

–120

G = 10

–100

G = 1

–80

–60

CMRR – dB

–40

–20

0

0 10 10M100 1k 10k 100k 1M

FREQUENCY – Hz

Figure 10. CMRR vs. Frequency RTI,
Zero to 1k Source Imbalance

160

140

120

100

80

60

40

20

POWER SUPPLY REJECTION – dB

0

10 100k

100 1k 10k

FREQUENCY – Hz

+VS = 15V dc +

1V p-p SINEWAVE

G = 1000

G = 100

G

= 10

G = 1

Figure 13. Positive PSRR vs.
Frequency

30

p-p

20

10

FULL POWER RESPONSE – V

0

1k 10k 1M100k

G1000 G100 G10

FREQUENCY – Hz

G = 1, 10, 100

BANDWIDTH LIMITED

Figure 11. Large Signal Frequency
Response

160

140

120

100

80

60

40

20

POWER SUPPLY REJECTION – dB

0

10 100k

100 1k 10k

FREQUENCY – Hz

–VS = –15V dc +

1V p-p SINEWAVE

G = 1000

G = 100

G

= 10

G = 1

Figure 14. Negative PSRR vs.
Frequency

10.0

8.0

6.0

4.0

SLEW RATE –V/ms

2.0

0

1 1000

GAIN – V/V

G = 1000

10 100

Figure 12. Slew Rate vs. Gain

Figure 15. RTI Noise Spectral
Density vs. Gain

100k

10k

1000

100

0 1 10k

CURRENT NOISE SPECTRAL DENSITY – fA/ Hz

10 100 1k

FREQUENCY – Hz

Figure 16. Input Current Noise vs.
Frequency

VERTICAL SCALE; 1 DIVISION = 5mV

Figure 17. Low Frequency Noise␣ –
G = 1 (System Gain = 1000)

0.1 – 10Hz

VERTICAL SCALE; 1 DIVISION = 0.1mV

Figure 18. Low Frequency Noise –

G = 1000 (System Gain = 100,000)

0.1 – 10Hz

REV. E–6–

AD524

–12 TO +12

–8 TO +8

–4 TO +4
OUTPUT

STEP – V

+4 TO –4

+8 TO –8

+12 TO –12

020

1% 0.1% 0.01%

1% 0.1% 0.01%

51015

SETTLING TIME – ms

Figure 19. Settling Time Gain = 1

Figure 20. Large Signal Pulse
Response and Settling Time – G =1

–12 TO +12

–8 TO +8

–4 TO +4
OUTPUT

STEP – V

+4 TO –4

+8 TO –8

+12 TO –12

1%

1%

0.1%

0.1%

0.01%

0.01%

–12 TO +12

–8 TO +8

–4 TO +4
OUTPUT

STEP – V

+4 TO –4

+8 TO –8

+12 TO –12

020

0.1% 0.01%

1%

1%

51015

SETTLING TIME – ms

0.1%

0.01%

Figure 21. Settling Time Gain = 10

Figure 22. Large Signal Pulse
Response and Settling Time
G = 10

–12 TO +12

–8 TO +8

–4 TO +4

OUTPUT

STEP – V

+4 TO –4

+8 TO –8

+12 TO –12

080

Figure 25. Settling Time Gain = 1000

1% 0.1% 0.01%

1% 0.1% 0.01%

20 40 60

SETTLING TIME – ms

7010 30 50

02051015

SETTLING TIME – ms

Figure 23. Settling Time Gain = 100

Figure 26. Large Signal Pulse Re­sponse and Settling Time G = 1000

Figure 24. Large Signal Pulse
Response and Settling Time
G = 100

REV. E –7–

AD524

INPUT

20V p-p

11kV

0.1%

100kV

0.1%

0.1%

1kV

100V

0.1%

RG

G = 10

G = 100

G = 1000

RG

10kV

0.01%

+V

1

AD524

2

–V

10kV

1kV

0.1%

10T

V

S

S

OUT

Figure 27. Settling Time Test Circuit

+V

S

V

B

R56

20kV

S

50mA

G100
G1000

C4C3

Q2, Q4

RG

I

2

R52

20kV

A3

R55

20kV

CH

1

SENSE

V

O

REFERENCE

+IN

R53

20kV

R54

20kV

I

4

50mA

CH2, CH3,

CH

4

2

–IN

CH2,

CH3, CH

CH

1

4

50mA

I

3

20kV

Q1, Q3

I

1

50mA

A1 A2

R57

4.44kV

RG

1

404V

40V

–V

Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(R

)) + 1. For a Gain of 1, RG Is an Open Circuit

G

Theory of Operation

The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic con­struction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of R
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant, which impresses
the input voltage across R

.

G

(smaller

G

As RG is reduced to increase the programmed gain, the trans­conductance of the input preamp increases to the transconduct­ance of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 × 10

8

at a programmed gain of 1000, thus
reducing gain-related errors to a negligible 30 ppm. Second, the
gain bandwidth product, which is determined by C3 or C4 and
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/√Hz at
G = 1000.

INPUT PROTECTION

As interface amplifiers for data acquisition systems, instrumen­tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of R

will not adequately protect the inputs from

G

excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) would re­quire over 7k of resistance which would add 10 nV√Hz of noise.
To provide both input protection and low noise a special series
protect FET was used.

A unique FET design was used to provide a bidirectional cur­rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH

, CH

CH

, act as a resistance (≈1 kΩ) in series with the input as

3

4

,

2

before. During an overload in the positive direction, a fourth
channel, CH

, acts as a small resistance (≈3 kΩ) in series with

1

the gate, which draws only the leakage current, and the FET
limits I
the gate current must go through the small FET formed by CH

. When the FET enhances under a negative overload,

DSS

1

and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.

INPUT OFFSET AND OUTPUT OFFSET

Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small­signal high-gain applications that don’t have this capability.

10

100

1000
RG

+V

S

AD712

+V

1/2

G1, 10, 100

100V

s

1mF

1.62MV

1/2

1mF

–V

S

16.2kV

1.82kV

9.09kV

1kV

AD524

DUT

2

–V

S

16.2kV

1mF

G1000

Figure 29. Noise Test Circuit

REV. E–8–

AD524

40,000

2.105

G =

+1 = 20 620%

–V

S

+V

S

AD524

V

OUT

REFERENCE

1kV

RG

1

+INPUT

–INPUT

RG

2

2.105kV

1.5kV

40,000

4000

||4444.44

G =

+1 = 20 617%

G = 10

*R|

G = 10

= 4444.44V

*R|

G = 100

= 404.04V

*R|

G = 1000

= 40.04V

*NOMINAL (620%)

–V

S

+V

S

AD524

V

OUT

REFERENCE

RG

1

+INPUT

–INPUT

RG

2

4kV

RG

2

G = 100

G = 1000

RG

1

R2
5kV

R3

2.26kV

R

L

R1

2.26kV

G =

(R2||40kV) + R1 + R3

(R2||40kV)

(R1 + R2 + R3)||R

L

$ 2kV

G = 10

–V

S

+V

S

AD524

V

OUT

+INPUT

–INPUT

Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is that component
of offset that is directly proportional to gain i.e., input offset as
measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, out­put offset drift is dominant, while at high gains input offset drift
dominates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input­related numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.

By separating these errors, one can evaluate the total error inde­pendent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:

Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain × input error) + output error

As an illustration, a typical AD524 might have a +250 µV out-
put offset and a –50 µV input offset. In a unity gain configura-
tion, the total output offset would be 200 µV or the sum of the

two. At a gain of 100, the output offset would be –4.75 mV or:

+250 µV + 100(–50 µV) = –4.75 mV.

The AD524 provides for both input and output offset adjust­ment. This simplifies very high precision applications and mini­mize offset voltage changes in switched gain applications. In
such applications the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.

For best results R
temperature coefficient. An external R

should be a precision resistor with a low

G

affects both gain accuracy

G

and gain drift due to the mismatch between it and the internal
thin-film resistors. Gain accuracy is determined by the tolerance
of the external R

and the absolute accuracy of the internal resis-

G

tors (±20%). Gain drift is determined by the mismatch of the

temperature coefficient of R

and the temperature coefficient of

G

the internal resistors (– 50 ppm/°C typ).

Figure 31. Operating Connections for G = 20

The second technique uses the internal resistors in parallel with
an external resistor (Figure 32). This technique minimizes the
gain adjustment range and reduces the effects of temperature
coefficient sensitivity.

GAIN

The AD524 has internal high accuracy pretrimmed resistors for
pin programmable gain of 1, 10, 100 and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG

–INPUT

G = 100

G = 1000

+INPUT

together (for G = 1 RG2 is not connected).

2

10kV

INPUT
OFFSET
NULL

RG

G = 10

+V

S

1

AD524

RG

2

–V

S

V

OUT

OUTPUT
SIGNAL
COMMON

Figure 30. Operating Connections for G = 100

The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between pins 3
and 16, which programs the gain according to the formula

(see Figure 31).

REV. E –9–

40k

R

=

G

G =–1

Figure 32. Operating Connections for G = 20, Low Gain
T.C. Technique

The AD524 may also be configured to provide gain in the out­put stage. Figure 33 shows an H pad attenuator connected to
the reference and sense lines of the AD524. R1, R2 and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 will precisely set the gain
without affecting CMRR. CMRR is determined by the match of
R1 and R3.

Figure 33. Gain of 2000

AD524

V

OUT

REFERENCE

AD524

–V

S

+V

S

100V

AD711

G = 100

RG

2

+INPUT

–INPUT

V

OUT

REFERENCE

AD524

–V

S

+V

S

100V

AD712

RG

2

+INPUT

–INPUT

–V

S

RG

1

100V

Table I. Output Gain Resistor Values

Output Nominal
Gain R2 R1, R3 Gain

25 kΩ 2.26 kΩ 2.02
5 1.05 kΩ 2.05 kΩ 5.01
10 1 kΩ 4.42 kΩ 10.1

INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. Bias currents are an additional
source of input error and must be considered in a total error
budget. The bias currents, when multiplied by the source resis­tance, appear as an offset voltage. What is of concern in calculat­ing bias current errors is the change in bias current with respect to
signal voltage and temperature. Input offset current is the differ­ence between the two input bias currents. The effect of offset
current is an input offset voltage whose magnitude is the offset
current times the source impedance imbalance.

+V

S

AD524

LOAD

–V

S

TO POWER
SUPPLY
GROUND

a. Transformer Coupled

Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents will charge stray capacitances, causing
the output to drift uncontrollably or to saturate. Therefore,
when amplifying “floating” input sources such as transformers
and thermocouples, as well as ac-coupled sources, there must
still be a dc path from each input to ground.

COMMON-MODE REJECTION

Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. “Common-Mode
Rejection Ratio” (CMRR) is a ratio expression while “Common­Mode Rejection” (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.

In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due to
varied stray capacitances or cable capacitances. In many appli­cations shielded cables are used to minimize noise. This tech­nique can create common mode rejection errors unless the
shield is properly driven. Figures 35 and 36 shows active data
guards that are configured to improve ac common mode rejec­tion by “bootstrapping” the capacitances of the input cabling,
thus minimizing differential phase shift.

+V

S

AD524

LOAD

–V

S

b. Thermocouple

+V

S

AD524

LOAD

–V

S

c. AC Coupled

Figure 34. Indirect Ground Returns for Bias Currents

TO POWER
SUPPLY
GROUND

TO POWER
SUPPLY
GROUND

Figure 35. Shield Driver, G ≥ 100

Figure 36. Differential Shield Driver

GROUNDING

Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the sys­tem power-supply ground. Ideally, a single solid ground would
be desirable. However, since current flows through the ground
wires and etch stripes of the circuit cards, and since these paths
have resistance and inductance, hundreds of millivolts can be
generated between the system ground point and the data

REV. E–10–

AD524

AD524

REF

SENSE

LOAD

AD711

+INPUT

–INPUT

R1

V

X

I

L

V

X

R1

I

L

= =

= (1 +

V

IN

R1

)

40,000

R

G

A2

acquisition components. Separate ground returns should be
provided to minimize the current flow in the path from the sensi­tive points to the system ground point. In this way supply currents
and logic-gate return currents are not summed into the same
return path as analog signals where they would cause measure­ment errors.

Since the output voltage is developed with respect to the poten­tial on the reference terminal, an instrumentation amplifier can
solve many grounding problems.

DIG
COM

DIGITAL P.S.

+5V

C–15V

1mF

1mF1mF

AD574A

SIGNAL
GROUND

DIGITAL
DATA
OUTPUT

AD524

OUTPUT

REFERENCE

ANALOG P.S.

C+15V

0.1mF0.1
mF

6

*IF INDEPENDENT; OTHERWISE RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON

0.1mF0.1

AND HOLD

*ANALOG

GROUND

mF

AD583

SAMPLE

Figure 37. Basic Grounding Practice

SENSE TERMINAL

The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load, thus putting
the IxR drops “inside the loop” and virtually eliminating this
error source.

V+

(SENSE)

OUTPUT

(REF)

CURRENT
BOOSTER

X1

R

L

VIN+

V

IN

AD524

–

V–

Figure 38. AD524 Instrumentation Amplifier with Output
Current Booster

Typically, IC instrumentation amplifiers are rated for a full ±10
volt output swing into 2 kΩ. In some applications, however, the

need exists to drive more current into heavier loads. Figure 38
shows how a high-current booster may be connected “inside the
loop” of an instrumentation amplifier to provide the required
current boost without significantly degrading overall perfor­mance. Nonlinearities, offset and gain inaccuracies of the buffer
are minimized by the loop gain of the IA output amplifier. Off­set drift of the buffer is similarly reduced.

REV. E –11–

REFERENCE TERMINAL

The reference terminal may be used to offset the output by up

to ±10 V. This is useful when the load is “floating” or does not

share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. It must be remem-

bered that the total output swing is ±10 volts to be shared be-

tween signal and reference offset.

When the IA is of the three-amplifier configuration it is neces­sary that nearly zero impedance be presented to the reference
terminal.

Any significant resistance from the reference terminal to ground
increases the gain of the noninverting signal path, thereby upset­ting the common-mode rejection of the IA.

In the AD524 a reference source resistance will unbalance the

CMR trim by the ratio of 20 kΩ/R

. For example, if the refer-

REF

ence source impedance is 1 Ω, CMR will be reduced to 86 dB
(20 kΩ/1 Ω = 86 dB). An operational amplifier may be used to

provide that low impedance reference point as shown in Figure

39. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.

+V

S

VIN+

SENSE

AD524

–

V

IN

REF

–V

S

AD711

LOAD

V

OFFSET

Figure 39. Use of Reference Terminal to Provide Output
Offset

An instrumentation amplifier can be turned into a voltage-to­current converter by taking advantage of the sense and reference
terminals as shown in Figure 40.

Figure 40. Voltage-to-Current Converter

By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A
forced current I
drift specifications of A

will largely flow through the load. Offset and

L

must be added to the output offset and

2

, the

2

drift specifications of the IA.

AD524

R2
10kV

1mF
35V

–V

S

OUTPUT
OFFSET
NULL

+V

S

TO –V

AD524

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

20kV

20kV

20kV

404V

4.44kV

20kV

+V

S

20kV

20kV

40V

PROTECTION

PROTECTION

–IN

+IN

(+INPUT)

(–INPUT)

10kV

INPUT

OFFSET

NULL

10pF

20kV

AD711

–V

S

+V

S

AD7590

V

SS

V

DD

GND

39.2kV

28.7kV
316kV

1kV
1kV

1kV

V

DD

A2 A3

A4

WR

V

OUT

–IN

+IN

–V

+V

ANALOG

COMMON

1

PROTECTION

2

PROTECTION

INPUT

OFFSET

TRIM

S

S

1mF
35V

C1

GAIN TABLE

A

B

0

0

0

1

1

0

1

1

C2

3

4

R1
10kV

5

6

7

8

K1 – K3 =
THERMOSEN DM2C

4.5V COIL
D1 – D3 = IN4148

GAIN
10

1000
100
1

20kV

20kV

AD524

A1

20kV

+V

S

20kV

20kV

20kV

INPUTS

GAIN

RANGE

16

15

14

4.44kV
13

404V

12

40V

11

10

9

A
B

+5V

NC = NO CONNECT

R2

10kV

OUT

74LS138

DECODER

OUTPUT
OFFSET
TRIM

SHIELDS

NC

RELAY

Y0
Y1
Y2

G = 10

K1

G = 100

K1

K2

G = 1000

K3

+5V

K3D1

D2

K2

7407N

BUFFER

DRIVER

D3

10mF

LOGIC
COMMON

Figure 41. Three Decade Gain Programmable Amplifier

PROGRAMMABLE GAIN

Figure 41 shows the AD524 being used as a software program­mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It
should be noted that the “on” resistance of the switch in series
with the internal gain resistor becomes part of the gain equation
and will have an effect on gain accuracy.

The AD524 can also be connected for gain in the output stage.
Figure 42 shows an AD711 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation pre­sents a very low impedance to the feedback resistors, therefore
minimizing the common-mode rejection ratio degradation.

Figure 42. Programmable Output Gain

REV. E–12–

AD524

WR

CS

+INPUT

G = 10

–INPUT

G = 100

G = 1000

RG

2

RG

1

+V

S

AD7524

+V

S

–V

S

–V

S

+V

S

OUT2

39kV

AD589

MSB

LSB

DATA

INPUTS

–V

S

1/2

AD712

1/2

AD712

R3
20kV

R4

10kV

R6

5kV

C1

GND

R5

20kV

OUT1

V

REF

AD524

RG

2

RG

1

+V

S

–V

S

8

AD524

15 16

14

13

V

DD

GND

0.1mF LOW
LEAKAGE

10

CH

1kV

V

OUT

910

A1 A2 A3 A4

200ms

V

SS

ZERO PULSE

AD7510KD

AD711

11

12

+INPUT

(–INPUT)

G = 10

G = 100

G = 1000

–INPUT

(+INPUT)

DAC A/DAC B

RG
RG

1

13
12
11
16

1

3

2

2

DATA

INPUTS

PROTECTION

4.44kV
404V

40V

PROTECTION

CS

WR

AD524

V

b

20kV

20kV

+V

S

17

3

4

14

7
15
16

6
18

DAC A

DB0

DB7

AD7528

DAC B

5

20kV

20kV

20kV

10

9

6

20kV

1/2

AD712

2

1/2

AD712

256:1

1

19
20

V

OUT

Figure 43. Programmable Output Gain Using a DAC

Another method for developing the switching scheme is to use a
DAC. The AD7528 dual DAC, which acts essentially as a pair
of switched resistive attenuators having high analog linearity and
symmetrical bipolar transmission, is ideal in this application.
The multiplying DAC’s advantage is that it can handle inputs of
either polarity or zero without affecting the programmed gain.
The circuit shown uses an AD7528 to set the gain (DAC A) and
to perform a fine adjustment (DAC B).

Figure 44. Software Controllable Offset

In many applications complex software algorithms for autozero
applications are not available. For those applications Figure 45
provides a hardware solution.

AUTOZERO CIRCUITS

In many applications it is necessary to provide very accurate
data in high gain configurations. At room temperature the offset
effects can be nulled by the use of offset trimpots. Over the
operating temperature range, however, offset nulling becomes a
problem. The circuit of Figure 44 show a CMOS DAC operat­ing in the bipolar mode and connected to the reference terminal
to provide software controllable offset adjustments.

REV. E –13–

Figure 45. Autozero Circuit

AD524

ERROR BUDGET ANALYSIS

To illustrate how instrumentation amplifier specifications are
applied, we will now examine a typical case where an AD524 is
required to amplify the output of an unbalanced transducer.

Figure 46 shows a differential transducer, unbalanced by 100 Ω,

supplying a 0 to 20 mV signal to an AD524C. The output of the
IA feeds a 14-bit A-to-D converter with a 0 to 2 volt input volt-

age range. The operating temperature range is –25°C to +85°C.
Therefore, the largest change in temperature ∆T within the
operating range is from ambient to +85°C (85°C – 25°C = 60°C).

+10V

350V

350V350V

350V

RG

G = 100

RG

1

2

Figure 46. Typical Bridge Application

Table II. Error Budget Analysis of AD524CD in Bridge Application

In many applications, differential linearity and resolution are of
prime importance. This would be so in cases where the absolute
value of a variable is less important than changes in value. In
these applications, only the irreducible errors (45 ppm = 0.004%)
are significant. Furthermore, if a system has an intelligent pro­cessor monitoring the A-to-D output, the addition of a auto­gain/autozero cycle will remove all reducible errors and may
eliminate the requirement for initial calibration. This will also
reduce errors to 0.004%.

+V

S

10kV

14-BIT

AD524C

–V

S

ADC

0V TO 2V

F.S.

Effect on Effect on
Absolute Absolute Effect

AD524C Accuracy Accuracy on

Error Source Specifications Calculation at TA = +25ⴗC at TA = +85ⴗC Resolution

Gain Error ±0.25% ±0.25% = 2500 ppm 2500 ppm 2500 ppm –
Gain Instability 25 ppm (25 ppm/°C)(60°C) = 1500 ppm – 1500 ppm –
Gain Nonlinearity ±0.003% ±0.003% = 30 ppm – – 30 ppm
Input Offset Voltage ±50 µV, RTI ±50 µV/20 mV = ±2500 ppm 2500 ppm 2500 ppm –
Input Offset Voltage Drift ±0.5 µV/°C(±0.5 µV/°C)(60°C) = 30 µV

– 30 µV/20 mV = 1500 ppm – 1500 ppm –
Output Offset Voltage* ±2.0 mV ±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm –
Output Offset Voltage Drift* ±25 µV/°C(±25 µV/°C)(60°C)= 1500 µV

1500 µV/20 mV = 750 ppm – 750 ppm –
Bias Current-Source ±15 nA (±15 nA)(100 Ω) = 1.5 µV
Imbalance Error 1.5 µV/20 mV = 75 ppm 75 ppm 75 ppm –
Bias Current-Source ±100 pA/°C(±100 pA/°C)(100 Ω)(60°C) = 0.6 µV
Imbalance Drift 0.6 µV/20 mV= 30 ppm – 30 ppm –
Offset Current-Source ±10 nA (±10 nA)(100 Ω) = 1 µV
Imbalance Error 1 µV/20 mV = 50 ppm 50 ppm 50 ppm –
Offset Current-Source ±100 pA/°C (100 pA/°C)(100 Ω)(60°C) = 0.6 µV
Imbalance Drift 0.6 µV/20 mV = 30 ppm – 30 ppm –
Offset Current-Source ±10 nA (10 nA)(175 Ω) = 3.5 µV
Resistance-Error 3.5 µV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm –
Offset Current-Source ±100 pA/°C (100 pA/°C)(175 Ω)(60°C) = 1 µV
Resistance-Drift 1 µV/20 mV = 50 ppm – 50 ppm –
Common Mode Rejection 115 dB 115 dB = 1.8 ppm × 5 V = 8.8 µV
5 V dc 8.8 µV/20 mV = 444 ppm 444 ppm 444 ppm –

Noise, RTI

(0.1 Hz–10 Hz) 0.3 µV p-p 0.3 µV p-p/20 mV = 15 ppm – – 15 ppm

Total Error 6656.5 ppm 10516.5 ppm 45 ppm

*Output offset voltage and output offset voltage drift are given as RTI figures.

REV. E–14–

AD524

Figure 47 shows a simple application, in which the variation of
the cold-junction voltage of a Type J thermocouple-iron(+)–
constantan–is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590 semi­conductor temperature sensor.

R

A

NOMINAL

TYPE

J
K
E
T

S, R

MEASURING

JUNCTION

VALUE

52.3V

41.2V

61.4V

40.2V

5.76V

REFERENCE
JUNCTION

+158C < TA < +358C

IRON

V

CONSTANTAN

T

EO = VT – VA +

≅ V

T

+V

S

I

+ 2.5V

A

52.3V
R

A

AD590

CU

– 2.5V

T

A

V

A

52.3VI
1 +

7.5V

2.5V

AD580

R

A

E

O

52.3V

8.66kV

R

T

1kV

NOMINAL VALUE

9135V

G = 100

+V

S

–V

S

OUTPUT
AMPLIFIER
OR METER

AD524

Figure 47. Cold-Junction Compensation

The circuit is calibrated by adjusting RT for proper output voltage
with the measuring junction at a known reference temperature

and the circuit near 25°C. If resistors with low tempcos are
used, compensation accuracy will be to within ±0.5°C, for
temperatures between +15°C and +35°C. Other thermocouple

types may be accommodated with the standard resistance values
shown in the table. For other ranges of ambient temperature,
the equation in the figure may be solved for the optimum values

and RA.

of R

T

The microprocessor controlled data acquisition system shown in
Figure 48 includes both autozero and autogain capability. By
dedicating two of the differential inputs, one to ground and one
to the A/D reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The autozero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8-bit) to the AD7524, which eliminates the zero error
since its output has an inverted scale. The autogain cycle con­verts the A/D reference and compares it with full scale. A multi­plicative correction factor is then computed and applied to
subsequent readings.

For a comprehensive study of instrumentation amplifier design
and applications, refer to the Instrumentation Amplifier Applica-
tion Guide, available free from Analog Devices.

V

AD7507

A0 A2

EN A1

LATCH

RG

2

RG

1

20kV

1/2

AD712

AD524

10kV

AD712

5kV

ADDRESS BUS

20kV

1/2

ADDRESS BUS

AD583

–V

REF

AD7524

DECODE

V

N

I

AGND

AD574A

CONTROL

REF

PROCESSOR

MICRO-

Figure 48. Microprocessor Controlled Data Acquisition System

REV. E –15–

AD524

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Ceramic DIP

(D-16)

0.005 (0.13) MIN

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.358 (9.09)

0.342 (8.69)
SQ

TOP

VIEW

0.080 (2.03) MAX

16

1

0.840 (21.34) MAX

0.023 (0.58)

0.014 (0.36)

PIN 1

0.100

(2.54)

BSC

9

8

0.070 (1.78)

0.030 (0.76)

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MAX

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

20-Terminal Leadless Chip Carrier

(E-20A)

0.200 (5.08)
BSC

REF

0.055 (1.40)

0.045 (1.14)

0.075
(1.91)

REF

19

18

14

13

20

1

BOTTOM

VIEW

0.150 (3.81)

4

8

BSC

0.100 (2.54)

0.064 (1.63)

0.358

(9.09)

MAX

SQ

0.088 (2.24)

0.054 (1.37)

0.095 (2.41)

0.075 (1.90)

0.011 (0.28)

0.007 (0.18)
R TYP

0.075 (1.91)

0.015 (0.38)

0.008 (0.20)

0.100 (2.54) BSC

0.015 (0.38)

3

MIN

0.028 (0.71)

0.022 (0.56)

0.050 (1.27)
BSC

9

45° TYP

C722e–0–4/99

0.0118 (0.30)

0.0040 (0.10)

16-Lead SOIC

0.4133 (10.50)

0.3977 (10.00)

16 9

PIN 1

0.0500

0.0192 (0.49)

(1.27)

0.0138 (0.35)

BSC

(R-16)

0.2992 (7.60)

81

0.1043 (2.65)

0.0926 (2.35)

SEATING
PLANE

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8°
0°

0.0157 (0.40)

x 45°

PRINTED IN U.S.A.

REV. E–16–