ANALOG DEVICES AD5242 Service Manual

I2C® Compatible

www.BDTIC.com/ADI

a

256-Position Digital Potentiometers

FEATURES
256 Positions
10 k, 100 k, 1 M
Low Tempco 30 ppm/C
Internal Power ON Midscale Preset
Single-Supply 2.7 V to 5.5 V or

Dual-Supply 2.7 V for AC or Bipolar Operation

2

C Compatible Interface with Readback Capability

I
Extra Programmable Logic Outputs
Self-Contained Shutdown Feature
Extended Temperature Range –40C to +105C

APPLICATIONS
Multimedia, Video, and Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5241/AD5242 provide a single-/dual-channel, 256­position, digitally controlled variable resistor (VR) device. These
devices perform the same electronic adjustment function as a
potentiometer, trimmer, or variable resistor. Each VR offers a
completely programmable value of resistance between the A
Terminal and the wiper, or the B Terminal and the wiper.
For AD5242, the fixed A-to-B terminal resistance of 10 kΩ,
100 kΩ, or 1 MΩ has a 1% channel-to-channel matching
tolerance. The nominal temperature coefficient of both parts is
30 ppm/°C.

Wiper position programming defaults to midscale at system
power ON. Once powered, the VR wiper position is programmed

2

by an I

C compatible 2-wire serial data interface. Both parts
have available two extra programmable logic outputs that
enable users to drive digital loads, logic gates, LED drivers, and
analog switches in their system.

The AD5241/AD5242 are available in surface-mount (SOIC-14/-

16) packages and, for ultracompact solutions, TSSOP-14/-16
packages. All parts are guaranteed to operate over the
extended temperature range of –40°C to +105°C. For 3-wire,
SPI compatible interface applications, please refer to AD5200,
AD5201, AD5203, AD5204, AD5206, AD5231*, AD5232*,
AD5235*, AD7376, AD8400, AD8402, and AD8403 products.

SHDN

V

V

SDA
SCL

GND

AD5241/AD5242

FUNCTIONAL BLOCK DIAGRAM

A

1W1B1

SHDN

DD

SS

V

V

SDA
SCL

GND

DD

SS

DECODE

RDAC

REGISTER 1

ADDR

DECODE

SERIAL INPUT REGISTER

AD0

A

W1B

1

RDAC

REGISTER 1

ADDR

AD5242

1

SERIAL INPUT REGISTER

AD0

AD5241

8

AD1

AD1

A2W2B

REGISTER 2

8

RDAC

1

O1O

2

REGISTER 2

PWR-ON

RESET

2

PWR-ON

REGISTER

RESET

O

2O1

*Nonvolatile digital potentiometer
I2C is a registered trademark of Philips Corporation.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD5241/AD5242–SPECIFICATIONS

www.BDTIC.com/ADI

(VDD = 3 V  10% or 5 V  10%, VA = +VDD, VB = 0 V, –40C < TA < +105C, unless

10 k, 100 k, 1 M VERSION

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS, RHEOSTAT MODE (Specifications apply to all VRs.)

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance DR T

Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity

3

3

Voltage Divider Temperature

Coefficient DV
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

4

5

A, B C

5

WC

Common-Mode Leakage I

DIGITAL INPUTS

Input Logic High (SDA and SCL) V
Input Logic Low (SDA and SCL) V
Input Logic High (AD0 and AD1) V
Input Logic Low (AD0 and AD1) V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

DIGITAL OUTPUT V

Output Logic Low (SDA) V
Output Logic Low (O
Output Logic High (O
Three-State Leakage Current (SDA) I
Output Capacitance

and O2)VOLI

1

and O2)V

1

5

POWER SUPPLIES

Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

6

Power Supply Sensitivity PSS –0.01 +0.002 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 80

Total Harmonic Distortion THD

V

Settling Time t

W

Resistor Noise Voltage e

2

2

R-DNL RWB, VA = No Connect –1 ±0.4 +1 LSB
R-INL RWB, VA = No Connect –2 ±0.5 +2 LSB

DR T

/DT VAB = VDD, Wiper = No Connect 30 ppm/°C

AB

W

DNL –1 ±0.4 +1 LSB
INL –2 ±0.5 +2 LSB

W

WFSE

WZSE

V

A, B, W

A, B

W

CM

IH

IL

IH

IL

IH

IL

IL

C

IL

OL

OL

OH

OZ

C

OZ

DD RANGEVSS

DD/SS RANGE

DD

SS

P

DISS

5, 7, 8

BW_100 kΩ R
BW_1 MΩ R

S

N_WB

otherwise noted.)

= 25°C, RAB = 10 kΩ –30 +30 %

A

= 25°C, RAB = 100 kΩ/1 MΩ –30 +50 %

A

IW = VDD /R, VDD = 3 V or 5 V 60 120 Ω

/DT Code = 80

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
VA = VB = V

VDD = 5 V 2.4 V
VDD = 5 V 0 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0 0.6 V
VIN = 0 V or 5 V 1 µA

IOL = 3 mA 0.4 V
IOL = 6 mA 0.6 V

= 1.6 mA 0.4 V

SINK

I

= 40 µA4V

SOURCE

VIN = 0 V or 5 V ±1 µA

= 0 V 2.7 5.5 V

±2.3 ±2.7 V
VIH = 5 V or VIL = 0 V 0.1 50 µA
VSS = –2.5 V, VDD = +2.5 V +0.1 –50 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 0.5 250 µW

= 100 kΩ, Code = 80

AB

= 1 MΩ, Code = 80

AB

W

VA = 1 V rms + 2 V dc, 0.005 %

= 2 V dc, f = 1 kHz

V

B

VA = VDD, VB = 0 V, ±1 LSB Error Band, 2 µs

= 10 kΩ

R

AB

RWB = 5 kΩ, f = 1 kHz 14 nV√Hz

H

H

H

H

H

W

5 ppm/°C

–1 –0.5 0 LSB
0 0.5 1 LSB

V

SS

V

DD

V
45 pF
60 pF
1nA

0.7 V

DD

VDD + 0.5 V

–0.5 +0.3 VDDV

DD

DD

V

V

3pF

38 pF

H

H

H

650 kHz
69 kHz
6 kHz

–2–

REV. B

AD5241/AD5242

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1Max Unit

5, 9

INTERFACE TIMING CHARACTERISTICS (Applies to all parts.

SCL Clock Frequency f
t

Bus Free Time between t

BUF

SCL

1

STOP and START

Hold Time (Repeated START) t

t

HD; STA

2

After this period, the first clock 600 ns
pulse is generated.

Low Period of SCL Clock t

t

LOW

High Period of SCL Clock t

t

HIGH

t

Setup Time for Repeated

SU; STA

START Condition t
t
t
t

Data Hold Time t

HD; DAT

Data Setup Time t

SU; DAT

Rise Time of Both t

R

3

4

5

6

7

8

SDA and SCL Signals

Fall Time of Both SDA and SCL Signals t

t

F

t

Setup Time for STOP Condition t

SU; STO

NOTES

1

Typicals represent average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10.

4

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band­width. The highest R value results in the minimum overall power consumption.

8

All dynamic characteristics use VDD = 5 V.

9

See timing diagram for location of measured values.

Specifications subject to change without notice.

9

10

)

0 400 kHz

1.3 µs

1.3 µs

0.6 50 µs

600 ns

900 ns

100 ns

300 ns

300 ns

= VDD and VB = 0 V.

A

REV. B

–3–

AD5241/AD5242

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V , –7 V

V

SS

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

A

AX–BX, AX–WX, BX–WX at 10 kΩ in TSSOP-14 . . . ±5.0 mA
AX–BX, AX–WX, BX–WX at 100 kΩ in TSSOP-14 . . ± 1.5 mA
AX–BX, AX–WX, BX–WX at 1 MΩ in TSSOP-14 . . . ±0.5 mA

Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . –40°C to +105°C

*

Thermal Resistance θ

JA

SOIC (SOIC-14) . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

SOIC (SOIC-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W

Maximum Junction Temperature (T

DD

Package Power Dissipation P

*

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

*

Lead Temperatures

*

R-14, R-16A, RU-14, RU-16 (Vapor Phase, 60 sec) . 215°C

D

max) . . . . . . . . . . 150°C

J

= (TJmax – TA)/θ

JA

R-14, R-16A, RU-14, RU-16 (Infrared, 15 sec) . . . . . 220°C

*Max current increases at lower resistance and different packages.

ORDERING GUIDE

Number of

Number of End to End Temperature Package Package Devices per

Model Channels RAB () Range (C) Description Option Container

AD5241BR10 1 10 k –40 to +105 SOIC-14 R-14 56
AD5241BR10-REEL7 1 10 k –40 to +105 SOIC-14 R-14 1000
AD5241BRU10-REEL7 1 10 k –40 to +105 TSSOP-14 RU-14 1000
AD5241BR100 1 100 k –40 to +105 SOIC-14 R-14 56
AD5241BR100-REEL7 1 100 k –40 to +105 SOIC-14 R-14 1000
AD5241BRU100-REEL7 1 100 k –40 to +105 TSSOP-14 RU-14 1000
AD5241BR1M 1 1 M –40 to +105 SOIC-14 R-14 56
AD5241BRU1M-REEL7 1 1 M –40 to +105 TSSOP-14 RU-14 1000
AD5242BR10 2 10 k –40 to +105 SOIC-16 R-16A 48
AD5242BR10-REEL7 2 10 k –40 to +105 SOIC-16 R-16A 1000
AD5242BRU10-REEL7 2 10 k –40 to +105 TSSOP-16 RU-16 1000
AD5242BR100 2 100 k –40 to +105 SOIC-16 R-16A 48
AD5242BR100-REEL7 2 100 k –40 to +105 SOIC-16 R-16A 1000
AD5242BRU100-REEL7 2 100 k –40 to +105 TSSOP-16 RU-16 1000
AD5242BR1M 2 1 M –40 to +105 SOIC-16 R-16A 48
AD5242BRU1M-REEL7 2 1 M –40 to +105 TSSOP-16 RU-16 1000

NOTES

1

The AD5241/AD5242 die size is 69 mil × 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5495245 applies.

2

TSSOP packaged units are only available in 1,000-piece quantity Tape and Reel.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5241/AD5242 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. B

AD5241/AD5242

TOP VIEW

(Not to Scale)

1

O

1

A

1

W

1

B

1

V

DD

SHDN

SCL

SDA

A

2

W

2

B

2

O

2

V

SS

DGND

AD1

AD0

AD5242

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

www.BDTIC.com/ADI

AD5241 PIN CONFIGURATION

1

A

1

2

W

1

3

B

1

4

V

DD

5

SHDN

6

SCL

7

SDA

NC = NO CONNECT

AD5241

TOP VIEW

(Not to Scale)

14

13

12

11

10

9

8

O

1

NC

O

2

V

SS

DGND

AD1

AD0

AD5241 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1A
2W
3B
4V

1

1

1

DD

Resistor Terminal A
Wiper Terminal W
Resistor Terminal B

1

1

1

Positive power supply, specified for opera­tion from 2.2 V to 5.5 V.

5 SHDN Active low, asynchronous connection of

Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to VDD if

not used.
6 SCL Serial Clock Input
7 SDA Serial Data Input/Output
8AD0 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
9AD1 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
10 DGND Common Ground
11 V

SS

Negative power supply, specified for

operation from 0 V to –2.7 V.
12 O

2

Logic Output Terminal O

2

13 NC No Connect
14 O

1

Logic Output Terminal O

1

AD5242 PIN CONFIGURATION

AD5242 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1O
2A
3W
4B
5V

1

1

1

1

DD

Logic Output Terminal O
Resistor Terminal A
Wiper Terminal W
Resistor Terminal B

1

1

1

1

Positive power supply, specified for opera­tion from 2.2 V to 5.5 V.

6 SHDN Active low, asynchronous connection of

Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to VDD if

not used.
7 SCL Serial Clock Input
8 SDA Serial Data Input/Output
9 AD0 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
10 AD1 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
11 DGND Common Ground
12 V

SS

Negative power supply, specified for

operation from 0 V to –2.7 V.
13 O
14 B
15 W
16 A

2

2

2

2

Logic Output Terminal O

Resistor Terminal B

Wiper Terminal W

Resistor Terminal A

2

2

2

2

REV. B

–5–