ANALOG DEVICES AD5242 Service Manual

I2C® Compatible

www.BDTIC.com/ADI

a

256-Position Digital Potentiometers

FEATURES
256 Positions
10 k, 100 k, 1 M
Low Tempco 30 ppm/C
Internal Power ON Midscale Preset
Single-Supply 2.7 V to 5.5 V or

Dual-Supply 2.7 V for AC or Bipolar Operation

2

C Compatible Interface with Readback Capability

I
Extra Programmable Logic Outputs
Self-Contained Shutdown Feature
Extended Temperature Range –40C to +105C

APPLICATIONS
Multimedia, Video, and Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5241/AD5242 provide a single-/dual-channel, 256­position, digitally controlled variable resistor (VR) device. These
devices perform the same electronic adjustment function as a
potentiometer, trimmer, or variable resistor. Each VR offers a
completely programmable value of resistance between the A
Terminal and the wiper, or the B Terminal and the wiper.
For AD5242, the fixed A-to-B terminal resistance of 10 kΩ,
100 kΩ, or 1 MΩ has a 1% channel-to-channel matching
tolerance. The nominal temperature coefficient of both parts is
30 ppm/°C.

Wiper position programming defaults to midscale at system
power ON. Once powered, the VR wiper position is programmed

2

by an I

C compatible 2-wire serial data interface. Both parts
have available two extra programmable logic outputs that
enable users to drive digital loads, logic gates, LED drivers, and
analog switches in their system.

The AD5241/AD5242 are available in surface-mount (SOIC-14/-

16) packages and, for ultracompact solutions, TSSOP-14/-16
packages. All parts are guaranteed to operate over the
extended temperature range of –40°C to +105°C. For 3-wire,
SPI compatible interface applications, please refer to AD5200,
AD5201, AD5203, AD5204, AD5206, AD5231*, AD5232*,
AD5235*, AD7376, AD8400, AD8402, and AD8403 products.

SHDN

V

V

SDA
SCL

GND

AD5241/AD5242

FUNCTIONAL BLOCK DIAGRAM

A

1W1B1

SHDN

DD

SS

V

V

SDA
SCL

GND

DD

SS

DECODE

RDAC

REGISTER 1

ADDR

DECODE

SERIAL INPUT REGISTER

AD0

A

W1B

1

RDAC

REGISTER 1

ADDR

AD5242

1

SERIAL INPUT REGISTER

AD0

AD5241

8

AD1

AD1

A2W2B

REGISTER 2

8

RDAC

1

O1O

2

REGISTER 2

PWR-ON

RESET

2

PWR-ON

REGISTER

RESET

O

2O1

*Nonvolatile digital potentiometer
I2C is a registered trademark of Philips Corporation.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD5241/AD5242–SPECIFICATIONS

www.BDTIC.com/ADI

(VDD = 3 V  10% or 5 V  10%, VA = +VDD, VB = 0 V, –40C < TA < +105C, unless

10 k, 100 k, 1 M VERSION

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS, RHEOSTAT MODE (Specifications apply to all VRs.)

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance DR T

Resistance Temperature Coefficient R
Wiper Resistance R

DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)

Resolution N 8 Bits
Differential Nonlinearity
Integral Nonlinearity

3

3

Voltage Divider Temperature

Coefficient DV
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

4

5

A, B C

5

WC

Common-Mode Leakage I

DIGITAL INPUTS

Input Logic High (SDA and SCL) V
Input Logic Low (SDA and SCL) V
Input Logic High (AD0 and AD1) V
Input Logic Low (AD0 and AD1) V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

5

DIGITAL OUTPUT V

Output Logic Low (SDA) V
Output Logic Low (O
Output Logic High (O
Three-State Leakage Current (SDA) I
Output Capacitance

and O2)VOLI

1

and O2)V

1

5

POWER SUPPLIES

Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation

6

Power Supply Sensitivity PSS –0.01 +0.002 +0.01 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10 kΩ RAB = 10 kΩ, Code = 80

Total Harmonic Distortion THD

V

Settling Time t

W

Resistor Noise Voltage e

2

2

R-DNL RWB, VA = No Connect –1 ±0.4 +1 LSB
R-INL RWB, VA = No Connect –2 ±0.5 +2 LSB

DR T

/DT VAB = VDD, Wiper = No Connect 30 ppm/°C

AB

W

DNL –1 ±0.4 +1 LSB
INL –2 ±0.5 +2 LSB

W

WFSE

WZSE

V

A, B, W

A, B

W

CM

IH

IL

IH

IL

IH

IL

IL

C

IL

OL

OL

OH

OZ

C

OZ

DD RANGEVSS

DD/SS RANGE

DD

SS

P

DISS

5, 7, 8

BW_100 kΩ R
BW_1 MΩ R

S

N_WB

otherwise noted.)

= 25°C, RAB = 10 kΩ –30 +30 %

A

= 25°C, RAB = 100 kΩ/1 MΩ –30 +50 %

A

IW = VDD /R, VDD = 3 V or 5 V 60 120 Ω

/DT Code = 80

Code = FF
Code = 00

f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
VA = VB = V

VDD = 5 V 2.4 V
VDD = 5 V 0 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0 0.6 V
VIN = 0 V or 5 V 1 µA

IOL = 3 mA 0.4 V
IOL = 6 mA 0.6 V

= 1.6 mA 0.4 V

SINK

I

= 40 µA4V

SOURCE

VIN = 0 V or 5 V ±1 µA

= 0 V 2.7 5.5 V

±2.3 ±2.7 V
VIH = 5 V or VIL = 0 V 0.1 50 µA
VSS = –2.5 V, VDD = +2.5 V +0.1 –50 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 0.5 250 µW

= 100 kΩ, Code = 80

AB

= 1 MΩ, Code = 80

AB

W

VA = 1 V rms + 2 V dc, 0.005 %

= 2 V dc, f = 1 kHz

V

B

VA = VDD, VB = 0 V, ±1 LSB Error Band, 2 µs

= 10 kΩ

R

AB

RWB = 5 kΩ, f = 1 kHz 14 nV√Hz

H

H

H

H

H

W

5 ppm/°C

–1 –0.5 0 LSB
0 0.5 1 LSB

V

SS

V

DD

V
45 pF
60 pF
1nA

0.7 V

DD

VDD + 0.5 V

–0.5 +0.3 VDDV

DD

DD

V

V

3pF

38 pF

H

H

H

650 kHz
69 kHz
6 kHz

–2–

REV. B

AD5241/AD5242

www.BDTIC.com/ADI

Parameter Symbol Conditions Min Typ1Max Unit

5, 9

INTERFACE TIMING CHARACTERISTICS (Applies to all parts.

SCL Clock Frequency f
t

Bus Free Time between t

BUF

SCL

1

STOP and START

Hold Time (Repeated START) t

t

HD; STA

2

After this period, the first clock 600 ns
pulse is generated.

Low Period of SCL Clock t

t

LOW

High Period of SCL Clock t

t

HIGH

t

Setup Time for Repeated

SU; STA

START Condition t
t
t
t

Data Hold Time t

HD; DAT

Data Setup Time t

SU; DAT

Rise Time of Both t

R

3

4

5

6

7

8

SDA and SCL Signals

Fall Time of Both SDA and SCL Signals t

t

F

t

Setup Time for STOP Condition t

SU; STO

NOTES

1

Typicals represent average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi­tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10.

4

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

7

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band­width. The highest R value results in the minimum overall power consumption.

8

All dynamic characteristics use VDD = 5 V.

9

See timing diagram for location of measured values.

Specifications subject to change without notice.

9

10

)

0 400 kHz

1.3 µs

1.3 µs

0.6 50 µs

600 ns

900 ns

100 ns

300 ns

300 ns

= VDD and VB = 0 V.

A

REV. B

–3–

AD5241/AD5242

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V , –7 V

V

SS

V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

V

A

AX–BX, AX–WX, BX–WX at 10 kΩ in TSSOP-14 . . . ±5.0 mA
AX–BX, AX–WX, BX–WX at 100 kΩ in TSSOP-14 . . ± 1.5 mA
AX–BX, AX–WX, BX–WX at 1 MΩ in TSSOP-14 . . . ±0.5 mA

Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . –40°C to +105°C

*

Thermal Resistance θ

JA

SOIC (SOIC-14) . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

SOIC (SOIC-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W

Maximum Junction Temperature (T

DD

Package Power Dissipation P

*

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

*

Lead Temperatures

*

R-14, R-16A, RU-14, RU-16 (Vapor Phase, 60 sec) . 215°C

D

max) . . . . . . . . . . 150°C

J

= (TJmax – TA)/θ

JA

R-14, R-16A, RU-14, RU-16 (Infrared, 15 sec) . . . . . 220°C

*Max current increases at lower resistance and different packages.

ORDERING GUIDE

Number of

Number of End to End Temperature Package Package Devices per

Model Channels RAB () Range (C) Description Option Container

AD5241BR10 1 10 k –40 to +105 SOIC-14 R-14 56
AD5241BR10-REEL7 1 10 k –40 to +105 SOIC-14 R-14 1000
AD5241BRU10-REEL7 1 10 k –40 to +105 TSSOP-14 RU-14 1000
AD5241BR100 1 100 k –40 to +105 SOIC-14 R-14 56
AD5241BR100-REEL7 1 100 k –40 to +105 SOIC-14 R-14 1000
AD5241BRU100-REEL7 1 100 k –40 to +105 TSSOP-14 RU-14 1000
AD5241BR1M 1 1 M –40 to +105 SOIC-14 R-14 56
AD5241BRU1M-REEL7 1 1 M –40 to +105 TSSOP-14 RU-14 1000
AD5242BR10 2 10 k –40 to +105 SOIC-16 R-16A 48
AD5242BR10-REEL7 2 10 k –40 to +105 SOIC-16 R-16A 1000
AD5242BRU10-REEL7 2 10 k –40 to +105 TSSOP-16 RU-16 1000
AD5242BR100 2 100 k –40 to +105 SOIC-16 R-16A 48
AD5242BR100-REEL7 2 100 k –40 to +105 SOIC-16 R-16A 1000
AD5242BRU100-REEL7 2 100 k –40 to +105 TSSOP-16 RU-16 1000
AD5242BR1M 2 1 M –40 to +105 SOIC-16 R-16A 48
AD5242BRU1M-REEL7 2 1 M –40 to +105 TSSOP-16 RU-16 1000

NOTES

1

The AD5241/AD5242 die size is 69 mil × 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5495245 applies.

2

TSSOP packaged units are only available in 1,000-piece quantity Tape and Reel.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5241/AD5242 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. B

AD5241/AD5242

TOP VIEW

(Not to Scale)

1

O

1

A

1

W

1

B

1

V

DD

SHDN

SCL

SDA

A

2

W

2

B

2

O

2

V

SS

DGND

AD1

AD0

AD5242

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

www.BDTIC.com/ADI

AD5241 PIN CONFIGURATION

1

A

1

2

W

1

3

B

1

4

V

DD

5

SHDN

6

SCL

7

SDA

NC = NO CONNECT

AD5241

TOP VIEW

(Not to Scale)

14

13

12

11

10

9

8

O

1

NC

O

2

V

SS

DGND

AD1

AD0

AD5241 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1A
2W
3B
4V

1

1

1

DD

Resistor Terminal A
Wiper Terminal W
Resistor Terminal B

1

1

1

Positive power supply, specified for opera­tion from 2.2 V to 5.5 V.

5 SHDN Active low, asynchronous connection of

Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to VDD if

not used.
6 SCL Serial Clock Input
7 SDA Serial Data Input/Output
8AD0 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
9AD1 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
10 DGND Common Ground
11 V

SS

Negative power supply, specified for

operation from 0 V to –2.7 V.
12 O

2

Logic Output Terminal O

2

13 NC No Connect
14 O

1

Logic Output Terminal O

1

AD5242 PIN CONFIGURATION

AD5242 PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1O
2A
3W
4B
5V

1

1

1

1

DD

Logic Output Terminal O
Resistor Terminal A
Wiper Terminal W
Resistor Terminal B

1

1

1

1

Positive power supply, specified for opera­tion from 2.2 V to 5.5 V.

6 SHDN Active low, asynchronous connection of

Wiper W to Terminal B, and open circuit
of Terminal A. RDAC register contents
unchanged. SHDN should tie to VDD if

not used.
7 SCL Serial Clock Input
8 SDA Serial Data Input/Output
9 AD0 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
10 AD1 Programmable address bit for multiple

package decoding. Bits AD0 and AD1

provide four possible addresses.
11 DGND Common Ground
12 V

SS

Negative power supply, specified for

operation from 0 V to –2.7 V.
13 O
14 B
15 W
16 A

2

2

2

2

Logic Output Terminal O

Resistor Terminal B

Wiper Terminal W

Resistor Terminal A

2

2

2

2

REV. B

–5–

AD5241/AD5242

www.BDTIC.com/ADI

t

8

SDA

t

1

t

8

t

9

t

2

SCL

t

2

SP

t

3

t

t

4

6

t

7

t

5

S P

t

10

Figure 1. Detail Timing Diagram

Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format:

S01011AD1 AD0 R/W A A/B RS SD O1O2XXXAD7D6D5D4D3D2 D1D0 A P

SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE

where:

S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pins AD1 and AD0.
R/W = Read Enable at High and output to SDA. Write Enable at Low.
A/B = RDAC subaddress select. ‘0’ for RDAC1 and ‘1’ for RDAC2.
RS = Midscale reset, active high.
SD = Shutdown in active high. Same as SHDN except inverse logic.

, O2 = Output logic pin latched values.

O

1

D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.

SCL

SDA

START BY

MASTER

1

0

0

1

SLAVE ADDRESS BYTE

1AD1AD0R/W

1

FRAME 1

91 199

RS SD O1 O2 X X X D7 D6 D5 D4D3D2 D1D0

A/B

ACK BY
AD5241

FRAME 2

INSTRUCTION BYTE

ACK BY
AD5241

Figure 2. Writing to the RDAC Serial Register

SCL

SDA

START BY

MASTER

1

0

0

1

SLAVE ADDRESS BYTE

1

FRAME 1

1AD1AD0

91 9

R/W

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5241

DATA BYTE FROM PREVIOUSLY SELECTED

RDAC REGISTER IN WRITE MODE

FRAME 2

Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode

FRAME 3

DATA BYTE

NO ACK BY

MASTER

STOP BY
MASTER

ACK BY
AD5241

STOP BY
MASTER

–6–

REV. B

Typical Performance Characteristics–AD5241/AD5242

CODE – Decimal

0.50

0.25

0

–0.25

–0.50

POTENTIOMETER MODE

INTEGRAL NONLINEARITY – LSB

256

224

160

128

6432

0

19296

VDD = +2.7V
V

DD

= +5.5V

V

DD

= 2.7V

VDD/VSS = 2.7V

VDD/VSS = +2.7V/0V, +5.5V/0V

www.BDTIC.com/ADI

1.0

0.5

VDD/VSS = +2.7V/0V

0

NONLINEARITY – LSB

–0.5

RHEOSTAT MODE DIFFERENTIAL

–1.0

VDD/VSS = +5.5V/0V, 2.7V

CODE – Decimal

TPC 1. RDNL vs. Code

1.0

VDD/VSS = +2.7V/0V

0.5

0

VDD = +2.7V
V

= +5.5V

DD

= 2.7V

V

DD

2241921601289664320

V

= +2.7V

DD

V

= +5.5V

DD

V

= 2.7V

DD

256

10000

1000

100

TPC 4. INL vs. Code

1M

100k

VDD = 2.7V

= 25C

T

A

NONLINEARITY – LSB

–0.5

RHEOSTAT MODE INTEGRAL

–1.0

0.25

0.13

0

POTENTIOMETER MODE

–0.13

DIFFERENTIAL NONLINEARITY – LSB

–0.25

VDD/VSS = +5.5V/0V, 2.7V

CODE – Decimal

TPC 2. RINL vs. Code

VDD/VSS = +2.7V/0V, +5.5V/0V, 2.7V

CODE – Decimal

TPC 3. DNL vs. Code

2241921601289664320

VDD = +2.7V
V

= +5.5V

DD

V

= 2.7V

DD

2241921601289664320

256

256

10

NOMINAL RESISTANCE – k

1

–20

–40

0

TEMPERATURE –

10k

40

20



C

80

60

TPC 5. Nominal Resistance vs. Temperature

10000

1000

100

- SUPPLY CURRENT – A

10

DD

I

VDD = 2.5V

1

0

INPUT LOGIC VOLTAGE – V

VDD = 5V

VDD = 3V

TPC 6. Supply Current vs. Input Logic Voltage

54321

REV. B

–7–

AD5241/AD5242

www.BDTIC.com/ADI

SHUTDOWN CURRENT – A

0.1

0.01

0.001
–40

–20

0

20

TEMPERATURE –

RAB = 10k
V

= 5.5V

DD

60

40



C

80

TPC 7. Shutdown Current vs. Temperature

70

C



60

10M VERSION

50

40

30

20

10

0

–10

–20

POTENTIOMETER MODE TEMPCO – ppm/

–30

10k VERSION

100k VERSION

320

64

96

128

CODE – Decimal

VDD/VSS = 2.7V/0V

= 25C

T

A

160 192 224 256

TPC 8.⌬VWB/⌬T Potentiometer Mode Tempco

100

TA = 25C

90

80

70

60

50

40

WIPER RESISTANCE – 

30

20

10

COMMON MODE – V

VDD/VSS = +2.7V/0V

VDD/VSS = 2.7V/0V

VDD/VSS = +5.5V/0V

543210–1–2–3

TPC 10. Incremental Wiper Contact vs. VDD/V

300

A – VDD/VSS = 5.5V/0V
CODE = FF

250

B – V

A



CODE = FF

200

C – V
CODE = FF

150

D – V
CODE = 55

E – V

100

– SUPPLY CURRENT

CODE = 55

DD

I

F – V

50

CODE = 55

0

10

DD/VSS

DD/VSS

DD/VSS

DD/VSS

DD/VSS

= 3.3V/0V

= 2.5V/0V

= 5.5V/0V

= 3.3V/0V

= 2.5V/0V

FREQUENCY – kHz

TPC 11. Supply Current vs. Frequency

SS

6

D

A

E
B

F
C

1000100

120

100

C



80

60

40

20

0

–20

–40

RHEOSTAT MODE TEMPCO – ppm/

–60

–80

100k VERSION

10k VERSION

10M VERSION

9664320

CODE – Decimal

VDD/VSS = 2.7V/0V

= 25C

T

A

160128

192

TPC 9.⌬RWB/⌬T Rheostat Mode Tempco

224

256

6

0

–6

–12

–18

–24

GAIN – dB

–30

–36

–42

–48

–54

100

FREQUENCY – Hz

TPC 12. AD5242 10 kΩ Gain vs. Frequency vs. Code

–8–

FF

H

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

100k10k1k

1M

REV. B

AD5241/AD5242

www.BDTIC.com/ADI

6

0

–6

–12

–18

–24

GAIN – dB

–30

–36

–42

–48

–54

100

FF

H

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY – Hz

100k10k1k

TPC 13. AD5242 100 kΩ Gain vs. Frequency vs. Code

OPERATION

The AD5241/AD5242 provide a single-/dual-channel, 256­position digitally controlled variable resistor (VR) device. The
terms VR, RDAC, and programmable resistor are commonly
used interchangeably to refer to digital potentiometer.

To program the VR settings, refer to the Digital Interface sec­tion. Both parts have an internal power ON preset that places
the wiper in midscale during power-on, which simplifies the
fault condition recovery at power-up. In addition, the shutdown
SHDN Pin of AD5241/AD5242 places the RDAC in an almost
zero power consumption state where Terminal A is open circuited
and Wiper W is connected to Terminal B, resulting in only
leakage current being consumed in the VR structure. During
shutdown, the VR latch contents are maintained when the RDAC
is inactive. When the part is returned from shutdown, the stored
VR setting will be applied to the RDAC.

A

SHDN

SW

SHDN

D7
D6
D5
D4
D3
D2
D1
D0

RDAC

LATCH

AND

DECODER

R

R

R

R

B

N

SW

2–1

N

SW

2–2

W

SW

1

R

/2

SW

DIGITAL CIRCUITRY
OMITTED FOR CLARITY

RAB

0

N

Figure 4. Equivalent RDAC Circuit

6

0

–6

–12

–18

–24

GAIN – dB

–30

–36

–42

–48

–54

100

FF

H

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY – Hz

100k10k1k

TPC 14. AD5242 1 MΩ Gain vs. Frequency vs. Code

PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and
B is available in 10 kΩ, 100 kΩ, and 1 MΩ. The final two or
three digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100; 1 MΩ = 1 M. The
nominal resistance (R

) of the VR has 256 contact points

AB

accessed by the Wiper Terminal, plus the B Terminal con­tact. The 8-bit data in the RDAC latch is decoded to select
one of the 256 possible settings. Assume a 10 kΩ part is used;
the wiper’s first connection starts at the B Terminal for data

. Since there is a 60 Ω wiper contact resistance, such con-

00

H

nection yields a minimum of 60 Ω resistance between Terminals
W and B. The second connection is the first tap point that cor­responds to 99 Ω (R

. The third connection is the next tap point representing

01

H

138 Ω (39 × 2 + 60) for data 02

= RAB/256 + RW = 39 + 60) for data

WB

and so on. Each LSB data

H,

value increase moves the wiper up the resistor ladder until the
last tap point is reached at 10021 Ω [R

– 1 LSB + RW].

AB

Figure 4 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string will not be accessed; there­fore, there is 1 LSB less of the nominal resistance at full scale in
addition to the wiper resistance.

The general equation determining the digitally programmed
resistance between W and B is:

RD

WB AB W

D

256

RR

=×+

()

(1)

where:

D is the decimal equivalent of the binary code between 0

and 255, which is loaded in the 8-bit RDAC register.

R

is the nominal end-to-end resistance.

AB

is the wiper resistance contributed by the on resistance

R

W

of the internal switch.

Again, if R
circuit or tied to W, the following output resistance at R

= 10 kΩ and the A Terminal can be either open

AB

WB

will

be set for the following RDAC latch codes.

REV. B

–9–

AD5241/AD5242

www.BDTIC.com/ADI

DR

WB

(DEC) ()Output State

255 10021 Full-Scale (R

– 1 LSB + RW)

WB

128 5060 Midscale
199 1 LSB
060Zero-Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum current of no more
than ±20 mA. Otherwise, degradation or possible destruction of
the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digi­tally controlled resistance, R

. When these terminals are used,

WA

the B Terminal can be opened or tied to the Wiper Terminal.
Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is:

D

256

RD

()

WA AB W

For R

= 10 kΩ, and the B Terminal can be either open circuit

AB

or tied to W. The following output resistance R

–

=×+

256

RR

will be set for

WA

(2)

the following RDAC latch codes.

DR

WA

(DEC) () Output State

255 99 Full-Scale
128 5060 Midscale
1 10021 1 LSB
0 10060 Zero-Scale

The typical distribution of the nominal resistance R

AB

from

channel to channel matches within ±1% for AD5242. Device­to-device matching is process lot dependent and it is possible to
have ±30% variation. Since the resistance element is processed
in thin film technology, the change in R

with temperature has

AB

no more than a 30 ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates output voltages at
wiper-to-B and wiper-to-A to be proportional to the input volt­age at A-to-B. Unlike the polarity of V

– VSS, which must be

DD

positive, voltage across A–B, W–A, and W–B can be at either
polarity provided that V

is powered by a negative supply.

SS

If ignoring the effect of the wiper resistance for approximation,
connecting the A Terminal to 5 V and the B Terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal AB divided by the 256 positions of the
potentiometer divider. Since AD5241/AD5242 can be sup­plied by dual supplies, the general equation defining the output
voltage at V

with respect to ground for any valid input voltage

W

applied to Terminals A and B is:

D

−

VDDV

=+

()

WA B

256

256

256

V

(3)

which can be simplified to

VDDVV

=+

()

WABB

256

(4)

where D is the decimal equivalent of the binary code between 0
to 255 that is loaded in the 8-bit RDAC register.

For more accurate calculation including the effects of wiper
resistance, V

VD

W

where R

can be found as:

W

RD

()

WB

=

()

WB

R

AB

(D) and RWA(D) can be obtained from Equations 1

V

A

RD

WA

+

R

AB

()

V

B

(5)

and 2.

Operation of the digital potentiometer in the Divider Mode results
in a more accurate operation over temperature. Unlike the
Rheostat Mode, the output voltage is dependent on the ratio
of the internal resistors R

and RWB, and not the absolute

WA

values; therefore, the temperature drift reduces to 5 ppm/°C.

DIGITAL INTERFACE
2-Wire Serial Bus

The AD5241/AD5242 are controlled via an I2C compatible
serial bus. The RDACs are connected to this bus as slave devices.

Referring to Figures 2 and 3, the first byte of AD5241/AD5242
is a Slave Address Byte. It has a 7-bit slave address and an R/W
Bit. The 5 MSBs are 01011 and the following two bits are
determined by the state of the AD0 and AD1 Pins of the device.
AD0 and AD1 allow users to use up to four of these devices on
one bus.

2

The 2-wire I

C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (Figure 2). The following byte
is the Slave Address Byte, Frame 1, which consists of the
7-bit slave address followed by an R/W Bit (this bit deter-
mines whether data will be read from or written to the
slave device).

The slave whose address corresponds to the transmitted
address will respond by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge Bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W Bit is high, the master will read
from the slave device. If the R/W Bit is low, the master will
write to the slave device.

2. A Write operation contains an extra Instruction Byte more
than the Read operation. This Instruction Byte, Frame 2,
in Write Mode follows the Slave Address Byte. The MSB of
the Instruction Byte labeled A/B is the RDAC subaddress
select. A “low” selects RDAC1 and a “high” selects RDAC2
for the dual-channel AD5242. Set A/B to low for AD5241.
The second MSB, RS, is the midscale reset. A logic high of
this bit moves the wiper of a selected RDAC to the center tap
where R

= RWB. The third MSB, SD, is a shutdown bit. A

WA

logic high on SD causes the RDAC open circuit at Terminal A
while shorting the wiper to Terminal B. This operation yields
almost a 0 Ω in Rheostat Mode or 0 V in Potentiometer
Mode. This SD Bit serves the same function as the SHDN

–10–

REV. B

AD5241/AD5242

RPR

P

SD

G

M1

SD

G

M2

3.3V

E

2

PROM

RPR

P

5V

AD5242

SCL2

SDA2

V

DD2

= 5V

SCL1

SDA1

V

DD2

= 3.3V

www.BDTIC.com/ADI

Pin except that SHDN Pin reacts to active low. The follow­ing two bits are O

and O1. They are extra programmable

2

logic outputs that users can use to drive other digital loads,
logic gates, LED drivers, analog switches, and the like. The
three LSBs are Don’t Care. See Figure 2.

3. After acknowledging the Instruction Byte, the last byte in

each device to be written to or read from independently. The
master device output bus line drivers are open-drain pull­downs in a fully I

2

C compatible interface. Note, a device will be
addressed properly only if the bit information of AD0 and
AD1 in the Slave Address Byte matches with the logic inputs at
pins AD0 and AD1 of that particular device.

Write Mode is the Data Byte, Frame 3. Data is transmitted
over the serial bus in sequences of nine clock pulses (eight
data bits followed by an Acknowledge Bit). The transitions
on the SDA line must occur during the low period of SCL
and remain stable during the high period of SCL (Figure 2).

4. Unlike the Write Mode, the Data Byte follows immediately
after the acknowledgment of the Slave Address Byte in Read
Mode, Frame 2. Data is transmitted over the serial bus
in sequences of nine clock pulses (slightly different than the
Write Mode, there are eight data bits followed by a No
Acknowledge logic 1 Bit in Read Mode). Similarly, the transi-

MASTER

Figure 5. Multiple AD5242 Devices on One Bus

SDA SCL

AD1

AD0

AD5242

RPR

V

DD

P

SDA SCL

AD1

AD0

AD5242

tions on the SDA line must occur during the low period of
SCL and remain stable during the high period of SCL. See
Figure 3.

5. When all Data Bits have been read or written, a STOP condi­tion is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In Write Mode, the master will pull the SDA line
high during the tenth clock pulse to establish a STOP con­dition (see Figure 2). In Read Mode, the master will issue a
No Acknowledge for the ninth clock pulse (i.e., the SDA
line remains high). The master will then bring the SDA
line low before the tenth clock pulse, which goes high to

LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE

While most old systems may be operated at one voltage, a new
component may be optimized at another. When they operate the
same signal at two different voltages, a proper method of level­shifting is needed. For instance, one can use a 3.3 V E
to interface with a 5 V digital potentiometer. A level-shift scheme
is needed in order to enable a bidirectional communication so
that the setting of the digital potentiometer can be stored to and
retrieved from the E

2

PROM. Figure 6 shows one of the tech­niques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold
FDV301N if V

falls below 2.5 V.

DD

establish a STOP condition (see Figure 3).

A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instruct­ing the part only once. During the Write cycle, each Data Byte
will update the RDAC output. For example, after the RDAC
has acknowledged its Slave Address and Instruction Bytes, the
RDAC output will be updated. If another byte is written to the
RDAC while it is still addressed to a specific slave device with
the same instruction, this byte will update the output of the
selected slave device. If different instructions are needed, the
Write Mode has to start a whole new sequence with a new Slave

Figure 6. Level-Shift for Different Voltage Devices Operation

Address, Instruction, and Data Bytes transferred again. Simi­larly, a repeated Read function of the RDAC is also allowed.

READBACK RDAC VALUE

Specific to the AD5242 dual-channel device, the channel of inter-

IN

est is the one that was previously selected in the Write Mode.
In addition, to read both RDAC values consecutively, users
have to perform two write-read cycles. For example, users may
first specify the RDAC1 subaddress in the Write Mode (it is not
necessary to issue the Data Byte and the STOP condition), then
change to the Read Mode and read the RDAC1 value. To con­tinue reading the RDAC2 value, users have to switch back to
the Write Mode and specify the subaddress, then switch once
again to the Read Mode and read the RDAC2 value. It is not
necessary to issue the Write Mode Data Byte or the first stop
condition for this operation. Users should refer to Figures 2 and
3 for the programming format.

MULTIPLE DEVICES ON ONE BUS

Figure 5 shows four AD5242 devices on the same serial bus.
Each has a different slave address since the state of their AD0
and AD1 Pins are different. This allows each RDAC within

REV. B

ADDITIONAL PROGRAMMABLE LOGIC OUTPUT

AD5241/AD5242 feature additional programmable logic out­puts, O
switches, and logic gates. They can also be used as self-con­tained shutdown as preset to logic 0 feature which will be
explained later. O
The logic states of O
under the Write Mode (see Figure 2). Figure 7 shows the out­put stage of O
in push-pull configuration. As shown, the output will be equal to
V
capability to drive milliamperes of load.

–11–

Figure 7. Output Stage of Logic Output O

and O2, that can be used to drive digital load, analog

1

or VSS, and these logic outputs have adequate current driving

DD

O1 DATA IN FRAME 2
OF WRITE MODE

and O2 default to logic 0 during power-up.

1

and O2 can be programmed in Frame 2

1

which employs large P and N channel MOSFETs

1

5V

1 2

SDA

SCL

V

DD

SDA SCL

AD1

AD0

AD5242

M

P

M

N

V

DD

SDA SCL

AD1

AD0

AD5242

2

PROM

V

DD

O1



V

SS

1

AD5241/AD5242

www.BDTIC.com/ADI

Users can also activate O1 and O2 in three different ways with­out affecting the wiper settings.

1. Start, Slave Address Byte, Acknowledge, Instruction Byte
and O2 specified, Acknowledge, Stop.

with O

1

2. Complete the write cycle with Stop, then Start, Slave Address

Byte, Acknowledge, Instruction Byte with O

and O2 speci-

1

fied, Acknowledge, Stop.

3. Do not complete the write cycle by not issuing the Stop, then

Start, Slave Address Byte, Acknowledge, Instruction Byte

and O2 specified, Acknowledge, Stop.

with O

1

All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 9. This applies
to digital input Pins SDA, SCL, and SHDN.

SELF-CONTAINED SHUTDOWN FUNCTION

Shutdown can be activated by strobing the SHDN Pin or pro­gramming the SD Bit in the Write Mode Instruction Byte. In
addition, shutdown can even be implemented with the device
digital output as shown in Figure 8. In this configuration, the
device will be shut down during power-up, but users are allowed
to program the device. Thus when O

is programmed high, the

1

device will exit from the shutdown mode and respond to the
new setting. This self-contained shutdown function allows abso­lute shutdown during power-up, which is crucial in hazardous
environments without adding extra components.

O1

SHDN

R

PD

SDA

SCL

Figure 8. Shutdown by Internal Logic Output

340

Figure 9. ESD Protection of Digital Pins

A,B,W

Figure 10. ESD Protection of Resistor Terminals

LOGIC

V

SS

V

SS

–12–

REV. B

Test Circuits

W

B

V

SS

TO V

DD

DUT

I

SW

CODE =

H

R

SW

=

0.1V
I

SW

0.1V

www.BDTIC.com/ADI

Test Circuits 1 to 9 define the test conditions used in the product
specifications table.

V+ = V

DD

1LSB = V+/2

V

MS

N

V

DUT

A

B

W

OFFSET

GND

V

IN

OFFSET
BIAS

AD5241/AD5242

5V

OP279

W

A

DUT

B

V

OUT

Test Circuit 1. Potentiometer Divider Nonlinearity Error
(INL, DNL)

NO CONNECT

DUT

A

B

W

I

W

V

MS

Test Circuit 2. Resistor Position Nonlinearity Error (Rheo­stat Operation; R-INL, R-DNL)

DUT

A

V

MS2

W

B

IW = VDD/R

V

W

V

MS1

RW = [V

NOMINAL

– V

MS1

MS2

]/I

W

Test Circuit 3. Wiper Resistance

V

A

V

DD

A

V+

W

B

V+ = V

10%

DD

PSRR (dB) = 20 LOG

PSS (%/ %) =

V

MS

VMS%

V

DD

( )

%

V

V

MS

DD

Test Circuit 6. Noninverting Gain

OFFSET

GND

A

V

DUT

IN

2.5V

B

+15V

W

OP42

–15V

V

OUT

Test Circuit 7. Gain vs. Frequency

Test Circuit 8. Incremental ON Resistance

NC

V

DD

DUT

V

A

W

B

GND

SS

NC

I

CM

V

CM

Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)

OFFSET

GND

A

DUT

OFFSET
BIAS

B

5V

W

OP279

V

OUT

Test Circuit 9. Common-Mode Leakage Current

Test Circuit 5. Inverting Gain

REV. B

–13–

AD5241/AD5242

www.BDTIC.com/ADI

DIGITAL POTENTIOMETER SELECTION GUIDE

Number Resolution Power
of VRs Terminal Interface Nominal (Number Supply

Part per Voltage Data Resistance of Wiper Current
Number Package1Range Control2(k) Positions) (IDD)Packages Comments

AD5201 1 ±3 V, +5.5 V 3-Wire 10, 50 33 40 µA MSOP-10 Full AC Specs, Dual Supply,

Power-On-Reset, Low Cost

AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, MSOP-8 No Rollover, Power-On-Reset

AD7376 1 ±15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, Single 28 V or Dual ± 15 V

TSSOP-14 Supply Operation

AD5200 1 ±3 V, +5.5 V 3-Wire 10, 50 256 40 µA MSOP-10 Full AC Specs, Dual Supply,

Power-On-Reset

AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SOIC-8 Full AC Specs

AD5241 1 ±3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SOIC-14, TSSOP-14 I

AD5231 1

AD5260 1 ±5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-14 TC < 50 ppm/°C

AD5207 2 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 40 µA TSSOP-14 Full AC Specs, SVO

AD5222 2 ±3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SOIC-14, TSSOP-14 No Rollover, Stereo, Power-On-

AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOIC-14, Full AC Specs, nA

AD5232 2

AD5235 2

AD5242 2 ±3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SOIC-16, TSSOP-16 I2C Compatible, TC

AD5262 2 ±5 V, +12 V 3-Wire 20, 50, 200 256 60 µA TSSOP-16 Medium Voltage Operation,

AD5203 4 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, Full AC Specs, nA

AD5233 4

AD5204 4 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, Full AC Specs, nA

AD5206 6 ±3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, Full AC Specs, Dual Supply,

NOTES

1

VR stands for variable resistor. This term is used interchangeably with RDAC, programmable resistor, and digital potentiometer.

2

3-wire interface is SPI and Microwire compatible. 2-wire interface is I2C compatible.

±2.75 V, +5.5 V

±2.75 V, +5.5 V

±2.75 V, +5.5 V

±2.75 V, +5.5 V

3-Wire 10, 50, 100 1024 10 µA TSSOP-16 Nonvolatile Memory, Direct

TSSOP-14 Shutdown Current

3-Wire 10, 50, 100 256 10 µA TSSOP-16 Nonvolatile Memory, Direct

3-Wire 25, 250 1024 5 µA TSSOP-16 Nonvolatile Memory,

TSSOP-24 Shutdown Current

3-Wire 10, 50, 100 64 10 µA TSSOP-24 Nonvolatile Memory, Direct

TSSOP-24 Power-On-Reset

TSSOP-24 Shutdown Current

TSSOP-24 Power-On-Reset

2

C Compatible, TC

< 50 ppm/°C

Program, I/D, ± 6 dB Settability

Reset, TC < 50 ppm/°C

Program, I/D, ±6 dB Settability

TC < 50 ppm/°C

< 50 ppm/°C

TC < 50 ppm/°C

Program, I/D, ±6 dB Settability

–14–

REV. B

OUTLINE DIMENSIONS

16

9

81

PIN 1

SEATING

PLANE

8
0

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20
MAX

0.20

0.09

0.75

0.60

0.45

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

www.BDTIC.com/ADI

AD5241/AD5242

14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

COPLANARITY

14

0.65

BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

8

71

SEATING
PLANE

6.40

BSC

1.20
MAX

0.20

0.09

8
0

14-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-14)

Dimensions shown in millimeters and (inches)

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.75

0.60

0.45

16-Lead Standard Small Outline Package [SOIC]

Narrow Body

(R-16A)

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

8

6.20 (0.2441)

5.80 (0.2283)

7

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.19 (0.0075)

PIN 1

14

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.33 (0.0130)

4.00 (0.1575)

3.80 (0.1496)

COPLANARITY

0.25 (0.0098)

0.10 (0.0039)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012 AB

REV. B

0.50 (0.0197)

0.25 (0.0098)

8
0

1.27 (0.0500)

0.40 (0.0157)

 45

–15–

4.00 (0.1575)

3.80 (0.1496)

COPLANARITY

0.25 (0.0098)

0.10 (0.0039)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012 AC

PIN 1

10.00 (0.3937)

9.80 (0.3858)

16

1

1.27 (0.0500)
BSC

0.51 (0.0201)

0.33 (0.0130)

9

6.20 (0.2441)

5.80 (0.2283)

8

1.75 (0.0689)

1.35 (0.0531)

SEATING
PLANE

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0197)

0.25 (0.0098)

8
0

1.27 (0.0500)

0.40 (0.0157)

 45

AD5241/AD5242

www.BDTIC.com/ADI

Revision History

Location Page

8/02—Data Sheet changed from REV. A to REV. B.

Additions to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to TPC 8 and TPC 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Changes to READBACK RDAC VALUE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Changes to ADDITIONAL PROGRAMMABLE LOGIC OUTPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Added SELF-CONTAINED SHUTDOWN section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Added new Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Changes to DIGITAL POTENTIOMETER SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2/02—Data Sheet changed from REV. 0 to REV. A.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to FUNCTIONAL BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to Figures 1, 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Addition of Readback RDAC Value and Additional Programmable Logic Output sections, and addition of new Figure 7

(which changed succeeding figure numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Additions/edits to DIGITAL POTENTIOMETER SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C00926–0–8/02(B)

–16–

PRINTED IN U.S.A.

REV. B