64-position digital potentiometer
10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Simple up/down digital or manual configurable control
Midscale preset
Low potentiometer mode tempco = 10 ppm/°C
Low rheostat mode tempco = 35 ppm/°C
Ultralow power, I
Fast adjustment time, ts = 1 µs
Chip select enable multiple device operation
Low operating voltage, 2.7 V to 5.5 V
Automotive temperature range, −40°C to +105°C
Compact thin SOT-23-8 (2.9 mm × 3 mm) Pb-free package
APPLICATIONS
Mechanical potentiometer and trimmer replacements
LCD backlight, contrast, and brightness controls
Portable electronics level adjustment
Programmable power supply
Digital trimmer replacements
Automatic closed-loop control
GENERAL DESCRIPTION
The AD5227 is Analog Devices’ latest 64-step up/down control
digital potentiometer
adjustment function as a 5 V potentiometer or variable resistor.
Its simple 3-wire up/down interface allows manual switching or
high speed digital control. The AD5227 presets to midscale at
power-up. When
every clock pulse. The direction is determined by the state of
the U/
any host controller, discrete logic, or manually with a rotary
encoder or pushbuttons. The AD5227’s 64-step resolution, small
footprint, and simple interface enable it to replace mechanical
potentiometers and trimmers with typically 6× improved
resolution, solid-state reliability, and design layout flexibility,
resulting in a considerable cost savings in end users’ systems.
pin (see Table 1). The interface is simple to activate by
D
= 0.4 µA typ and 3 µA max
DD
1
. This device performs the same electronic
is enabled, the devices changes step at
CS
Control Digital Potentiometer
AD5227
FUNCTIONAL BLOCK DIAGRAM
V
DD
AD5227
CS
U/D
CLK
GND
6-BIT UP/DOWN
CONTROL
LOGIC
POR
MIDSCALE
Figure 1.
WIPER
REGISTER
The AD5227 is available in a compact thin SOT-23-8 (TSOT-8)
Pb-free package. The part is guaranteed to operate over the
automotive temperature range of −40°C to +105°C.
Users who consider EEMEM potentiometers should refer to
some recommendations in the Applications section.
Table 1. Truth Table
U/
CS
0
0
CLK
↓
↓
D
Operation
0 RWB Decrement
1 RWB Increment
1 X X No Operation
1
RWA increments if RWB decrements and vice versa.
A
W
B
04419-0-001
1
1
The term s digital potentiometer and RDAC are used interchangeably.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
10 kΩ, 50 kΩ, 100 kΩ versions: VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, A = no connect −0.5 ±0.15 +0.5 LSB
Resistor Integral Nonlinearity2 R-INL RWB, A = no connect −1 ±0.3 +1 LSB
Nominal Resistor Tolerance3 ∆RAB/RAB −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C
Wiper Resistance RW V
V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE
Resolution N 6 Bits
Integral Nonlinearity3 INL −1 ±0.1 +1 LSB
Differential Nonlinearity
3, 4
DNL −0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Midscale 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V
≥+31 steps from midscale −1 −0.5 0 LSB
WFSE
≤−32 steps from midscale 0 0.5 +1 LSB
WZSE
RESISTOR TERMINALS
Voltage Range5 V
Capacitance A, B6 C
With respect to GND 0 VDD V
A, B, W
A, B
Capacitance W6 CW
Common-Mode Leakage ICM V
DIGITAL INPUTS (CS, CLK, U/D)
Input Logic High VIH 2.4 5.5 V
Input Logic Low VIL 0 0.8 V
Input Current II V
Input Capacitance6 C
5 pF
I
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
Supply Current IDD
Power Dissipation7 P
DISS
Power Supply Sensitivity PSSR VDD = 5 V ± 10% 0.01 0.05 %/%
DYNAMIC CHARACTERISTICS6, 8, 9
Bandwidth –3 dB BW_10 k RAB = 10 kΩ, midscale 460 kHz
BW_50 k RAB = 50 kΩ, midscale 100 kHz
BW_100 k RAB = 100 kΩ, midscale 50 kHz
Total Harmonic Distortion THD
Adjustment Settling Time tS
Resistor Noise Voltage e
Footnotes on the next page.
R
N_WB
= 2.7 V 100 200 Ω
DD
= 5.5 V 50 Ω
DD
f = 1 MHz, measured to
140 pF
GND
f = 1 MHz, measured to
150 pF
GND
= VB = VW 1 nA
A
= 0 V or 5 V ±1 µA
IN
= 5 V or VIL = 0 V,
V
IH
V
= 5 V
DD
= 5 V or VIL = 0 V,
V
IH
= 5 V
V
DD
= 1 V rms, RAB = 10 kΩ,
V
A
= 0 V dc, f = 1 kHz
V
B
= 5 V ± 1 LSB error
V
A
band, V
V
= 0, measured at
B
W
= 5 kΩ, f = 1 kHz 14 nV/√Hz
WB
0.4 3 µA
17 µW
0.05 %
1 µs
Rev. 0 | Page 3 of 16
AD5227
Parameter Symbol Conditions Min Typ1 Max Unit
INTERFACE TIMING CHARACTERISTICS (applies to all parts
Clock Frequency f
CLK
Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns
CS to CLK Setup Time
CS Rise to CLK Hold Time
U/D to Clock Fall Setup Time
t
CSS
t
CSH
t
UDS
1
Typicals represent average readings at 25°C, VDD = 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
8
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use VDD = V.
10
All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
CS = LOW
U/D = HIGH
6, 10
)
50 MHz
10 ns
10 ns
10 ns
CLK
R
WB
Figure 2. Increment R
CS = LOW
U/D = 0
CLK
R
WB
Figure 3. Decrement R
1
CS
0
t
CLK
U/D
R
WB
CSS
1
0
1
0
t
t
UDS
t
CL
CH
t
S
Figure 4. Detailed Timing Diagram(Only R
04419-0-004
WB
04419-0-005
WB
t
CSH
04419-0-006
Decrement Shown)
WB
Rev. 0 | Page 4 of 16
AD5227
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V, +7 V
VA, VB, VW to GND 0 V, VDD
0 V, V
Digital Input Voltage to GND (CS, CLK, U/D)
DD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (R
≤ 5 kΩ, A open)1 ±1 mA
WB
IWA Continuous (RWA ≤ 5 kΩ, B open)1 ±1 mA
IAB Continuous
= 10 kΩ/50 kΩ/100 kΩ)1
(R
AB
±500 µA/
±100 µA/±50 µA
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 s – 30 s) 245°C
Thermal Resistance2 θJA 230°C/W
1
Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2
Package power dissipation = (TJmax – TA) / θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
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