Analog Devices AD5222 Datasheet

Increment /Decrement

DECODE

UP/DOWN
COUNTER

AD5222

V

SS

A1

W1
B1

DECODE

UP/DOWN
COUNTER

A2

W2
B2

POR

DAC

SELECT

AND

ENABLE

CLK

CS

U/D

DACSEL

MODE

GND

V

DD

V

SS

A1

W1
B1

A2

W2
B2

CLK

CS

U/D

DACSEL

MODE

GND

V

DD

U/D

INCREMENT

5V

a

FEATURES
128-Position, 2-Channel
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀, 1 M⍀
Very Low Power: 40 ␮A Max
ⴞ2.7 V Dual Supply Operation or

2.7 V to 5.5 V Single Supply Operation

Increment/Decrement Count Control

APPLICATIONS
Stereo Channel Audio Level Control
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5222 provides a dual channel, 128-position, digitally
controlled variable-resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. Choices between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.

The AD5222 contains two fixed resistors with wiper contacts that
tap the fixed resistor value at a point determined by a digitally
controlled up/down counter. The resistance between the wiper
and either end point of the fixed resistor provides a constant
resistance step size that is equal to the end-to-end resistance
divided by the number of positions (e.g., R

78 Ω). The variable resistor offers a true adjustable value of

resistance, between Terminal A and the wiper, or Terminal B

and the wiper. The fixed A-to-B terminal resistance of 10 kΩ,
50 kΩ, 100 kΩ, or 1 MΩ has a nominal temperature coefficient
of –35 ppm/°C.

The chip select CS, count CLK and U/D direction control inputs
set the variable resistor position. The MODE determines whether
both VRs are incremented together or independently. With
MODE at logic zero, both wipers are incremented UP or DOWN
without changing the relative settings between the wipers. Also,
the relative ratio between the wipers is preserved if either wiper
reaches the end of the resistor array. In the independent MODE
(Logic 1) only the VR determined by the DACSEL pin is changed.
DACSEL (Logic 0) changes RDAC 1. These inputs, which con­trol the internal up/down counter, can be easily generated with

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

STEP

= 10 kΩ/128 =

Dual Digital Potentiometer

AD5222

FUNCTIONAL BLOCK DIAGRAM

mechanical or push-button switches (or other contact closure
devices). This simple digital interface eliminates the need for
microcontrollers in front panel interface designs.

The AD5222 is available in the surface-mount (SO-14) package.
For ultracompact solutions, selected models are available in the
thin TSSOP-14 package. All parts are guaranteed to operate

over the extended industrial temperature range of –40°C to
+85°C. For 3-wire, SPI-compatible interface applications, see

the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/
AD8403 products.

Figure 1. Typical Push-Button Control Application

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(VDD = 3 V ⴞ 10% or 5 V ⴞ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC,

AD5222–SPECIFICATIONS

Parameter Symbol Condition Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL
Resistor Nonlinearity

Nominal Resistor Tolerance ∆RV

Resistance Temperature Coefficient R
Wiper Resistance

Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution N 7 Bits
Integral Nonlinearity

Differential Nonlinearity

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

5

6

A, B C

6

WC

Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Single-Supply Range V
Power Dual-Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation
Power Supply Sensitivity PSS 0.002 0.05 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time t

V

W

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)

Input Clock Pulsewidth tCH, t

CS to CLK Setup Time t
CS Rise to CLK Hold Time t

U/D to Clock Fall Setup Time t
U/D to Clock Fall Hold Time t
DACSEL to Clock Fall Setup Time t
DACSEL to Clock Fall Hold Time t
MODE to Clock Fall Setup Time t
MODE to Clock Fall Hold Time t

NOTES

1

Typicals represent average readings at 25°C, V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.

3

Wiper resistance is not measured on the R

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (I

DISS

8

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

9

All dynamic characteristics use VDD = 5 V.

10

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both V

Specifications subject to change without notice.

2

2

3

4

4

R-DNL RWB, V
R-INL RWB, V

R

INL R
INL R

DNL –1 ±1/4 +1 LSB

V

CM

6

7

6, 8, 9

IL

C

DD

SS

P

BW_50K R
BW_100K R
BW_1M R

S

N_WB

CSS

CSH

UDS

UDH

DSS

DSH

MDS

MDH

= 5 V.

DD

= 1 MΩ models.

AB

× V

). CMOS logic level inputs result in minimum power dissipation.

DD

DD

unless otherwise noted.)

/∆TV

AB

W

O

/∆T Code = 40

W

WFSE

WZSE

A, B, W

A, B

W

IH

IL

IL

DD RANGEVSS

DD/SS RANGE

DISS

W

CL

DD

AB

AB

IW = VDD/R, V
CH 1 to 2, VAB = VDD, T

AB

AB

Code = 7F
Code = 00

f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40
VA = VB = V

VDD = 5 V/3 V 2.4/2.1 V
VDD = 5 V/3 V 0.8/0.6 V
V

= 0 V or 5 V ±1 µA

IN

= 0 V 2.7 5.5 V

VIH = 5 V or V
VSS = –2.5 V, V
VIH = 5 V or VIL = 0 V, V

AB

AB

AB

AB

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.005 %
R

AB

R

WB

Clock Level High or Low 30 ns

= 5 V or VDD = 3 V.

= NC –1 ±1/4 +1 LSB

A

= NC –1 ±0.4 +1 LSB

A

= VDD, Wiper = No Connect, T
= V

, Wiper = No Connect –35 ppm/°C

DD

= 3 V or 5 V 45 100 Ω

DD

= 25°C0.21%

A

= 25°C –30 +30 %

A

= 10 kΩ, 50 kΩ, or 100 kΩ –1 ±1/4 +1 LSB
= 1 MΩ –2 ±1/2 +2 LSB

H

H

H

–1 –0.5 +0 LSB
0 0.5 1 LSB

V

H

H

W

20 ppm/°C

SS

V

DD

V
45 pF
60 pF
1nA

5pF

±2.3 ±2.7 V

= 0 V 15 40 µA

IL

= +2.7 V 15 40 µA

DD

= 10 kΩ, Code = 40
= 50 kΩ, Code = 40
= 100 kΩ, Code = 40
= 500 kΩ, Code = 40

= 5 V 150 400 µW

DD

H

H

H

H

1000 kHz
180 kHz
78 kHz
7kHz

= 10 kΩ, ±1 LSB Error Band 2 µs

= 5 kΩ, f = 1 kHz 14 nV√Hz

6, 10

20 ns
20 ns
10 ns
30 ns
20 ns
30 ns
20 ns
40 ns

–2–

REV. 0

AD5222

ABSOLUTE MAXIMUM RATINGS

(T

= 25°C, unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –5 V

V

SS

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V

DD

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

V

A

AX – BX, AX – WX, BX – W

. . . . . . . . . . . . . . . . . . . ±20 mA

X

Digital Input Voltage to GND . . . . . . . . . . . . 0 V, V

DD

DD

+ 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Package Power Dissipation . . . . . . . . . . . . . (T

Thermal Resistance θ

,

JA

max – T

J

)/θ

A

JA

SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

CS

t

CH

t

CL

t

UDH

t

DSH

t

MDH

t

CSH

CLK

U/D

DACSEL

MODE

t

t

t

t

CSS

UDS

DSS

MDS

Figure 2. Detail Timing Diagram

Truth Table

CS CLK U/D Operation

L t H Wiper Increment Toward Terminal A
L t L Wiper Decrement Toward Terminal B
H X X Wiper Position Fixed

Common Mode (MODE = 0) moves both wipers together either
UP or DOWN the resistor array without changing the relative
distance between the wipers. Also, the distance between both
wipers is preserved if either reaches the end of the array. Inde­pendent Mode (MODE = 1) allows user to control each RDAC
individually: DACSEL = 0 sets RDAC1; DACSEL = 1: sets
RDAC2.

ORDERING GUIDE

Kilo Package Package

Model Ohms Temperature Description Option

AD5222BR10 10 –40°C/+85°C SO-14 R-14
AD5222BRU10 10 –40°C/+85°C TSSOP-14 RU-14
AD5222BR50 50 –40°C/+85°C SO-14 R-14
AD5222BRU50 50 –40°C/+85°C TSSOP-14 RU-14
AD5222BR100 100 –40°C/+85°C SO-14 R-14
AD5222BRU100 100 –40°C/+85°C TSSOP-14 RU-14
AD5222BR1M 1,000 –40°C/+85°C SO-14 R-14
AD5222BRU1M 1,000 –40°C/+85°C TSSOP-14 RU-14

The AD5222 die size is 56 mil × 60 mil, 3360 sq. mil; 1.4224 mm × 1.524 mm,

2.1677 sq. mm. Contains 1503 transistors. Patent Number 5495245 applies.

PIN FUNCTION DESCRIPTIONS

Pin Name Description

1 B1 B Terminal RDAC #1.
2 A1 A Terminal RDAC #1.
3 W1 Wiper RDAC #1, DACSEL = 0.
4V

SS

Negative Power Supply. Specified for operation
at both 0 V or –2.7 V (Sum of |V

| + |VSS|

DD

< 5.5 V).
5 W2 Wiper RDAC #2, DACSEL = 1.
6 A2 A Terminal RDAC #2.
7 B2 B Terminal RDAC #2.
8 GND Ground.
9 MODE Common MODE = 0, Independent MODE = 1.
10 DACSEL DAC Select determines which wiper is incre-

mented in the Independent MODE = 1.

DACSEL = 0 sets RDAC1, DACSEL = 1 sets

RDAC2.
11 U/D UP/DOWN Direction Control.
12 CLK Serial Clock Input, Negative Edge Triggered.
13 CS Chip Select Input, Active Low. When CS is

high, the UP/DOWN counter is disabled.
14 V

DD

Positive Power Supply. Specified for operation

at both +3 V or +5 V. (Sum of |V

| + |VSS|

DD

< 5.5 V).

PIN CONFIGURATION

B1

1
2

A1

3

W1

AD5222

TOP VIEW

4

V

SS

(Not to Scale)

5

W2

6

A2

78

B2

14
13
12
11
10

9

V

DD

CS

CLK
U/D
DACSEL
MODE
GND

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5222 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

WARNING!

ESD SENSITIVE DEVICE