Analog Devices AD5220 Datasheet

Increment/Decrement

a

FEATURES
128 Position
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀
Very Low Power: 40 ␮A Max
Increment/Decrement Count Control

APPLICATIONS
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment

GENERAL DESCRIPTION

The AD5220 provides a single channel, 128-position digitally
controlled variable resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. A choice between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.

The AD5220 contains a fixed resistor with a wiper contact that
taps the fixed resistor value at a point determined by a digitally
controlled UP/DOWN counter. The resistance between the
wiper and either end point of the fixed resistor provides a con­stant resistance step size that is equal to the end-to-end resis­tance divided by the number of positions (e.g., R

128 = 78 Ω). The variable resistor offers a true adjustable value

of resistance, between the A terminal and the wiper, or the B
terminal and the wiper. The fixed A-to-B terminal resistance of

10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient
of 800 ppm/°C.

The chip select CS, count CLK and U/D direction control
inputs set the variable resistor position. These inputs that con­trol the internal UP/DOWN counter can be easily generated
with mechanical or push button switches (or other contact closure
devices). External debounce circuitry is required for the nega­tive-edge sensitive CLK pin. This simple digital interface elimi­nates the need for microcontrollers in front panel interface designs.

The AD5220 is available in both surface mount (SO-8) and the
8-lead plastic DIP package. For ultracompact solutions selected

models are available in the thin µSOIC package. All parts are

guaranteed to operate over the extended industrial temperature

range of –40°C to +85°C. For 3-wire, SPI compatible inter-

face applications, see the AD7376/AD8400/AD8402/AD8403
products.

STEP

= 10 kΩ/

Digital Potentiometer

AD5220

FUNCTIONAL BLOCK DIAGRAM

V

CLK

CS

U/D

UP/DOWN

INCREMENT

EN

POR

DOWN

CNTR

40

H

UP/

RS

D
E

7

C
O
D
E

AD5220

+5V

Figure 1. Typical Push-Button Control Application

UPCOUNT DETAIL

= 5.5V

V

DD

= 5.5V

V

A

V

= 0V

50mV/DIV

5V/DIV

B

f = 100kHz

Figure 2a. Stair-Step Increment Output

VDD = 5.5V

= 5.5V

V

A

= 0V

V

B

f = 60kHz

COUNT
00

H

f

= 60kHz

CLK

Figure 2b. Full-Scale Up/Down Count

A

W
B
GND

CS

U/D

CLK

AD5220

v 3FH v 00

DD

V

WB

CLK

H

V

WR

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD5220–SPECIFICATIONS

(VDD = +3 V ⴞ 10% or +5 V ⴞ 10%, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC unless

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ1Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs

Resistor Differential NL

Resistor Nonlinearity

Nominal Resistor Tolerance ∆RT
Resistance Temperature Coefficient ∆R

Wiper Resistance R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs

Resolution N 7 Bits
Integral Nonlinearity

Differential Nonlinearity Error

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range
Capacitance
Capacitance

4

5

A, B C

5

WC

Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation
Power Supply Sensitivity PSS 0.004 0.015 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time t

V

W

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS Applies to All Parts

Input Clock Pulsewidth tCH, t

CS to CLK Setup Time t
CS Rise to Clock Hold Time t

U/D to Clock Fall Setup Time t

NOTES

1

Typicals represent average readings at +25°C and V

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.

4

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

5

Guaranteed by design and not subject to production test.

6

P

is calculated from (I

DISS

7

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band­width. The highest R value results in the minimum overall power consumption.

8

All dynamic characteristics use VDD = +5 V.

9

See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.

Specifications subject to change without notice.

2

2

3

3

5

6

5, 7, 8

× V

). CMOS logic level inputs result in minimum power dissipation.

DD

DD

otherwise noted)

R-DNL RWB, VA = NC, R

R-INL RWB, VA = NC, R

/∆TV

AB

W

INL R

DNL R

/∆T Code = 40

W

WFSE

WZSE

VA, VB, V

A, CB

W

CM

IH

IL

IL

C

IL

DD

DD

P

DISS

BW_50K R
BW_100K R

W

S

NWB

CL

CSS

CSH

UDS

= +5 V.

DD

, VA = NC, R

R

WB

, VA = NC, R

R

WB

= +25°C –30 +30 %

A

= V

AB

IW = VDD/R, V

AB

R

AB

AB

R

AB

Code = 7F
Code = 00

W

, Wiper = No Connect 800 ppm/°C

DD

DD

= 10 kΩ –1 ±0.5 +1 LSB
= 50 kΩ, 100 kΩ –0.5 ±0.2 +0.5 LSB
= 10 kΩ –1 ±0.4 +1 LSB
= 50 kΩ, 100 kΩ –0.5 ±0.1 +0.5 LSB

H

H

H

f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40
VA = VB = V

W

VDD = +5 V/+3 V 2.4/2.1 V
VDD = +5 V/+3 V 0.8/0.6 V
V

= 0 V or +5 V ±1 µA

IN

VIH = +5 V or VIL = 0 V, V
VIH = +5 V or VIL = 0 V, V

= 10 kΩ, Code = 40

AB

= 50 kΩ, Code = 40

AB

= 100 kΩ, Code = 40

AB

VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz 0.002 %
VA = VDD, VB = 0 V, 50% of Final Value,

10K/50K/100K 0.6/3/6 µs

R

= 5 kΩ, f = 1 kHz 14 nV/√Hz

WB

5, 9

Clock Level High or Low 25 ns

= 10 kΩ –1 ±0.4 +1 LSB

AB

= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB

AB

= 10 kΩ –1 ±0.5 +1 LSB

AB

= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB

AB

= +3 V or +5 V 40 100 Ω

20 ppm/°C

–2 –0.5 0 LSB
0 +0.5 +1 LSB

0V

H

H

10 pF
48 pF

DD

7.5 nA

5pF

2.7 5.5 V

= +5 V 15 40 µA

DD

= +5 V 75 200 µW

DD

H

H

H

650 kHz
142 kHz
69 kHz

20 ns
20 ns
10 ns

= VDD and VB = 0 V.

A

V

–2–

REV. 0

AD5220

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

CLK

U/D

A1

GND

V

DD

CS

B1
W1

AD5220

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C, unless otherwise noted)

A

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

V

A

AX–BX, AX–WX, BX–W

. . . . . . . . . . . . . . . . . . . . . . ±20 mA

X

Digital Input Voltage to GND . . . . . . . . . . . 0 V, V

DD

DD

+ 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

MAX) . . . . . . . .+150°C

J

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Resistance θ

JA

max–T

J

)/θ

A

JA

P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W

SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Table I. Truth Table

CS CLK U/D Operation

L t H Wiper Increment Toward Terminal A
L t L Wiper Decrement Toward Terminal B
H X X Wiper Position Fixed

1

CS

CLK

U/D

0

1
0

1
0

t

CSS

t

CH

t

CL

t

UDS

t

CSH

Figure 3. Detail Timing Diagram

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin
No. Name Description

1 CLK Serial Clock Input, Negative Edge Triggered
2U/D UP/DOWN Direction Increment Control
3 A1 Terminal A1
4 GND Ground
5 W1 Wiper Terminal
6 B1 Terminal B1
7 CS Chip Select Input, Active Low
8VDDPositive Power Supply

ORDERING GUIDE

Model k⍀ Temperature Range Package Descriptions Package Options

AD5220BN10 10 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR10 10 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM10 10 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN50 50 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR50 50 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM50 50 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN100 100 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR100 100 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM100 100 –40°C to +85°C 8-Lead µSOIC RM-8

NOTE
The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–REV. 0