ANALOG DEVICES AD2S81A, AD2S82A Service Manual

SIN I/P

SIGNAL

GND

COS I/P

ANALOG

GND

RIPPLE

CLK
+12V
–12V

COMP

DATA
LOAD

SEGMENT

SWITCHING

SC1

SC2

16 DATA BITS

BYTE

SELECT

BUSY DIR

AC ERROR
O/P

VCO I/P

AD2S82A

VCO O/P

16-BIT

UP/DOWN COUNTER

VCO DATA
TRANSFER

LOGIC

+5V
DIGITAL

GND

R-2R
DAC

INTEGRATOR

I/P

PHASE

SENSITIVE

DETECTOR

DEMOD

I/P

DEMOD

O/P

OUTPUT DATA LATCH

INTEGRATOR
O/P

A2

A1

A3

INHIBIT

ENABLE

查询AD2S81供应商查询AD2S81供应商

Variable Resolution, Monolithic

a

FEATURES
Monolithic (BiMOS ll) Tracking R/D Converter
Ratiometric Conversion
Low Power Consumption: 300 mW Typ
Dynamic Performance Set by User
Velocity Output
ESD Class 2 Protection (2,000 V Min)

AD2S81A
28-Lead DIP Package
Low Cost

AD2S82A
44-Lead PLCC Package
10-, 12-, 14- and 16-Bit Resolution Set by User
High Max Tracking Rate 1040 RPS (10 Bits)
VCO Output (Inter LSB Output)
Data Complement Facility
Industrial Temperature Range

APPLICATIONS
DC Brushless and AC Motor Control
Process Control
Numerical Control of Machine Tools
Robotics
Axis Control

GENERAL DESCRIPTION

The AD2S82A is a monolithic 10-, 12-, 14- or 16-bit tracking
resolver-to-digital converter contained in a 44-lead J leaded
PLCC package. Two extra functions are provided in the new
surface mount package–COMPLEMENT and VCO output.

The AD2S81A is a monolithic 12-bit fixed resolution tracking
resolver-to-digital converter packaged in a 28-lead DIP.

The converters allow users to select their own dynamic performance
with external components. This allows the users great flexibility in
defining the converter that best suits their system requirements.
The AD2S82A allows users to select the resolution to be 10, 12,
14 or 16 bits and to track resolver signals rotating at up to 1040
revs per second (62,400 rpm) when set to 10-bit resolution.

The AD2S81A and AD2S82A convert resolver format input
signals into a parallel natural binary digital word using a ratio­metric tracking conversion method. This ensures high-noise
immunity and tolerance of lead length when the converter is
remote from the resolver.

The output word is in a three-state digital logic form available in
two bytes on the 16 output data lines for the AD2S82A and on
eight output data lines for the AD2S81A. BYTE SELECT,
ENABLE and INHIBIT pins ensure easy data transfer to 8- and
16-bit data buses, and outputs are provided to allow for cycle or
pitch counting in external counters.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Resolver-to-Digital Converters

AD2S81A/AD2S82A

AD2S82A FUNCTIONAL BLOCK DIAGRAM

An analog signal proportional to velocity is also available and
can be used to replace a tachogenerator.

PRODUCT HIGHLIGHTS

Monolithic. A one-chip solution reduces the package size re-

quired and increases the reliability.

Resolution Set by User. Two control pins are used to select
the resolution of the AD2S82A to be 10, 12, 14 or 16 bits al­lowing the user to use the AD2S82A with the optimum resolu­tion for each application.

Ratiometric Tracking Conversion. Conversion technique
provides continuous output position data without conversion
delay and is insensitive to absolute signal levels. It also provides
good noise immunity and tolerance to harmonic distortion on
the reference and input signals.

Dynamic Performance Set by the User. By selecting exter­nal resistor and capacitor values the user can determine band­width, maximum tracking rate and velocity scaling of the
converter to match the system requirements. The external com­ponents required are all low cost, preferred value resistors and
capacitors, and the component values are easy to select using
the simple instructions given.

Velocity Output. An analog signal proportional to velocity is
available and is linear to typically one percent. This can be used
in place of a velocity transducer in many applications to provide
loop stabilization in servo controls and velocity feedback data.

Low Power Consumption. Typically only 300 mW.

MODELS AVAILABLE

Information on the models available is given in the Ordering
Guide.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD2S81A/AD2S82A–SPECIFICATIONS

(@ TA = +25ⴗC, unless otherwise noted)

AD2S81A AD2S82A

Parameter Conditions Min Typ Max Min Typ Max Units

SIGNAL INPUTS

Frequency 400 20,000 50 20,000 Hz
Voltage Level 1.8 2.0 2.2 1.8 2.0 2.2 V rms
Input Bias Current 60 150 60 150 nA

Input Impedance 1.0 1.0 MΩ
Maximum Voltage ±8 ±8V pk

REFERENCE INPUT

Frequency 400 20,000 50 20,000 Hz
Voltage Level 1.0 8.0 1.0 8.0 V pk
Input Bias Current 60 150 60 150 nA

Input Impedance 1.0 1.0 MΩ

CONTROL DYNAMICS

Repeatability 1 1 LSB
Allowable Phase Shift (Signals to Reference) –10 +10 –10 +10 Degrees
Tracking Rate 10 Bits 1040 rps

12 Bits 260 260 rps
14 Bits 65 rps

Bandwidth

1

16 Bits 16.25 rps
User Selectable

ACCURACY

Angular Accuracy H ⴞ22 + 1 LSB arc min

J ⴞ30 + 1 LSB ⴞ8 + 1 LSB arc min
K ⴞ4 + 1 LSB arc min

L ⴞ2 + 1 LSB arc min
Monotonicity Guaranteed Monotonic
Missing Codes (16-Bit Resolution) J, K 4 Codes

L 1 Code

VELOCITY SIGNAL

Linearity Over Full Range ±1 ⴞ3 ±1 ⴞ3 % FSD
Reversion Error ±2 ±2 % FSD

DC Zero Offset

2

66mV

DC Zero Offset Tempco –22 –22 µV/°C

Gain Scaling Accuracy ⴞ10 ⴞ10 % FSD

Output Voltage 1 mA Load ±8 ±9 ±10.5 ±8 ±9 ±10.5 V

Dynamic Ripple Mean Value 1.5 1.5 % rms O/P

Output Load 1.0 1.0 kΩ

INPUT/OUTPUT PROTECTION

Analog Inputs Overvoltage Protection ±8 ±8V
Analog Outputs Short Circuit O/P Protection ±5.6 ±8 ±10.4 ±5.6 ±8 ±10.4 mA

DIGITAL POSITION

Resolution 10, 12, 14 and 16
Output Format Bidirectional Natural Binary
Load 3 3 LSTTL

INHIBIT

3

Sense Logic LO to Inhibit
Time to Stable Data 600 600 ns

ENABLE

3

Logic LO Enables Position

Output. Logic HI Outputs in

High Impedance State
ENABLE/Disable Time 35 110 35 110 ns

BYTE SELECT

3

Sense
Logic HI MS Byte DB1–DB8,

(LS Byte DB9–DB16)
Logic LO LS Byte DB1–DB8,

(LS Byte DB9–DB16)

4

4

Time to Data Available 60 140 60 140 ns

SHORT CYCLE INPUTS

SC1 SC2

4, 5

Internally Pulled High

(100 kΩ) to +V

S

0 0 10 Bit
0 1 12 Bit
1 0 14 Bit
1 1 16 Bit

DATA LOAD

4, 5

Sense Internally Pulled High (100 kΩ) 150 300 ns

to +V

Logic LO Allows

S;

Data to Be Loaded into the

Counters from the Data Lines

–2–

REV. B

AD2S81A/AD2S82A

Parameter Conditions Min Typ Max Min Typ Max Units

AD2S81A AD2S82A

COMPLEMENT

4, 5

Internally Pulled High (100 kΩ) to

+VS; Logic LO to Activate; No
Connect for Normal Operation

3

BUSY

Sense Logic HI When Position O/P Changing
Width 200 600 200 600 ns
Load Use Additional Pull-Up 1 1 LSTTL

DIRECTION

3

Sense Logic HI Counting Up

Logic LO Counting Down

Max Load 3 3 LSTTL

RIPPLE CLOCK

3

Sense Logic HI, All 1s to All 0s

All 0s to All 1s
Width Dependent On Input Velocity 300 300
Reset Before Next Busy
Load 3 3 LSTTL

DIGITAL INPUTS

High Voltage, V

Low Voltage, V

IH

IL

INHIBIT, ENABLE 2.0 2.0 V

DB1–DB16, Byte Select

±VS = ±10.8 V, V

INHIBIT, ENABLE 0.8 0.8 V

= 5.0 V

L

DB1–DB16, Byte Select

±VS = ±13.2 V, V

= 5.0 V

L

DIGITAL INPUTS

High Current, I

Low Current, I

IH

IL

INHIBIT, ENABLE ⴞ100 ⴞ100 µA

DB1–DB16

±VS = ±13.2 V, V

INHIBIT, ENABLE ⴞ100 ⴞ100 µA

= 5.5 V

L

DB1–DB16, Byte Select

±VS = ±13.2 V, V

= 5.5 V

L

DIGITAL INPUTS

Low Voltage, V

Low Current, I

IL

IL

ENABLE = HI 1.0 1.0 V

SC1, SC2, Data Load

±VS = ±12.0 V, V

ENABLE = HI –400 –400 µA

= 5.0 V

L

SC1, SC2, Data Load

±VS = ±12.0 V, V

= 5.0 V

L

DIGITAL OUTPUTS

High Voltage, V

Low Voltage, V

OH

OL

DB1–DB16; RIPPLE CLK, DIR 2.4 2.4 V

±VS = ±12.0 V, V

I

= 100 µA

OH

DB1–DB16, RIPPLE CLK, DIR 0.4 0.4 V

±VS = ±12.0 V, V

IOL = 1.2 mA

= 4.5 V

L

= 5.5 V

L

THREE-STATE LEAKAGE DB1–DB16 Only

Current I

L

+V

= ±12.0 V, VL = 5.5 V ±100 ±100 µA

S

VOL = 0 V

+V

= ±12.0 V, VL = 5.5 V ±100 ±100 µA

S

VOH = 5.0 V

POWER SUPPLIES

Voltage Levels

+V

S

–V

S

+V

L

Current

+I

S

+I

S

+I

L

NOTES

1

Refers to small signal bandwidth.

2

Output offset dependent on value for R6.

3

Refer to timing diagram.

4

AD2S82A only.

5

These pins are referenced to +VS (i.e., HI = +12 V, LO = 0 V).

±VS @ ±12 V ⴞ12 ⴞ 23 ⴞ12 ⴞ 23 mA

±VS @ ±13.2 V ⴞ19 ⴞ 30 ⴞ19 ⴞ 30 mA

±VL @ ±5.0 V ⴞ0.5 ⴞ1.5 ⴞ0.5 ⴞ1.5 mA

+10.8 +13.2 +10.8 +13.2 V
–10.8 –13.2 –10.8 –13.2 V
+5 +13.2 +5 +13.2 V

Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.

REV. B

–3–

AD2S81A/AD2S82A–SPECIFICATIONS

(typical @ +25ⴗC unless otherwise noted)

Parameter Conditions Min Typ Max Min Typ Max Units

RATIO MULTIPLIER

AC Error Output Scaling 10 Bit 177.6 mV/Bit

PHASE SENSITIVE DETECTOR

Output Offset Voltage 12 12 mV
Gain

In Phase w.r.t. REF –0.882 –0.9 –0.918 –0.882 –0.9 –0.918 V rms/V dc
In Quadrature w.r.t. REF 0.04 0.04 V rms/V dc

Input Bias Current 60 150 60 150 nA

Input Impedance 1 1 MΩ
Input Voltage ±8 ±8V

INTEGRATOR

Open-Loop Gain At 10 kHz 57 63 57 63 dB
Dead Zone Current (Hysteresis) 100 100 nA/LSB
Input Offset Voltage 1 5 1 5 mV
Input Bias Current 60 150 60 150 nA

Output Voltage Range ±VS = ±10.8 V dc ±7V

VCO ±VS = ±12 V dc

Maximum Rate 1.0 1.1 1.0 1.1 MHz

VCO Rate Positive DIR 7.1 7.9 8.7 7.1 7.9 8.7 kHz/µA

VCO Power Supply Sensitivity

Increase +V

Decrease +V

Input Offset Voltage 1 5 1 5 mV
Input Bias Current 70 380 70 380 nA

Input Bias Current Tempco –1.22 –1.22 nA/°C
Input Voltage Range ±8 ±8V

Linearity of Absolute Rate

Full Range <2 <2 % FSD
Over 0% to 50% of Full Range <1 <1 % FSD

Reversion Error 1.5 1.5 % FSD

Sensitivity of Reversion Error ±8 ±8 %/V of

to Symmetry of Power Supplies Asymmetry

VCO Output

POWER SUPPLIES

Voltage Levels

+V
–V
+V

Current

+I
+I
+I

NOTES

1

The VCO output swings between ±3 V depending on the resolver direction.

2

AD2S82A only.

Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.

1, 2

S

S

L

S

S

L

12 Bit 44.4 44.4 mV/Bit
14 Bit 11.1 mV/Bit
16 Bit 2.775 mV/Bit

Negative DIR 7.1 7.9 8.7 7.1 7.9 8.7 kHz/µA

S

–V

S

S

–V

S

±VS @ ±12 V ⴞ12 ⴞ 23 ⴞ12 ⴞ 23 mA
±VS @ ±13.2 V ⴞ19 ⴞ 30 ⴞ19 ⴞ 30 mA
±VL @ ±5.0 V ⴞ0.5 ⴞ1.5 ⴞ0.5 ⴞ1.5 mA

AD2S81A AD2S82A

+0.5 +0.5 %/V
–8.0 –8.0 %/V
–8.0 –8.0 %/V
+2.0 +2.0 %/V

±2.7 ±3.0 ±3.3 V/LSB

+10.8 +13.2 +10.8 +13.2 V
–10.8 –13.2 –10.8 –13.2 V
+5 +13.2 +5 +13.2 V

ORDERING GUIDE

Operating
Temperature Package

Accuracy Ranges Options*

AD2S81AJD 30 arc min 0°C to +70°C D-28
AD2S82AHP 22 arc min –40°C to +85°C P-44A
AD2S82AJP 8 arc min –40°C to +85°C P-44A
AD2S82AKP 4 arc min –40°C to +85°C P-44A
AD2S82ALP 2 arc min –40°C to +85°C P-44A

*D = Ceramic DIP Package; P = Plastic Leaded Chip Carrier (PLCC) Package.

ESD SENSITIVITY

The AD2S81A and AD2S82A features an input protection circuit consisting of large “distributed”
diodes and polysilicon series resistors to dissipate both high energy discharge (Human Body Model)
and fast, low energy pulses (Charges Device Model).

T

he AD2S81A and AD2S82A is ESD protection Class II (2000 V min). Proper ESD precautions are
strongly recommended to avoid functional damage or performance degradation. For further informa­tion on ESD precautions, refer to Analog Devices ESD Prevention Manual.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. B

AD2S81A/AD2S82A

REFERENCE I/P

DEMOD I/P

DEMOD O/P
INTEGRATOR O/P

ANALOG GND

SIN I/P

+V

S

–V

S

RIPPLE CLK
DIR

AC ERROR O/P

COS I/P

INTEGRATOR I/P
VCO I/P

MSB DB1

BUSY

DB2

DIGITAL GND
DB3
DB4 BYTE SELECT
DB5
DB6

+V

L

DB7 DB8 LSB

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD2S81A

INHIBIT

ENABLE

7
8

9
10
11
12
13
14
15
16
17

6 5 4 3 2 1 44 43 42 41 40

39
38
37
36
35
34
33
32
31
30
29

18 19 20 21 22 23 24 25 26 27 28

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

NC = NO CONNECT

–V

S

RIPPLE CLK
DIR
BUSY
DATA LOAD

COMPLEMENT

SC2
SC1
DIGITAL GND

INHIBIT

NC

SIN O/P

+V

S

MSB DB1

NC

DB2
DB3
DB4
DB5
DB6
DB7
DB8

DB9

DB10

DB11

DB12

DB14

DB15

LSB DB16

+V

L

ENABLE

BYTE

SELECT

DB13

AD2S82A

SIGNAL GND

ANALOG GND

COS I/P

AC ERROR O/P

DEMOD I/P

REFERENCE I/P

DEMOD O/P

INTEGRATOR O/P

INTEGRATOR I/P

VCO O/P

VCO I/P

RECOMMENDED OPERATING CONDITIONS

Power Supply Voltage (+VS to –V
Power Supply Voltage V

. . . . . . . . . . . . . . . . . . +5 V dc ±10%

L

) . . . . . . . . . ±12 V dc ±10%

S

Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ±10%

Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak

Signal and Reference Harmonic Distortion . . . . . . . 10% (max)

Phase Shift Between Signal and Reference . ±10 Degrees (max)

Ambient Operating Temperature Range

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . –40°C to +85°C

PIN FUNCTION DESCRIPTIONS

Mnemonic Description

REFERENCE I/P Reference Signal Input
DEMOD I/P Demodulator Input
AC ERROR O/P Ratio Multiplier Output
COS I/P Cosine Input
ANALOG GND Power Ground
SIGNAL GND Resolver Signal Ground
SIN I/P Sine Input
+V

S

DB1–DB16 Parallel Output Data
+V

L

ENABLE Logic Hi-Output Data in High Impedance

BYTE SELECT Logic Hi-Most Significant Byte to DB1–DB8

INHIBIT Logic Lo Inhibits Data Transfer to Output Latches
DIGITAL GND Digital Ground
SC1–SC2* Select Converter Resolution
DATA LOAD* Logic Lo DB1–DB16 Inputs

BUSY Converter Busy, Data Not Valid While Busy Hi
DIR Logic State Defines Direction of Input Signal Rotation
RIPPLE CLK Positive Pulse when Converter Output Changes from

–V
VCO I/P VCO Input
INTEGRATOR I/P Integrator Input
INTEGRATOR O/P Integrator Output
DEMOD O/P Demodulator Output
COMPLEMENT* Active Logic Lo

VCO O/P* VCO Output

*AD2S82A Only.

Binary Resolution Degrees Minutes Seconds
Bits (N) (2N) /Bit /Bit /Bit

S

0 1 360.0 21600.0 1296000.0
1 2 180.0 10800.0 648000.0
2 4 90.0 5400.0 324000.0
3 8 45.0 2700.0 162000.0
4 16 22.5 1350.0 81000.0

5 32 11.25 675.0 40500.0
6 64 5.625 337.5 20250.0
7 128 2.8125 168.75 10125.0
8 256 1.40625 84.375 5062.5
9 512 0.703125 42.1875 2531.25

10 1024 0.3515625 21.09375 1265.625
11 2048 0.1757813 10.546875 632.8125
12 4096 0.0878906 5.273438 316.40625
13 8192 0.0439453 2.636719 158.20313
14 116384 0.0219727 1.318359 79.10156

15 32768 0.0109836 0.659180 39.55078
16 65536 0.0054932 0.329590 19.77539
17 131072 0.0027466 0.164795 9.88770

18 262144 0.0013733 0.082397 4.94385

REV. B –5–

Positive Power Supply

Logic Power Supply

State Logic Lo Present Data to the Output Latches

Logic Lo-Most Significant Byte to DB1–DB8

Logic Hi DB1–DB16 Outputs

1s to All 0s or Vice Versa
Negative Power Supply

Bit Weight Table

ABSOLUTE MAXIMUM RATINGS1 (with respect to GND)

2

+V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V dc

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –14 V dc

–V

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V

+V

L

Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

S

S

S

S

Any Logical Input . . . . . . . . . . . . . . . . . . . –0.4 V dc to +VL dc

Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V to –V

S

S

S

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 mW

Operating Temperature

Commercial (JD) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial (HP, JP, KP, LP) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature (All Grades) . . . . . . . . .–65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

CAUTION

1. Absolute Maximum Ratings are those values beyond which damage to the

device may occur.

2. Correct polarity voltages must be maintained on the +VS and –VS pins.

AD2S81A/AD2S82A PIN CONFIGURATIONS