Serial Configuration (EPCS) Devices
Datasheet
C51014-4.0 Datasheet
This datasheet describes serial configuration (EPCS) devices.
Supported Devices
Ta b l e 1 lists the supported Altera EPCS devices.
Table 1. Altera EPCS Devices
Device
Memory Size
(bits)
On-Chip
Decompression
Support
ISP Support
Cascading
Support
Reprogrammable
Recommended
Operating
Voltage (V)
EPCS1 1,048,576 No Yes No Yes 3.3
EPCS4 4,194,304 No Yes No Yes 3.3
EPCS16 16,777,216 No Yes No Yes 3.3
EPCS64 67,108,864 No Yes No Yes 3.3
EPCS128 134,217,728 No Yes No Yes 3.3
f For more information about programming EPCS devices using the Altera
Programming Unit (APU) or Master Programming Unit (MPU), refer to the Altera
Programming Hardware Datasheet.
f The EPCS device can be re-programmed in system with ByteBlasterII download
cable or an external microprocessor using SRunner. For more information, refer to
AN418: SRunner: An Embedded Solution for Serial Configuration Device Programming.
Features
EPCS devices offer the following features:
■ Supports active serial (AS) x1 configuration scheme
■ Easy-to-use four-pin interface
■ Low cost, low pin count, and non-volatile memory
■ Low current during configuration and near-zero standby mode current
■ 2.7-V to 3.6-V operation
■ EPCS1, EPCS4, and EPCS16 devices available in 8-pin small-outline integrated
■ EPCS64 and EPCS128 devices available in 16-pin SOIC package
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January 2012 Altera Corporation
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circuit (SOIC) package
ISO
9001:2008
Registered
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Page 2 Functional Description
■ Enables the Nios
interface
■ Reprogrammable memory with more than 100,000 erase or program cycles
■ Write protection support for memory sectors using status register bits
■ In-system programming (ISP) support with SRunner software driver
■ ISP support with USB-Blaster
■ Additional programming support with the APU and programming hardware
from BP Microsystems, System General, and other vendors
■ By default, the memory array is erased and the bits are set to
Functional Description
To configure a system using an SRAM-based device, each time you power on the
device, you must load the configuration data. The EPCS device is a flash memory
device that can store configuration data that you use for FPGA configuration purpose
after power on. You can use the EPCS device on all FPGA that support AS x1
configuration scheme.
For an 8-pin SOIC package, you can migrate vertically from the EPCS1 device to the
EPCS4 or EPCS16 device. For a 16-pin SOIC package, you can migrate vertically from
the EPCS64 device to the EPCS128 device.
processor to access unused flash memory through AS memory
, EthernetBlaster, or ByteBlaster II download cables
1
With the new data decompression feature supported, you can determine using which
EPCS device to store the configuration data for configuring your FPGA.
Example 1 shows how you can calculate the compression ratio to determine which
EPCS device is suitable for the FPGA.
Example 1. Compression Ratio Calculation
EP4SGX530 = 189,000,000 bits
EPCS128 = 134,217,728 bits
Preliminary data indicates that compression typically reduces the
configuration bitstream size by 35% to 55%. Assume w orst case that is 35%
decompression.
189,000,000 bits x 0.65 = 122,85 0,000 bits
The EPCS128 device is suitable.
f For more information about the FPGA decompression feature, refer to the
configuration chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
Active Serial FPGA Configuration Page 3
Figure 1 shows the EPCS device block diagram.
Figur e 1. EPCS Device Bl ock Diagram
EPCS Device
nCS
DCLK
Control
Logic
Decode Logic
Accessing Memory in EPCS Devices
You can access the unused memory locations of the EPCS device to store or retrieve
data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for
creating bus-based (especially microprocessor-based) systems in Altera devices.
SOPC Builder assembles library components such as processors and memories into
custom microprocessor systems.
I/O Shift
Register
Data Buffer
Memory
Array
DATA
ASDI
Status RegisterAddress Counter
SOPC Builder includes the EPCS device controller core, which is an interface core
designed specifically to work with the EPCS device. With this core, you can create a
system with a Nios embedded processor that allows software access to any memory
location within the EPCS device.
Active Serial FPGA Configuration
The following Altera FPGAs support the AS configuration scheme with EPCS devices:
■ Arria
■ Cyclone
■ All device families in the Stratix
There are four signals on the EPCS device that interface directly with the FPGA’s
control signals. The EPCS device signals are
the
1 For more information about the EPCS device pin description, refer to Table 22 on
page 36.
series
series
DATA0, DCLK, ASDO
, and
nCSO
series except the Stratix device family
DATA, DCLK, ASDI
, and
nCS
interface with
control signals on the FPGA, respectively.
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 4 Active Serial FPGA Configuration
Figure 2 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using a download cable.
Figur e 2. Alt era FPGA Configuration in AS Mode Using a Download Cable
VCC (1) VCC (1) VCC (1)
10 kΩ 10 kΩ 10 kΩ
CONF_DONE
nSTATUS
nCONFIG
EPCS Device (2)
nCE
10 kΩ
DATA
DCLK
nCS
ASDI
Pin 1
DATA0
DCLK
nCSO
ASDO
V
(1)
CC
(1), (4)
Altera FPGA
nCEO
MSEL[]
N.C.
(3)
Notes to Figure 2:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the
MSEL[]
input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
Active Serial FPGA Configuration Page 5
Figure 3 shows the configuration of an FPGA device in the AS configuration scheme
with an EPCS device using the APU or a third-party programmer.
Figur e 3. Alt era FPGA Configuration in AS Mode Usin g APU or a Thir d-party Programmer
VCC (1) VCC (1) VCC (1)
10 kΩ 10 kΩ 10 kΩ
Altera FPGA
CONF_DONE
nSTATUS
nCONFIG
EPCS Device (2)
nCE
DATA
DCLK
nCS
ASDI
Notes to Figure 3:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the
device handbook.
(4) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
MSEL[]
input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
DATA0
DCLK
nCSO
ASDO
(1) , (4)
nCEO
MSEL[]
N.C.
(3)
In an AS configuration, the FPGA acts as the configuration master in the
configuration flow and provides the clock to the EPCS device. The FPGA enables the
EPCS device by pulling the
nCS
signal low using the
nCSO
signal as shown in Figure 2
and Figure 3. Then, the FPGA sends the instructions and addresses to the EPCS device
using the
configuration data to the FPGA’s
latched into the FPGA on the next
ASDO
signal. The EPCS device responds to the instructions by sending the
DATA0
pin on the falling edge of
DCLK
signal’s falling edge.
DCLK
. The data is
1 Before the FPGA enters configuration mode, ensure that VCC of the EPCS device is
ready. If VCC is not ready, you must hold
nCONFIG
low until all power rails of EPCS
device are ready.
The FPGA controls the
mode. If the
CONF_DONE
signal goes high too early, the FPGA pulses its
reconfiguration. If the configuration is successful, the FPGA releases the
pin, allowing the external 10-k resistor to pull the
initialization begins after the
nSTATUS
and
CONF_DONE
pins during configuration in the AS
signal does not go high at the end of configuration, or if the
nSTATUS
pin low to start a
CONF_DONE
CONF_DONE
CONF_DONE
pin goes high. After the initialization, the
signal high. The FPGA
FPGA enters user mode.
f For more information about configuring the FPGAs in AS configuration mode or
other configuration modes, refer to the configuration chapter in the appropriate
device handbook.
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 6 Active Serial FPGA Configuration
DATA
DCLK
nCS
ASDI
DATA0
DCLK
nCSO
nCE
nCONFIG
nSTATUS
MSEL[ ]
nCEO
CONF_DONE
ASDO
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
(3)
Altera FPGA (Master)
DATA0
DCLK
nCE
nCONFIG
nSTATUS
MSEL[ ]
nCEO
CONF_DONE
(4)
Altera FPGA (Slave)
EPCS Device (2)
N.C.
You can configure multiple devices with a single EPCS device. However, you cannot
cascade EPCS devices. To ensure that the programming file size of the cascaded
FPGAs does not exceed the capacity of an EPCS device, refer to Table 1 on page 1.
Figure 4 shows the AS configuration scheme with multiple FPGAs in the chain. The
first FPGA is the configuration master and its
following FPGAs are configuration slave devices and their
MSEL[]
pins are set to AS mode. The
MSEL[]
pins are set to PS
mode.
Figure 4. Multiple Devices in AS Mode
(1), (5)
Notes to Figure 4:
(1) For more information about the VCC value, refer to the configuration chapter in the appropriate device handbook.
(2) EPCS devices cannot be cascaded.
(3) Connect the
MSEL[]
input pins to select the AS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(4) Connect the
MSEL[]
input pins to select the PS configuration mode. For more information, refer to the configuration chapter in the appropriate
device handbook.
(5) For more information about configuration pin I/O requirements in an AS configuration scheme for an Altera FPGA, refer to the configuration
chapter in the appropriate device handbook.
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 7
EPCS Device Memory Access
This section describes the memory array organization and operation codes of the
EPCS device. For the timing specifications, refer to “Timing Information” on page 29.
Memory Array Organization
Ta b l e 2 lists the memory array organization details in EPCS128, EPCS64, EPCS16,
EPCS4, and EPCS1 devices.
Table 2. Memory Ar ray Organizat ion in EPCS Devices
Details EPCS128 EPCS64 EPCS16 EPCS4 EPCS1
Bytes
Number of sect ors 64 128 32 8 4
Bytes per sector
Pages per sector 1,024 256 256 256 128
Total number of
pages
Bytes per page 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes
16,777,216 bytes
(128 Mb)
262,144 by tes
(2 Mb)
65,536 32,768 8,192 2,048 512
8,388,608 bytes
(64 Mb)
65,536 bytes
(512 Kb)
2,097,152 bytes
(16 Mb)
65,536 bytes
(512 Kb)
524,288 bytes
(4 Mb)
65,536 bytes
(512 Kb)
131,072 bytes
(1 Mb)
32,768 bytes
(256 Kb)
Ta b l e 3 through Table 7 on page 15 list the address range for each sector in EPCS128,
EPCS64, EPCS16, EPCS4, and EPCS1 devices.
Table 3. Address Range for Sectors in EPCS128 Devices (Part 1 of 3)
Sector
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
Address Range (Byte Addresses in HEX)
Start End
H'FC0000 H'FFFFFF
H'F80000 H'FBFFFF
H'F40000 H'F7FFFF
H'F00000 H'F3FFFF
H'EC0000 H'EFFFFF
H'E80000 H'EBFFFF
H'E40000 H'E7FFFF
H'E00000 H'E3FFFF
H'DC0000 H'DFFFFF
H'D80000 H'DBFFFF
H'D40000 H'D7FFFF
H'D00000 H'D3FFFF
H'CC0000 H'CFFFFF
H'C80000 H'CBFFFF
H'C40000 H'C7FFFF
H'C00000 H'C3FFFF
H'BC0000 H'BFFFFF
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 8 EPCS Device Memory Access
Table 3. Address Range for Sectors in EPCS128 Devices (Part 2 of 3)
Sector
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Address Range (Byte Addresses in HEX)
Start End
H'B80000 H'BBFFFF
H'B40000 H'B7FFFF
H'B00000 H'B3FFFF
H'AC0000 H'AFFFFF
H'A80000 H'ABFFFF
H'A40000 H'A7FFFF
H'A00000 H'A3FFFF
H'9C0000 H'9FFFFF
H'980000 H'9BFFFF
H'940000 H'97FFFF
H'900000 H'93FFFF
H'8C0000 H'8FFFFF
H'880000 H'8BFFFF
H'840000 H'87FFFF
H'800000 H'83FFFF
H'7C0000 H'7FFFFF
H'780000 H'7BFFFF
H'740000 H'77FFFF
H'700000 H'73FFFF
H'6C0000 H'6FFFFF
H'680000 H'6BFFFF
H'640000 H'67FFFF
H'600000 H'63FFFF
H'5C0000 H'5FFFFF
H'580000 H'5BFFFF
H'540000 H'57FFFF
H'500000 H'53FFFF
H'4C0000 H'4FFFFF
H'480000 H'4BFFFF
H'440000 H'47FFFF
H'400000 H'43FFFF
H'3C0000 H'3FFFFF
H'380000 H'3BFFFF
H'340000 H'37FFFF
H'300000 H'33FFFF
H'2C0000 H'2FFFFF
H'280000 H'2BFFFF
H'240000 H'27FFFF
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 9
Table 3. Address Range for Sectors in EPCS128 Devices (Part 3 of 3)
Sector
8
7
6
5
4
3
2
1
0
Address Range (Byte Addresses in HEX)
Start End
H'200000 H'23FFFF
H'1C0000 H'1FFFFF
H'180000 H'1BFFFF
H'140000 H'17FFFF
H'100000 H'13FFFF
H'0C0000 H'0FFFFF
H'080000 H'0BFFFF
H'040000 H'07FFFF
H'000000 H'03FFFF
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 10 EPCS Device Memory Access
Table 4. Address Range for Sectors in EPCS64 Devices (Part 1 of 4)
Sector
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
Address Range (Byte Addresses in HEX)
Start End
H'7F0000 H'7FFFFF
H'7E0000 H'7EFFFF
H'7D0000 H'7DFFFF
H'7C0000 H'7CFFFF
H'7B0000 H'7BFFFF
H'7A0000 H'7AFFFF
H'790000 H'79FFFF
H'780000 H'78FFFF
H'770000 H'77FFFF
H'760000 H'76FFFF
H'750000 H'75FFFF
H'740000 H'74FFFF
H'730000 H'73FFFF
H'720000 H'72FFFF
H'710000 H'71FFFF
H'700000 H'70FFFF
H'6F0000 H'6FFFFF
H'6E0000 H'6EFFFF
H'6D0000 H'6DFFFF
H'6C0000 H'6CFFFF
H'6B0000 H'6BFFFF
H'6A0000 H'6AFFFF
H'690000 H'69FFFF
H'680000 H'68FFFF
H'670000 H'67FFFF
H'660000 H'66FFFF
H'650000 H'65FFFF
H'640000 H'64FFFF
H'630000 H'63FFFF
H'620000 H'62FFFF
H'610000 H'61FFFF
H'600000 H'60FFFF
H'5F0000 H'5FFFFF
H'5E0000 H'5EFFFF
H'5D0000 H'5DFFFF
H'5C0000 H'5CFFFF
H'5B0000 H'5BFFFF
H'5A0000 H'5AFFFF
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
EPCS Device Memory Access Page 11
Table 4. Address Range for Sectors in EPCS64 Devices (Part 2 of 4)
Sector
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
Address Range (Byte Addresses in HEX)
Start End
H'590000 H'59FFFF
H'580000 H'58FFFF
H'570000 H'57FFFF
H'560000 H'56FFFF
H'550000 H'55FFFF
H'540000 H'54FFFF
H'530000 H'53FFFF
H'520000 H'52FFFF
H'510000 H'51FFFF
H'500000 H'50FFFF
H'4F0000 H'4FFFFF
H'4E0000 H'4EFFFF
H'4D0000 H'4DFFFF
H'4C0000 H'4CFFFF
H'4B0000 H'4BFFFF
H'4A0000 H'4AFFFF
H'490000 H'49FFFF
H'480000 H'48FFFF
H'470000 H'47FFFF
H'460000 H'46FFFF
H'450000 H'45FFFF
H'440000 H'44FFFF
H'430000 H'43FFFF
H'420000 H'42FFFF
H'410000 H'41FFFF
H'400000 H'40FFFF
H'3F0000 H'3FFFFF
H'3E0000 H'3EFFFF
H'3D0000 H'3DFFFF
H'3C0000 H'3CFFFF
H'3B0000 H'3BFFFF
H'3A0000 H'3AFFFF
H'390000 H'39FFFF
H'380000 H'38FFFF
H'370000 H'37FFFF
H'360000 H'36FFFF
H'350000 H'35FFFF
H'340000 H'34FFFF
Serial Configuration (EPCS) Devices DatasheetJanuary 2012 Altera Corporation
Page 12 EPCS Device Memory Access
Table 4. Address Range for Sectors in EPCS64 Devices (Part 3 of 4)
Sector
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
Address Range (Byte Addresses in HEX)
Start End
H'330000 H'33FFFF
H'320000 H'32FFFF
H'310000 H'31FFFF
H'300000 H'30FFFF
H'2F0000 H'2FFFFF
H'2E0000 H'2EFFFF
H'2D0000 H'2DFFFF
H'2C0000 H'2CFFFF
H'2B0000 H'2BFFFF
H'2A0000 H'2AFFFF
H'290000 H'29FFFF
H'280000 H'28FFFF
H'270000 H'27FFFF
H'260000 H'26FFFF
H'250000 H'25FFFF
H'240000 H'24FFFF
H'230000 H'23FFFF
H'220000 H'22FFFF
H'210000 H'21FFFF
H'200000 H'20FFFF
H'1F0000 H'1FFFFF
H'1E0000 H'1EFFFF
H'1D0000 H'1DFFFF
H'1C0000 H'1CFFFF
H'1B0000 H'1BFFFF
H'1A0000 H'1AFFFF
H'190000 H'19FFFF
H'180000 H'18FFFF
H'170000 H'17FFFF
H'160000 H'16FFFF
H'150000 H'15FFFF
H'140000 H'14FFFF
H'130000 H'13FFFF
H'120000 H'12FFFF
H'110000 H'11FFFF
H'100000 H'10FFFF
H'0F0000 H'0FFFFF
H'0E0000 H'0EFFFF
Serial Configuration (EPCS) Devices Datasheet January 2012 Altera Corporation
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