DSP Development Kit, Stratix V Edition
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01070-1.0
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Registered
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix V GS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
MAX V CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Load Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Memory Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
High-Speed Mezzanine Cards (HSMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43
40G QSFP Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
QDRII+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50
RLDRAM II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
iv Contents
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–60
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61
Appendix A. Board Revision History
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
This document describes the hardware features of the DSP Development Kit,
®
Stratix
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The DSP Development Kit, Stratix V Edition provides a hardware platform for
developing and prototyping high-performance and high-bandwidth application
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of Stratix V DSP designs.
1. Overview
V Edition, including the detailed pin-out and component reference
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera
®
and various
partners.
f To see a list of the latest HSMC cards available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the PCI Express hard IP
implementation, partial reconfiguration, and programmable power technology
ensure that designs implemented in the Stratix V DSPs operate faster, with lower
power than in previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Stratix V device family, refer to the Stratix V Device Handbook.
■ PCI Express hard IP implementation, refer to the Stratix V Hard IP for PCI Express
User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
Board Component Blocks
The board features the following major component blocks:
■ Altera Stratix V FPGA (5SGSMD5K2F40C2N) in the 1517-pin FineLine BGA
package
■ 457,000 LEs
■ 172,600 adaptive logic modules (ALMs)
■ 39-Mbits embedded memory
■ 36 transceivers (14.1 Gbps)
■ 174 full-duplex LVDS channels
■ 24 phase locked loops (PLLs)
■ 3,180 18x18-bit multipliers
■ 900-mV core voltage
■ 864 user I/Os
■ 1 PCI Express hard IP blocks
■ MAX
®
V CPLD (5M2210ZF256C4) System Controller in the 256-pin FineLine BGA
package
■ 2,210 LEs
■ 203 user I/Os
■ 1.8-V core voltage
■ FPGA configuration circuitry
■ MAX
II CPLD (EPM570GM100) and Flash Fast Passive Parallel (FPP)
configuration
■ On-Board USB-Blaster
TM
II for use with the Quartus® II Programmer, Nios®II
Software Build Tools, and System Console.
■ On-Board clocking circuitry
■ 50-MHz, 100-MHz, 125-MHz, and programmable oscillators
■ SMA connector for clock input (LVPECL)
■ Memory devices
■ 1152-Mbyte DDR3 SDRAM with a 72-bit data bus
■ 72-Mbyte CIO RLDRAM II with a 18-bit data bus
■ 4.5-Mbyte QDRII+ SRAM with a 18-bit data bus (footprint is compatible for
9-Mbyte QDRII with a 18-bit data bus)
■ Two 512-Mbyte synchronous flash with a 16-bit data bus
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 1: Overview 1–3
Board Component Blocks
■ Communication ports
■ PCI Express (PCIe) x8 edge connector
■ Two H S MC po rt s
■ One universal HSMC port A
■ One DQS-type HSMC port B
■ SMB for SDI input and output
■ QSFP
■ USB 2.0
■ Gigabit Ethernet
■ LCD header
■ General user I/O
■ 16 user LEDs
■ Two-line character LCD display
■ Six configuration status LED
■ One transmit/receive LED (TX/RX) per HSMC interface
■ Five PCI Express LEDs
■ Four Ethernet LEDs
■ Push buttons and DIP switches
■ One CPU reset push button
■ Three general user push buttons
■ Two configuration push buttons
■ Eight user DIP switches
■ Four MAX
V control DIP switches
■ Power
■ 19-V (laptop) DC input
■ PCI Express edge connector power
■ On-Board power measurement circuitry
■ System monitoring
■ Power—voltage, current, wattage
■ Temperature—FPGA die, local board
■ Mechanical
■ PCI Express short form factor
■ PCI Express chassis or bench-top operation
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
1–4 Chapter 1: Overview
Port A
Port B
1152 MB
DDR3
4.5 MB
QDRII+ SRAM
Push Buttons
and Switches
LED
CPLD
64 MB
Flash
64 MB
Flash
x8 Edge
Programmable
Oscillators
50 MHz, 100 MHz,
148 MHz, 156 MHz
QSFP
REFCLK
SMA IN
GigE
PHY
SDI
TX/TX
On-Board
USB- Blaster II
and USB Interface
x4 XCVR
x1 (LVPECL)
x1
x1 XCVR
x72
x18
72 MB CIO
RLDRAM II
x18
EPCQ
x4
x4
x8
x16
x4
XCVR x8
x32 Config
x32
x80
CLKIN x3
CLKOUT x3
XCVR x8
x80
CLKIN x3
CLKOUT x3
XCVR x6
ADDR
JTAG Chain
5SGSMD5K2F40C2N
Micro-USB
2.0
x19 USB Interface
LVDS/Single-Ended
DQS/Single-Ended
x16
x16
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the DSP Development Kit, Stratix V Edition.
Figure 1–1. DSP Development Kit, Stratix V Edition Block Diagram
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
2. Board Components
This chapter introduces all the important components on the DSP Development Kit,
Stratix V Edition. Figure 2–1 illustrates major component locations and Ta bl e 2– 1
provides a brief description of all features of the board.
1 A complete set of schematics, a physical layout database, and GERBER files for the
development board reside in the DSP Development Kit, Stratix V Edition documents
directory.
f For information about powering up the board and installing the demo software, refer
to the DSP Development Kit, Stratix V Edition User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix V GS” on page 2–5
■ “MAX V CPLD System Controller” on page 2–6
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–23
■ “General User Input/Output” on page 2–26
■ “Components and Interfaces” on page 2–31
■ “Memory” on page 2–46
■ “Power Supply” on page 2–57
■ “Statement of China-RoHS Compliance” on page 2–61
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–2 Chapter 2: Board Components
HSMC Port B (J2)
Power Switch (SW2)
DC Input Jack (J4)
QDRII+ x18 (U5)
DDR3 Memory
x8 (U12)
x16 (U17, U21, U23, U28)
JTAG Header (J10)
Clock Input
SMA Connector
(J13, J14)
CPU Reset Push Button (S4)
MAX V CPLD
System Controller (U4)
Character LCD (J15)
PCI Express
Edge Connector
(J18)
RLDRAM II x18
Memory
(U20)
Fan Power Header
(J11)
Transceiver TX SMA
Connectors (J3, J6)
Flash x32 Memory
(U10, U11)
Load, Error, and Configuration
Done LEDs (D15-D17)
HSMC Port A (J1)
SDI Video Port
(J16, J17)
Gigabit Ethernet Port (J9)
On-Board USB-Blaster II
Connector (J7)
Program Load and Program Select Push Buttons (S2, S3)
MAX V Reset Push Button (S1)
Stratix V GS FPGA (U15)
General User Push Buttons (S5, S6, S7)
User DIP Switch (SW1)
Program Select LEDs (D4-D6)
40G QSFP Connector
and Cage Assembly (J12)
Board Overview
Board Overview
This section provides an overview of the DSP Development Kit, Stratix V Edition,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the DSP Development Kit, Stratix V Edition Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U15 FPGA 5SGSMD5K2F40C2N, 1517-pin BGA.
U4 CPLD 5M2210ZF256C4, 256-pin BGA.
Configuration, Status, and Setup Elements
J10 JTAG header
J7 On-Board USB-Blaster II Micro-USB 2.0 connector for programming and debugging the FPGA.
SW3 JTAG DIP switch
SW4 FPGA mode select DIP switch Sets the Stratix V
SW5 Board settings DIP switch
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Provides access to the JTAG chain by using an external USB-Blaster
cable (disables the on-board USB-Blaster II).
Enables and disables devices in the JTAG chain. This switch is located
on the back of the board.
MSEL[4:0]
Controls the MAX V CPLD System Controller functions such as clock
select, clock enable, factory or user design load from flash and
FACTORY
signal command sent at power up. This switch is located at
the bottom of the board.
pins.
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 2 of 4)
Board Reference Type Description
SW6 PCI Express DIP switch
Controls the PCI Express lane width by connecting
together on the PCI Express edge connector. This switch is located at
prsnt
pins
the back of the board.
S3 Program select push button
S2 Program load push button
Toggles the program LEDs which selects the program image that loads
from flash memory to the FPGA.
Configures the FPGA from flash memory image based on the program
LEDs.
Illuminates to show the LED sequence that determines which flash
D4, D5, D6 Program LEDs
memory image loads to the FPGA when you press the program load
push button.
D17 Configuration done LED Illuminates when the FPGA is configured.
D15 Load LED Illuminates during FPGA configuration.
D16 Error LED Illuminates when the FPGA configuration from flash fails.
D24 Power LED Illuminates when 5-V power is present.
Indicate the transmit or receive activity of the System Console USB
D25, D26 System Console TX/RX LEDs
interface. The TX and RX LEDs would flicker if the link is in use and
active. The LEDs are either off when not in use or on when in use but
idle.
Indicate the transmit or receive activity of the JTAG chain. The TX and
D27, D28 JTAG TX/RX LEDs
RX LEDs would flicker if the link is in use and active. The LEDs are
either off when not in use or on when in use but idle.
D29, D30, D31,
D32
Ethernet LEDs Indicate the connection speed as well as transmit or receive activity.
D3, D13 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D1 HSMC port A Present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D11, D14 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.
D2 HSMC port B Present LED Illuminates when a daughtercard is plugged into the HSMC port B.
D33, D34 PCI Express Gen2/Gen3 LED
D35, D36, D37 PCI Express Link LEDs
You can configure these LEDs to illuminate when PCI Express is in
Gen2 or Gen3 mode.
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
X1 125 M oscillator
U38 Quad-output oscillator
U46 Quad-output oscillator
X6 148.5 M oscillator
125.000-MHz crystal oscillator for Gigabit Ethernet, Serial RapidIO™
(SRIO), or PCI Express.
Programmable oscillator with default frequencies of 100 MHz,
156.25 MHz, 625 MHz, and 270 MHz.
Programmable oscillator with default frequencies of 125 MHz,
644.53125 MHz, 282.5 MHz, and 125 MHz.
148.500-MHz voltage controlled crystal oscillator for SDI video. This
oscillator is programmable to any frequency between 20-810 MHz.
100.000-MHz (programmable to any frequency between 20–810 MHz)
X4 100 M oscillator
crystal oscillator for PCI Express or general use such as memories.
Multiplex with
CLKIN_SMA_P
or
CLKIN_SMA_N
based on CLK_SEL
switch value.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 3 of 4)
Board Reference Type Description
X3 50 M oscillator 50.000-MHz crystal oscillator for general purpose logic.
J13, J14 Clock input SMAs
Drives LVPECL-compatible clock inputs into the clock multiplexer
buffer.
U4 100 M oscillator 100-MHz crystal oscillator for the MAX V CPLD System Controller.
General User Input and Output
D7-D10,
D18-D21
User LEDs
Eight bi-color LEDs (green and red) for 16 user LEDs. Illuminates when
driven low.
SW1 User DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.
S1 MAX V reset push button The default reset for the MAX V CPLD System Controller.
S4 CPU reset push button The default reset for the FPGA logic.
S5, S6, S7 General user push buttons Three user push buttons. Driven low when pressed.
Memory Devices
U12, U17, U21,
U23, U28
DDR3 x72
A 1152-Mbyte DDR3 SDRAM with a 72-bit data bus. The 72-bit data
bus consists of four x16 devices and one x8 device with a single
address or command bus.
A 4.5-Mbyte QDRII+ SRAM with a 18-bit data bus. The device has a
U5 QDRII+ x18
separate 18-bit read and 18-bit write port with DDR signalling at up to
550 MHz.
U20 RLDRAM II x18
A 72-Mbyte CIO RLDRAM II with a 18-bit data bus. The 18-bit data bus
consists of a single x18 device with a single address or command bus.
Two 512-Mbyte synchronous flash devices with a 16-bit data buses for
U10, U11 Flash x32
non-volatile memory. The board supports two flash devices of 16-bit
interface each, which combine to allow for 1-Gbyte synchronous flash
with a 32-bit data bus.
Communication Ports
J18 PCI Express edge connector
Made of gold-plated edge fingers for up to ×8 signaling in either Gen1,
Gen2, or Gen3 mode.
J12 QSFP connector Provides four transceiver channels for a 40G QSFP module.
J1 HSMC port A
J2 HSMC port B
Provides eight transceiver channels and 84 CMOS or 17 LVDS
channels per the HSMC specification.
Provides four transceiver channels and 84 CMOS or a DQ/DQS
interface.
RJ-45 connector which provides a 10/100/1000 Ethernet connection
J9 Gigabit Ethernet port
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MAC MegaCore function in SGMII mode.
Video and Display Ports
Two 75-Ω system management bus (SMB) connectors which provide a
J16, J17 SDI video port
full-duplex SDI interface through a LMH0303 driver and LMH0384
cable equalizer.
J15 Character LCD header
A single 14-pin 0.1" pitch dual-row header which interfaces to the 16
character × 2 line LCD module.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–5
Featured Device: Stratix V GS
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 4 of 4)
Board Reference Type Description
Power Supply
J18 PCI Express edge connector
J4 DC input jack Accepts a 19-V DC power supply.
SW2 Power switch
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
Switch to power on or off the board when power is supplied from the
DC input jack.
Featured Device: Stratix V GS
The Stratix V GS development board features the Stratix V GS 5SGSMD5K2F40C2N
device (U15) in a 1517-pin FineLine BGA package.
f For more information about the Stratix V device family, refer to the Stratix V Device
Handbook.
Tab le 2– 2 describes the features of the Stratix V GS 5SGSMD5K2F40C2N device.
Table 2–2. Stratix V GS 5SGSMD5K2F40C2N Features
ALMs
172,600 457,000 690,400 2,014 5.27 3,180 24 36
Equivalent
LEs
Registers
M20K
Blocks
MLAB
Blocks (Mb)
18-bit × 18-bit
Multipliers
PLLs
Transceiver
Channels
(14.1 Gbps)
Tab le 2– 3 lists the Stratix V GS component reference and manufacturing information.
Table 2–3. Stratix V GS Component Reference and Manufacturing Information
Board
Reference
U15
Description Manufacturer
FPGA, Stratix V GS F1517, 457K
LEs, leadfree
Corporation 5SGSMD5K2F40C2NC2N www.altera.com
Altera
Manufacturing
Part Number
I/O Resources
Tab le 2– 4 lists the Stratix V GS device pin count and usage by function on the
development board.
Table 2–4. Stratix V GS Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
DDR3 1.5-V SSTL 126 1 Diff ×9DQS
RLDRAM II 1.8-V SSTL 57 1 Diff ×3 DQS
QDRII+ SRAM 1.8-V HSTL 67 1 Diff ×2 DQS
MAX V System Controller 1.5-V CMOS 8 —
Flash 1.8-V CMOS 68 —
PCI Express ×8 2.5-V CMOS + XCVR 43 1 REFCLK
Package Type
1517-pin
FineLine BGA
Manufacturer
Website
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–6 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–4. Stratix V GS Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
HSMC Port A 2.5-V CMOS + LVDS + XCVR 118 1 REFCLK
HSMC Port B 2.5-V CMOS + DQS + XCVR 104 1 REFCLK
Gigabit Ethernet 2.5-V CMOS + LVDS 8 —
On-Board USB-Blaster II
1.5-V CMOS 18 —
3.3-V CMOS 1 —
SDI Video 2.5-V CMOS + XCVR 8 1 REFCLK
QSFP 2.5-V CMOS + XCVR 23 1 REFCLK
Buttons 1.8/2.5-V CMOS 4 1 DEV_CLRn
Switches 1.8-V CMOS 8 —
Character LCD 2.5-V CMOS 11 —
LEDs 1.8/2.5-V CMOS 16 —
Clocks or Oscillators 1.8-V CMOS + LVDS 25 9 REFCLK
Device I/O Total:
MAX V CPLD System Controller
The board utilizes the 5M2210ZF256C4 System Controller, an Altera MAX V CPLD,
for the following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temp e ra tu re m onito ri ng
■ Fan control
■ Control registers for clocks
■ Control registers for remote system update
713
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–7
MAX V CPLD System Controller
Figure 2–2 illustrates the MAX V CPLD System Controller's functionality and external
circuit connections as a block diagram.
Figure 2–2. MAX V CPLD System Controller Block Diagram
MAX V System Controller
PC
On-Board
USB-Blaster II
Power
Measurement
Results
Temperature
Measurement
Results
JTAG Control
Encoder
LTC2418
Controller
LTC2990
Controller
MAX1619
Controller
SLD-HUB
Virtual-JTAG
Decoder
Information
Register
Control
Register
PFL
Si570
Controller
Si571
Controller
Si5538
Controller
FSM BUS
FPGA
Flash
Flash
GPIO
Si570
Programmable
Oscillator
Si571
Oscillator
Si5338
Oscillator
Si5338
Oscillator
Programmable
Programmable
Programmable
Tab le 2– 5 lists the I/O signals present on the MAX V CPLD System Controller. The
signal names and functions are relative to the MAX V device (U4).
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 1 of 6)
Schematic Signal Name
5M2210_JTAG_TMS
CLK125_EN
CLK50_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLKIN_50
CLOCK_SCL
CLOCK_SDA
CPU_RESETn
FACTORY_LOAD
FACTORY_REQUEST
MAX V CPLD
Pin Number
N4 — 2.5-V MAX V JTAG TMS
B9 — 2.5-V 125 MHz oscillator enable
E9 — 2.5-V 50 MHz oscillator enable
J5 — 2.5-V 100 MHz configuration clock input
A15 — 2.5-V DIP - clock oscillator enable
A13 — 2.5-V DIP - clock select SMA or oscillator
J12 AN6 1.8-V 50 MHz clock input
C9 — 2.5-V Programmable oscillator I2C clock
D9 — 2.5-V Programmable oscillator I2C data
D10 AM34 2.5-V FPGA reset push button
A2 — 2.5-V
R14 — 1.8-V
Stratix V GS
Pin Number
I/O
Standard
Description
DIP - load factory image or user1 image
from flash at power-up
On-Board USB-Blaster II request to send
FACTORY command
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–8 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 2 of 6)
Schematic Signal Name
FACTORY_STATUS
FLASH_ADVn
FLASH_CEn0
FLASH_CEn1
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYN0
FLASH_RDYBSYN1
FLASH_RESETn
FLASH_WEn
FM_A0
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_A23
FM_A24
FM_A25
FM_D0
FM_D1
MAX V CPLD
Pin Number
N12 — 1.8-V
Stratix V GS
Pin Number
I/O
Standard
Description
On-Board USB-Blaster II FACTORY
command status
N7 AP7 1.8-V FM bus flash memory address valid
R5 AV14 1.8-V FM bus flash memory chip enable 0
M7 AW13 1.8-V FM bus flash memory chip enable 1
R6 AM8 1.8-V FM bus flash memory clock
M6 AJ7 1.8-V FM bus flash memory output enable
T5 AL6 1.8-V FM bus flash memory chip ready 0
R7 AN7 1.8-V FM bus flash memory chip ready 1
P7 AJ6 1.8-V FM bus flash memory reset
N6 AN8 1.8-V FM bus flash memory write enable
E14 AW19 1.8-V FM address bus
C14 AV19 1.8-V FM address bus
C15 AM16 1.8-V FM address bus
E13 AL16 1.8-V FM address bus
E12 AF16 1.8-V FM address bus
D15 AG16 1.8-V FM address bus
F14 AN17 1.8-V FM address bus
D16 AM17 1.8-V FM address bus
F13 AP16 1.8-V FM address bus
E15 AN16 1.8-V FM address bus
E16 AT17 1.8-V FM address bus
F15 AR17 1.8-V FM address bus
G14 AU16 1.8-V FM address bus
F16 AU17 1.8-V FM address bus
G13 AW16 1.8-V FM address bus
G15 AV16 1.8-V FM address bus
G12 AW17 1.8-V FM address bus
G16 AV17 1.8-V FM address bus
H14 AU6 1.8-V FM address bus
H15 AT6 1.8-V FM address bus
H13 AL17 1.8-V FM address bus
H16 AK17 1.8-V FM address bus
J13 AE16 1.8-V FM address bus
R3 AE17 1.8-V FM address bus
P5 AH16 1.8-V FM address bus
T2 AP21 1.8-V FM address bus
J14 AN21 1.8-V FM data bus
J15 AD21 1.8-V FM data bus
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–9
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 3 of 6)
Schematic Signal Name
FM_D2
FM_D3
FM_D4
FM_D5
FM_D6
FM_D7
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
FM_D16
FM_D17
FM_D18
FM_D19
FM_D20
FM_D21
FM_D22
FM_D23
FM_D24
FM_D25
FM_D26
FM_D27
FM_D28
FM_D29
FM_D30
FM_D31
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
K16 AD20 1.8-V FM data bus
K13 AG21 1.8-V FM data bus
K15 AH21 1.8-V FM data bus
K14 AE21 1.8-V FM data bus
L16 AE20 1.8-V FM data bus
L11 AL22 1.8-V FM data bus
L15 AK21 1.8-V FM data bus
L12 AJ21 1.8-V FM data bus
M16 AJ20 1.8-V FM data bus
L13 AL21 1.8-V FM data bus
M15 AL20 1.8-V FM data bus
L14 AN25 1.8-V FM data bus
N16 AM25 1.8-V FM data bus
M13 AP24 1.8-V FM data bus
N15 AN24 1.8-V FM data bus
N14 AC24 1.8-V FM data bus
P15 AB24 1.8-V FM data bus
P14 AF25 1.8-V FM data bus
D13 AE25 1.8-V FM data bus
D14 AE24 1.8-V FM data bus
F11 AD24 1.8-V FM data bus
J16 AG24 1.8-V FM data bus
F12 AH24 1.8-V FM data bus
K12 AK24 1.8-V FM data bus
M14 AJ24 1.8-V FM data bus
N13 AL24 1.8-V FM data bus
R1 AL25 1.8-V FM data bus
P4 AW25 1.8-V FM data bus
N5 AV25 1.8-V FM data bus
P6 AT24 1.8-V FM data bus
K1 AH6 2.5-V FPGA configuration done
D3 AP33 2.5-V FPGA configuration data
C2 AT33 2.5-V FPGA configuration data
C3 AR33 2.5-V FPGA configuration data
E3 AU34 2.5-V FPGA configuration data
D2 AU33 2.5-V FPGA configuration data
E4 AN31 2.5-V FPGA configuration data
D1 AM31 2.5-V FPGA configuration data
E5 AU32 2.5-V FPGA configuration data
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–10 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 4 of 6)
Schematic Signal Name
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
FPGA_CONFIG_D16
FPGA_CONFIG_D17
FPGA_CONFIG_D18
FPGA_CONFIG_D19
FPGA_CONFIG_D20
FPGA_CONFIG_D21
FPGA_CONFIG_D22
FPGA_CONFIG_D23
FPGA_CONFIG_D24
FPGA_CONFIG_D25
FPGA_CONFIG_D26
FPGA_CONFIG_D27
FPGA_CONFIG_D28
FPGA_CONFIG_D29
FPGA_CONFIG_D30
FPGA_CONFIG_D31
FPGA_CVP_CONFDONE
FPGA_DCLK
FPGA_nCONFIG
FPGA_nSTATUS
FPGA_PR_DONE
FPGA_PR_ERROR
FPGA_PR_READY
FPGA_PR_REQUEST
HSMA_PRSNTn
HSMB_PRSNTn
M570_CLOCK
M570_PCIE_JTAG_EN
MAX5_BEN0
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
Description
F3 AT32 2.5-V FPGA configuration data
E1 AR31 2.5-V FPGA configuration data
F4 AP31 2.5-V FPGA configuration data
F2 AW34 2.5-V FPGA configuration data
F1 AV34 2.5-V FPGA configuration data
F6 AW31 2.5-V FPGA configuration data
G2 AV31 2.5-V FPGA configuration data
G3 AW32 2.5-V FPGA configuration data
G1 AV32 2.5-V FPGA configuration data
G4 AJ33 2.5-V FPGA configuration data
H2 AH33 2.5-V FPGA configuration data
G5 AL33 2.5-V FPGA configuration data
H3 AK33 2.5-V FPGA configuration data
J1 AK32 2.5-V FPGA configuration data
J2 AJ32 2.5-V FPGA configuration data
H5 AH31 2.5-V FPGA configuration data
K2 AG31 2.5-V FPGA configuration data
K5 AF31 2.5-V FPGA configuration data
L1 AE31 2.5-V FPGA configuration data
L2 AJ30 2.5-V FPGA configuration data
K3 AH30 2.5-V FPGA configuration data
M2 AR30 2.5-V FPGA configuration data
L4 AP30 2.5-V FPGA configuration data
L3 AU30 2.5-V FPGA configuration data
N3 AT29 2.5-V FPGA configuration via protocol done
J3 AC31 2.5-V FPGA configuration clock
N1 AK35 2.5-V FPGA configuration active
J4 AM5 2.5-V FPGA configuration ready status
H1 AT30 2.5-V FPGA partial reconfiguration done
P2 AU29 2.5-V FPGA partial reconfiguration error
E2 AN29 2.5-V FPGA partial reconfiguration ready
F5 AN30 2.5-V FPGA partial reconfiguration request
B8 AW8 2.5-V HSMC port A present
A8 AU7 2.5-V HSMC port B present
P11 — 1.8-V
P12 — 1.8-V
25-MHz clock to on-board USB-Blaster for
sending FACTORY command
A low signal disables the on-board
USB-Blaster when PCIe masters the JTAG
P10 U31 1.8-V MAX V byte enable 0
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–11
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 5 of 6)
Schematic Signal Name
MAX5_BEN1
MAX5_BEN2
MAX5_BEN3
MAX5_CLK
MAX5_CSN
MAX5_OEN
MAX5_WEN
MAX_CONF_DONE
MAX_ERROR
MAX_LOAD
MAX_RESETn
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
OVERTEMP
OVERTEMPn
PCIE_JTAG_EN
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
PGM_SEL
SDI_RX_BYPASS
SDI_RX_EN
SDI_TX_EN
SECURITY_MODE
SENSE_CS0n
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_SMB_CLK
SENSE_SMB_DATA
SI570_EN
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
Description
R11 T31 1.8-V MAX V byte enable 1
T12 N33 1.8-V MAX V byte enable 2
N11 M33 1.8-V MAX V byte enable 3
T11 E34 1.8-V MAX V clock
R10 B32 1.8-V MAX V chip select
M10 A32 1.8-V MAX V output enable
N10 A34 1.8-V MAX V write enable
E11 — 1.8-V FPGA configuration done LED
A4 — 1.8-V FPGA configuration error LED
A6 — 1.8-V FPGA configuration active LED
M9 — 1.8-V MAX V reset push button
B10 AA9 2.5-V DIP - FPGA mode select 0
B3 AA10 2.5-V DIP - FPGA mode select 1
C10 AD8 2.5-V DIP - FPGA mode select 2
C12 AG8 2.5-V DIP - FPGA mode select 3
C6 AH7 2.5-V DIP - FPGA mode select 4
B7 — 2.5-V Temperature monitor fan enable
C8 — 2.5-V
Temperature monitor over-temperature
indicator LED
C7 — 2.5-V DIP switch to enable the PCIe JTAG master
D12 — 2.5-V
Loads the flash memory image identified by
the PGM LEDs
B14 — 2.5-V Flash memory PGM select indicator 0
C13 — 2.5-V Flash memory PGM select indicator 1
B16 — 2.5-V Flash memory PGM select indicator 2
B13 — 2.5-V Toggles the
PGM_LED[0:2]
sequence
D5 AB30 2.5-V SDI equalization bypass
E8 AB28 2.5-V SDI receive enable
D11 AK27 2.5-V SDI transmit enable
R12 — 1.8-V
DIP - On-board USB-Blaster II send
FACTORY command at power up.
E7 — 2.5-V Power monitor chip select
A5 — 2.5-V Power monitor SPI clock
D7 — 2.5-V Power monitor SPI data in
B6 — 2.5-V Power monitor SPI data out
D8 — 2.5-V Temperature monitor SMB clock
A7 — 2.5-V Temperature monitor SMB data
A10 — 2.5-V Si570 programmable oscillator enable
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 6 of 6)
Schematic Signal Name
SI571_EN
TSENSE_ALERTn
MAX V CPLD
Pin Number
D4 — 2.5-V Si571 programmable VCXO enable
B5 — 2.5-V Temperature monitor alert
Stratix V GS
Pin Number
I/O
Standard
Description
Tab le 2– 6 lists the MAX V CPLD System Controller component reference and
manufacturing information.
Table 2–6. MAX V CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U4
MAX V CPLD 2210 LE
256FBGA LF 1.8V VCCINT
Altera
Corporation 5M2210ZF256C4N www.altera.com
Manufacturing
Part Number
Manufacturer
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX V CPLD System Controller
device programming methods that the DSP Development Kit, Stratix V Edition
supports.
Website
The development board supports three configuration methods:
■ On-Board USB-Blaster II is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied
micro-USB cable.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program load push button (S2).
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
FPGA Programming over On-Board USB-Blaster II
The on-board USB-Blaster II is implemented using a micro-USB type-B connector (J7),
a USB 2.0 PHY device, and an Altera MAX II CPLD EPM570GM100 (U14). This allows
the configuration of the FPGA using a USB cable which connects directly between the
USB port on the board (J7) and a USB port on a PC running the Quartus II software.
The on-board USB-Blaster II normally masters the JTAG chain.
f For more information about the on-board USB-Blaster II, refer to the on-board
USB-Blaster II page of the Altera Wiki website.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
MAX II CPLD EPM570GM100
The MAX II CPLD is dedicated to the on-board USB-Blaster II functionality. The
CPLD connects to the CY7C68013A USB 2.0 PHY device on one side and drives the
JTAG and System Console direct USB signals out the other side through the general
purpose I/O (GPIO) pins.
Tab le 2– 7 lists the I/O signals present on the MAX II CPLD EPM570GM100.
Table 2–7. MAX II CPLD EPM570GM100 On-Board USB-Blaster II I/O Signals
Schematic Signal Name Type Description
SC_RX
SC_TX
JTAG_RX
JTAG_TX
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
USB_CLK
USB_OEn
USB_RESETn
USB_DATA(7:0)
USB_RDn
USB_WRn
USB_EMPTY
USB_FULL
USB_ADDR(1:0)
USB_SCL
USB_SDA
FACTORY_REQUEST
FACTORY_STATUS
M570_CLOCK
1.5-V CMOS output USB system console receive LED
1.5-V CMOS output USB system console transmit LED
1.5-V CMOS output USB-Blaster II JTAG receive LED
1.5-V CMOS output USB-Blaster II JTAG transmit LED
2.5-V CMOS output GPIO for on-board JTAG chain clock
2.5-V CMOS output GPIO for on-board JTAG chain mode
2.5-V CMOS output GPIO for on-board JTAG chain data in
2.5-V CMOS input GPIO for on-board JTAG chain data out
1.5-V CMOS input USB System Console clock
1.5-V CMOS input USB System Console FPGA output enable
1.5-V CMOS input USB System Console reset
1.5-V CMOS inout (8 bits) USB System Console FIFO data bus
1.5-V CMOS input USB System Console read from FIFO
1.5-V CMOS input USB System Console write to FIFO
1.5-V CMOS output USB System Console FIFO empty
1.5-V CMOS output USB System Console FIFO full
1.5-V CMOS input/output USB System Console address bus
1.5-V CMOS input/output USB System Console configuration clock
1.5-V CMOS input/output USB System Console configuration data
1.5-V CMOS input Send FACTORY command
1.5-V CMOS output FACTORY command status
1.5-V CMOS input 25-MHz input clock for FACTORY command
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–14 Chapter 2: Board Components
Cypress
On-Board
USB-Blaster II
GPIO
TCK
Stratix V GS
FPGA
Analog
Switch
MAX V
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
ENABLE
ENABLE
ENABLE
ENABLE
JTAG Slave
JTAG Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
2.5 V
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
ALWAYS
ENABLED
(in chain)
DIP Switch
DIP Switch
DIP Switch
DIP Switch
10-pin
JTAG Header
Flash
Memory
PCI Express
Edge
Connector
JTAG Master
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Level
Translator
2.5 V
2.5 V
Configuration, Status, and Setup Elements
JTAG Chain
The on-board USB-Blaster II is automatically disabled when you connect an external
USB-Blaster to the JTAG chain or when you enable JTAG from the PCI Express edge
connector. Figure 2–3 illustrates the JTAG chain.
Figure 2–3. JTAG Chain
Each jumper shown in Figure 2–3 is located in the JTAG DIP switch (SW3) on the back
of the board. To connect a device or interface in the chain, their corresponding switch
must be in the OFF position. Push all the switches in the ON position to only have the
FPGA in the chain. Note that the MAX V CPLD System Controller must be in the
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
chain to use some of the GUI interfaces.
Chapter 2: Board Components 2–15
Configuration, Status, and Setup Elements
1 By default, the on-board USB-Blaster II clocks
TCK
at 24 MHz. For the on-board
USB-Blaster II to function correctly, you must set the Quartus II clock constraint on the
internal_tck
input signal to 24 MHz.
System Console USB Interface
The System Console USB interface is a fast parallel interface. Together with the soft
logic supplied by Altera, this interface provides a system console master for debug
access.
The system console controls the debug master via signals shown in Tab le 2–8 to give
fast access to an Avalon
®
Memory-Mapped (Avalon-MM) master bus that the Qsys
system integration tool generates.
f For more information about the system console, refer to the Analyzing and Debugging
Designs with the System Console chapter in volume 3 of the Quartus II Handbook.
Tab le 2– 8 lists the System Console USB interface pin connections relative to the FPGA.
Table 2–8. System Console USB Interface Pin Connections
Stratix V GS Device Pin Number Schematic Signal Name Direction Note
AV28
H34
G32, G33, F32, E32, A37, A36, C34, A35
N34
P34
J33
K33
E33
G34, K34
J34
F33
usb_clk
usb_reset_n
usb_data[7:0]
usb_full
usb_empty
usb_wr_n
usb_rd_n
usb_oe_n
usb_addr
usb_scl
usb_sda
input 48 MHz
input —
bidirectional G32(MSB), A35 (LSB)
output —
output —
input —
input —
input —
bidirectional Reserved
bidirectional —
bidirectional —
Flash Programming
Flash programming is possible through a variety of methods using the Stratix V GS
device.
The first method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware (page 1) of the flash over the network.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–16 Chapter 2: Board Components
Configuration, Status, and Setup Elements
The secondary method is to use the pre-built PFL design included in the development
kit. The development board implements the Altera PFL megafunction for flash
programming. The PFL megafunction is a block of logic that is programmed into an
Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for
writing to a compatible flash device. This pre-built design contains the PFL
megafunction that allows you to write either page 0, page 1, or other areas of flash
over the USB interface using the Quartus II software. Use this method to restore the
development board to its factory default settings.
Other methods to program the flash can be used as well, including the Nios II
processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the program load push button (S2), the MAX V
CPLD System Controller’s parallel flash loader configures the FPGA from the flash
memory. The system controller uses the Altera Parallel Flash Loader (PFL)
megafunction which reads 32-bit data from the flash memory and converts it to fast
passive parallel (FPP) format. This 32-bit data is then written to the dedicated
configuration pins in the FPGA during configuration.
After a power-up or reset event, the MAX V CPLD (U4) automatically configures the
FPGA in FPP mode with either the pre-installed factory .pof file or a user .pof file
depending on the setting of the
PGM_SEL
push-button (S3). There are three pages
reserved for the FPGA configuration data—factory hardware (page 0), user
hardware 1 (page 1), and user hardware 2 (page 2). There are three green
configuration status LEDs,
PGM_LED[0:2]
(D4, D5, D6), which indicates the status of
the FPP configuration. Tab le 2 –9 lists the configuration status LEDs settings.
Table 2–9. Configuration LED settings
LED
PGM_LED0 PGM_LED1 PGM_LED2
v — — Factory
— v — User hardware 1
——v User hardware 2
Note to Tab le 2– 9:
(1) A checkmark (v) indicates that the LED is ON (logic 0) while a dash (—) indicates that the LED is OFF (logic 1).
(1)
Design
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–17
MAX V CPLD
System Controller
FPGA_DATA [0]
FPGA_DCLK
FLASH_A [25:1]
FLASH_D [31:0]
DATA [0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
2.5 V
10 kΩ
nCE
CFI Flash
CONF_DONE LED
1 kΩ
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [25:0]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_ADVn
FLASH_ADVn
FPGA_nCONFIG
FPGA_CONF_DONE
FM Bus Interface
FLASH_RYBSYn
FPGA_nSTATUS
ERROR
LOAD
FACTORY
USB-BLASTER
1.8 V
10 kΩ
2.5 V
FLASH_RYBSYn
PGM_SEL
CONF_DONE
2.5 V
10 kΩ
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RESETn
50 MHz
100 MHz
PGM_CONFIG
MAX_RESETn
56.2 Ω
2.5 V
1 kΩ
MSEL4
MSEL[4:0] also
connects to MAX V
FPGA_INIT_DONE
2.5 V
56.2 Ω
CLK_SEL
CLK_ENABLE
USER_PGM
USB_SELECT
DIP Switch
PGM_LED0
PGM_LED1
PGM_LED2
2.5 V
56.2 Ω
CFI Flash
FLASH_A [25:0]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_ADVn
FLASH_RYBSYn
FLASH_CLK
FLASH_RESETn
10 kΩ
Configuration, Status, and Setup Elements
Figure 2–4 shows the PFL configuration.
Figure 2–4. PFL Configuration
f For more information on the flash memory map storage, refer to the DSP Development
Kit, Stratix V Edition User Guide.
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U15) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster connects to the board through the JTAG header
(J10).
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–18 Chapter 2: Board Components
Configuration, Status, and Setup Elements
f For more information on the following topics, refer to the respective documents:
■ Board Update Portal and PFL Design, refer to the DSP Development Kit, Stratix V
Edition User Guide.
■ PFL megafunction, refer to AN 386: Using the Parallel Flash Loader with the Quartus
II Software.
Status Elements
The development board includes board-specific status LEDs and switches for
enabling and configuring various features on the board, as well as a 16 character × 2
line LCD for displaying board power and temperature measurements. This section
describes these status elements.
Status LEDs
Surface mount LEDs indicate the various status of the board. A logic 0 is driven on the
I/O port to turn the LED on while a logic 1 is driven to turn the LED off.
Tab le 2– 10 lists the LED board references, names, and functional descriptions.
Table 2–10. Board-Specific LEDs (Part 1 of 2)
Board
Reference
D24 POWER — Blue LED. Illuminates when 5.0-V power is active.
D15 LOAD
D16 ERR
D17 CONF DN
D29 TX
D30 RX
D31 100
D32 1000
D1
D2
LED Name
HSMC Port A
Present
HSMC Port B
Present
Schematic Signal
Name
MAX_LOAD
MAX_ERROR
MAX_CONF_DONE
ENET_LED_TX
ENET_LED_RX
ENET_LED_LINK100
ENET_LED_LINK1000
HSMA_PRSNTN
HSMB_PRSNTN
Description
Green LED. Illuminates when the MAX V CPLD System Controller
is actively configuring the FPGA. Driven by the MAX V CPLD
System Controller.
Red LED. Illuminates when the MAX V CPLD System Controller
fails to configure the FPGA. Driven by the MAX V CPLD System
Controller.
Green LED. Illuminates when the FPGA is successfully
configured. Driven by the MAX V CPLD System Controller.
Green LED. Blinks to indicate Ethernet PHY transmit activity.
Driven by the Marvell 88E1111 PHY.
Green LED. Blinks to indicate Ethernet PHY receive activity.
Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 100 Mbps
connection speed Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps
connection speed. Driven by the Marvell 88E1111 PHY.
Green LED. Illuminates when the HSMC port A has a board or
cable plugged-in such that pin 160 becomes grounded. Driven
by the add-in card.
Green LED. Illuminates when the HSMC port B has a board or
cable plugged-in such that pin 160 becomes grounded. Driven
by the add-in card.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–19
Configuration, Status, and Setup Elements
Table 2–10. Board-Specific LEDs (Part 2 of 2)
Board
Reference
LED Name
D4, D5, D6 PGM_LED
D12 TEMP
Schematic Signal
Name
PGM_LED0
PGM_LED1
PGM_LED2
OVERTEMPn
Description
The sequence displayed determines if the factory design or a
user design is used to configure the FPGA from flash when you
press the PGM_LOAD push button. Refer to Table 2–9 for the
push button configuration settings.
Red LED. Illuminates when a heat sink or fan should be installed.
Driven by the MAX1619 thermal sensor
Tab le 2– 11 lists the board-specific LEDs component references and manufacturing
information.
Table 2–11. Board-Specific LEDs Component References and Manufacturing Information
Board Reference Description Manufacturer
D1, D2, D4-D6, D15,
D17, D29-D32
Green LEDs Lumex Inc. SML-LX1206GC-TR www.lumex.com
Manufacturer
Part Number
D16 Red LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com
D24 Blue LED Lumex Inc. SML-LX1206USBC-TR www.lumex.com
Setup Elements
The development board includes several different kinds of setup elements. This
section describes the following setup elements:
OVERTEMPn
Manufacturer
Website
signal.
■ Board settings DIP switch
■ JTAG control DIP switch
■ PCI Express control DIP switch
■ MAX V reset push button
■ Program load push button
■ Program select push button
■ CPU reset push button
Board Settings DIP Switch
The board settings DIP switch (SW5) controls various features specific to the board
and the MAX V CPLD System Controller logic design. Table 2–12 lists the switch
controls and descriptions.
Table 2–12. Board Settings DIP Switch Controls (Part 1 of 2)
Switch Schematic Signal Name Description Default
1
2
CLK_SEL
CLK_ENABLE
ON : SMA input clock select.
OFF : Programmable oscillator input clock select (default 100 MHz).
ON : On-Board oscillator enabled.
OFF : On-Board oscillator disabled.
OFF
ON
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–20 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Table 2–12. Board Settings DIP Switch Controls (Part 2 of 2)
Switch Schematic Signal Name Description Default
3
FACTORY_LOAD
4
SECURITY_MODE
ON : Load user 1 design from flash at power up.
OFF : Load factory design from flash at power up.
ON : Do not send FACTORY command at power-up.
OFF : Send FACTORY command at power-up.
OFF
ON
Tab le 2– 13 lists the board settings DIP switch component reference and
manufacturing information.
Table 2–13. Board Settings DIP Switch Component Reference and Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
SW5 Four-Position slide DIP switch C & K Components TDA04H0SB1 www.ck-components.com
JTAG Control DIP Switch
The JTAG control DIP switch (SW3) provides you an option to either remove or
include devices in the active JTAG chain. However, the Stratix V GS device is always
in the JTAG chain. Table 2–14 shows the switch controls and its descriptions.
Table 2–14. JTAG Control DIP Switch Controls
Switch Schematic Signal Name Description Default
5M2210_JTAG_EN
1
2
HSMA_JTAG_EN
3
HSMB_JTAG_EN
4
PCIE_JTAG_EN
ON : Bypass MAX V CPLD System Controller.
OFF : MAX V CPLD System Controller in-chain.
ON : Bypass HSMC port A.
OFF : HSMC port A in-chain.
ON : Bypass HSMC port B.
OFF : HSMC port B in-chain.
ON : On-Board USB-Blaster II or external USB-Blaster is the chain
master.
OFF : PCI Express edge connector is the chain master.
OFF
ON
ON
ON
Tab le 2– 15 lists the JTAG control DIP switch component references and
manufacturing information.
Table 2–15. JTAG Control DIP Switch Component Reference and Manufacturing Information
Board
Reference
Device Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
SW3 Four-Position slide DIP switch C & K Components TDA04H0SB1 www.ck-components.com
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–21
Configuration, Status, and Setup Elements
PCI Express Control DIP Switch
The PCI Express control DIP switch (SW6) can enable or disable different
configurations. Table 2–16 shows the switch controls and descriptions.
Table 2–16. PCI Express Control DIP Switch Controls
Switch Schematic Signal Name Description Default
PCIE_PRSNT2n_x1
1
2
PCIE_PRSNT2n_x4
3
PCIE_PRSNT2n_x8
4 — Unused —
ON : Enable x1 presence detect
OFF : Disable x1 presence detect
ON : Enable x4 presence detect
OFF : Disable x4 presence detect
ON : Enable x8 presence detect
OFF : Disable x8 presence detect
Tab le 2– 17 lists the PCI Express control DIP switch component reference and
manufacturing information.
Table 2–17. PCI Express Control DIP Switch Component Reference and Manufacturing Information
ON
ON
ON
Board
Reference
SW6 Four-Position slide DIP switch C & K Components TDA04H0SB1 www.ck-components.com
Device Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
MAX V Reset Push Button
The MAX V reset push button,
Controller. This push button is the default logic reset for the CPLD logic.
Tab le 2– 19 lists the MAX V reset push button component reference and
manufacturing information.
Table 2–18. MAX V Reset Push Button Component Reference and Manufacturing Information
Board
Reference
S1 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw
Description Manufacturer
MAX_RESETn
, is an input to the MAX V CPLD System
Manufacturer
Part Number
Manufacturer Website
Program Load Push Button
The program load push button,
Controller. The push button forces a reconfiguration of the FPGA from flash memory.
The location in the flash memory is based on the settings of the
controlled by the program select push button,
Tab le 2– 19 lists the program load push button component reference and
manufacturing information.
PGM_CONFIG
, is an input to the MAX V CPLD System
PGM_LED[2:0]
PGM_SEL
.
which is
Table 2–19. Program Load Push Button Component Reference and Manufacturing Information
Board
Reference
S2 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
Reference Manual
2–22 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Program Select Push Button
The program select push button,
Controller. The push button toggles the
location in the flash memory is used to configure the FPGA. Refer to Tabl e 2– 9 for the
configuration settings.
Tab le 2– 20 lists the program select push button component reference and
manufacturing information.
Table 2–20. Program Select Push Button Component Reference and Manufacturing Information
PGM_SEL
PGM_LED[2:0]
, is an input to the MAX V CPLD System
setting that selects which
Board
Reference
S3 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw
Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
CPU Reset Push Button
The CPU reset push button,
and is an open-drain I/O from the MAX V CPLD System Controller. This push button
is the default logic reset for the FPGA logic. The MAX V System Controller also
drives this push button during POR.
You must enable the
CPU_RESETn
function to work. Otherwise, the
enable the signal in the Quartus II software, and then pulled high on the board, this
push button resets every register within the FPGA with a low signal.
Tab le 2– 21 lists the CPU reset push button component reference and manufacturing
information.
Table 2–21. CPU Reset Configuration Push Button Component Reference and Manufacturing Information
Board
Reference
S4 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw
Description Manufacturer
CPU_RESETn
, is an input to the Stratix V GS
signal within the Quartus II software for this reset
CPU_RESETn
acts as a regular I/O pin. When you
Manufacturer
Part Number
Manufacturer Website
DEV_CLRn
pin
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–23
SMA
REFCLK INPUT
SMA
Buffer
(100 MHz
Default)
Si570
(100 MHz
Default)
Si5388
156.25 MHz
625 MHz
270 MHz
100 MHz
REFCLK4_QR2_P/N
REFCLK5_QR2_P/N (HSMB)
REFCLK2_QR1_P/N (HSMB)
REFCLK1_QR0_P/N (HSMA)
REFCLK0_QR0_P/N (HSMA)
644.53125 MHz
282.5 MHz
125 MHz
125 MHz
125 MHz
100 MHz
100 MHz
100 MHz
100 MHz
CLK4
CLK0
CLK6
CLK22
CLK16
CLK9
REFCLK5_QL2_P/N (148.5 MHz)
SDI (148.5 M / 148.35 M)
REFCLK4_QL2_P/N (QSFP)
REFCLK2_QL1_P (QSFP)
REFCLK1_QL0_P/N
PCIE_REF_CLK_P/N
CLKINTOP_P/N[1]
CLKINTOP_P/N[0]
CLKIN_50
CLKINBOT_P/N[0]
CLK_125_P/N
CLKINBOT_P/N[1]
Si5388
CLK3
CLK2
CLK1
CLK0
Si571
148.5 MHz
Default
B8
QL2
QL1
QL0
B3
B4
B7
QR2
QR1
QR0
CLK3
CLK2
CLK1
CLK0
50 M
125 M
Clock Circuitry
Clock Circuitry
This section describes the board's clock inputs and outputs.
On-Board Oscillators
The development board includes a 50-MHz, 100-MHz, 125-MHz, and 156.25-MHz
programmable oscillators. Figure 2–5 shows the default frequencies of all external
clocks going to the development board.
Figure 2–5. DSP Development Kit, Stratix V Edition External Clock Inputs and Default Frequencies
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–24 Chapter 2: Board Components
Clock Circuitry
Tab le 2– 22 lists the oscillators, its I/O standard, and voltages required for the
development board.
Table 2–22. On-Board Oscillators
Source
X3
X2
X4
X1
X6
U46
U38
Schematic Signal
Name
CLKIN_50
CLLK_CONFIG
REFCLK1_QL0_P
REFCLK1_QL0_N
CLKINBOT_P0
CLKINBOT_N0
CLKINTOP_P0
CLKINTOP_N0
REFCLK4_QR2_P
REFCLK4_QR2_N
CLK_125_P
CLK_125_N
REFCLK5_QL2_P
REFCLK5_QL2_N
CLKINTOP_P1
CLKINTOP_N1
REFCLK4_QL2_P
REFCLK4_QL2_N
REFCLK2_QL1_P
REFCLK2_QL1_N
CLKINBOT_P1
CLKINBOT_N1
REFCLK5_QR2_P
REFCLK5_QR2_N
REFCLK2_QR1_P
REFCLK2_QR1_N
REFCLK1_QR0_P
REFCLK1_QR0_N
REFCLK0_QR0_P
REFCLK0_QR0_N
Stratix V GS
Frequency I/O Standard
Device Pin
Application
Number
50.000 MHz 2.5V CMOS AN6 Nios II and MAX V
100.000 MHz 2.5V CMOS — Fast FPGA configuration
100.000 MHz
125.000 MHz
148.500 MHz
125.000 MHz
282.500 MHz
644.53125 MHz
125.000 MHz
270.000 MHz
625.000 MHz
156.250 MHz
100.000 MHz
LVDS
(fanout buffer)
LVDS AV 29
LVDS A W29
LVDS T33
LVDS T34
LVDS N32
LVDS M3 2
LVDS V3 4
LVDS V3 5
LVDS AB34
LVDS AB35
LVDS A F17
LVDS A G1 7
LVDS T7
LVDS T6
LVDS AB6
LVDS AB5
LVDS A D7
LVDS A D6
LVDS AF6
LVDS AF5
AD33
AD34
AH22
AJ22
J23
J24
V6
V5
PCI Express host/dual-XTL
Bottom edge
Top edge—DDR3
HSMC port B
10/100/1000 Ethernet
HD-SDI video
Top edge
QSFP
Bottom edge—memory
HSMC port B
XAUI, 10GbE, HSMC port A
HSMC port A
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–25
Clock Circuitry
Off-Board Clock Input/Output
The development board has input and output clocks which can be driven onto the
board. The output clocks can be programmed to different levels and I/O standards
according to the FPGA device’s specification.
Tab le 2– 23 lists the clock inputs for the development board.
Table 2–23. Off-Board Clock Inputs
Source
SMA
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
PCI Express
Edge
Schematic Signal
Name
CLKIN_SMA_P
CLKIN_SMA_N
HSMA_CLK_IN0
HSMA_CLK_IN_P1
HSMA_CLK_IN_N1
HSMA_CLK_IN_P2
HSMA_CLK_IN_N2
HSMB_CLK_IN0
HSMB_CLK_IN_P1
HSMB_CLK_IN_N1
HSMB_CLK_IN_P2
HSMB_CLK_IN_N2
PCIE_REFCLK_P
PCIE_REFCLK_N
I/O Standard
LVPECL —
LVPECL —
2.5-V AG28
LVDS/2.5-V AR8
LVDS/LVTTL AT8
LVDS/LVTTL G7
LVDS/LVTTL G6
2.5-V AF29
LVDS/LVTTL U15
LVDS/LVTTL T16
LVDS/LVTTL P16
LVDS/LVTTL N16
LVDS/LVTTL AF34
HCSL AF35
Stratix V GS
Device Pin
Number
Input to LVDS fan-out buffer (drives one REFCLK)
Single-ended input from the installed HSMC cable
or board.
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
Single-ended input from the installed HSMC cable
or board.
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
LVDS input from the PCI Express edge connector.
Tab le 2– 24 lists the clock outputs for the development board.
Description
Table 2–24. Off-Board Clock Outputs
Source
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
Samtec HSMC
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Schematic Signal
Name
HSMA_CLK_OUT0
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_N1
HSMA_CLK_OUT_P2
HSMA_CLK_OUT_N2
HSMB_CLK_OUT0
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_N1
HSMB_CLK_OUT_P2
HSMB_CLK_OUT_N2
I/O Standard
2.5V CMOS AJ10 FPGA CMOS output (or GPIO)
LVDS/2.5V CMOS AG9
LVDS/2.5V CMOS AH9
LVDS/2.5V CMOS G9
LVDS/2.5V CMOS G8
2.5V CMOS L16 FPGA CMOS output (or GPIO)
LVDS/2.5V CMOS D16
LVDS/2.5V CMOS C16
LVDS/2.5V CMOS B16
LVDS/2.5V CMOS A16
Stratix V GS
Device Pin
Number
Description
LVDS output. Can also support 2x CMOS
outputs.
LVDS output. Can also support 2x CMOS
outputs.
LVDS output. Can also support 2x CMOS
outputs.
LVDS output. Can also support 2x CMOS
outputs.
Reference Manual
2–26 Chapter 2: Board Components
General User Input/Output
Memory Clocks
The development board includes memory clocks which are driven to or received from
the on-board memory devices. For more information on the memory clock signals,
refer to the section on “Memory” on page 2–46.
Tab le 2– 25 lists the crystal oscillators component references and manufacturing
information.
Table 2–25. Crystal Oscillator Component References and Manufacturing Information
Board
Reference
X1
X2 100 MHz 2.5-V CMOS oscillator ECS, Inc. ECS-3525-1000-B-TR www.ecsxtal.com
X3 50 MHz 1.8-V oscillator ECS, Inc. ECS-3518-500-B-xx www.ecsxtal.com
X4
X6 125 MHz LVDS saw oscillator Silicon Labs 571FDB000159DG www.silabs.com
U38
U46
148.50 MHz LVDS voltage
controlled crystal oscillator
100.00 MHz LVDS
programmable crystal oscillator
Programmable LVDS
quad-clock 100M, 156.25M,
625M, 270M defaults
Programmable LVDS
quad-clock 125M, 644.53125M,
282.5M, 125M defaults
Description Manufacturer
Epson
Silicon Labs 570FAB000433DG www.silabs.com
Silicon Labs Si5338A-A01086-GM www.silabs.com
Silicon Labs Si5338A-A01085-GM www.silabs.com
Manufacturer
Part Number
EG-2121CA
125.0000M-LGPNL3
Manufacturer Website
www.eea.epson.com
General User Input/Output
This section describes the user I/O interface to the FPGA. This section describes the
following I/O elements:
■ User-defined push buttons
■ User-defined DIP switch
■ User-defined LEDs
■ Character LCD
User-Defined Push Buttons
The development board includes three user-defined push buttons. Board references
S5, S6, and S7 are push buttons that allow you to interact with the Stratix V GS device.
When you press and hold down the push button, the device pin is set to logic 0; when
you release the push button, the device pin is set to logic 1. There is no board-specific
function for these general user push buttons.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–27
General User Input/Output
Tab le 2– 26 lists the user-defined push button schematic signal names and their
corresponding Stratix V GS device pin numbers.
Table 2–26. User-Defined Push Button Schematic Signal Names and Functions
Board Reference
S5
S6
S7
Schematic Signal
Name
USER_PB2
USER_PB1
USER_PB0
I/O Standard
2.5-V
(Variable S5_VCCIO_HSMB)
Stratix V GS Device
Pin Number
A7
B7
C7
Description
User-Defined push
buttons
Tab le 2– 27 lists the user-defined push button component reference and the
manufacturing information.
Table 2–27. User-Defined Push Button Component Reference and Manufacturing Information
Board Reference Description Manufacturer
S5, S6, S7 Push button Dawning Precision Co., Ltd. TS-A02SA-2-S100 www.dawning2.com.tw
Manufacturer
Part Number
Manufacturer Website
User-Defined DIP Switches
Board reference SW1 is an 8-pin DIP switch. The switches are user-defined, and are
for additional FPGA input control. There is no board-specific function for these
switches.
Tab le 2– 28 lists the user-defined DIP switch schematic signal names and their
corresponding Stratix V GS pin numbers.
Table 2–28. User-Defined DIP Switch Schematic Signal Names and Functions
Board Reference
(SW1)
1
2
3
4
5
6
7
8
Schematic
Signal Name
USER_DIPSW0
USER_DIPSW1
USER_DIPSW2
USER_DIPSW3
USER_DIPSW4
USER_DIPSW5
USER_DIPSW6
USER_DIPSW7
I/O Standard
2.5-V
(Variable S5_VCCIO_HSMB)
Stratix V GS Device
Pin Number
E7
H7
J7
K7
M6
N6
P7
N7
Description
User-Defined DIP switch
connected to FPGA
device. When the switch
is in the CLOSED or ON
position, a logic 0 is
selected. When the
switch is in the OPEN or
OFF position, a logic 1 is
selected.
Tab le 2– 29 lists the user-defined DIP switch component reference and the
manufacturing information.
Table 2–29. User-Defined DIP Switch Component Reference and Manufacturing Information
Board Reference Description Manufacturer
SW1 Eight-Position DIP switch C & K Components TDA08H0SB1 www.ck-components.com
Manufacturer
Part Number
Manufacturer Website
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–28 Chapter 2: Board Components
General User Input/Output
User-Defined LEDs
The development board includes general and HSMC user-defined LEDs. This section
describes all user-defined LEDs. For information on board specific or status LEDs,
refer to“Status Elements” on page 2–18.
General User-Defined LEDs
Board references D7 through D10 and D18 through D21 are eight bi-color user LEDs
which allow status and debugging signals to be driven to the LEDs from the designs
loaded into the Stratix V GS device. These bi-color LEDs are in red and green, which
combines to a total of 16 unique user LEDs. The LEDs illuminate when a logic 0 is
driven, and turns off when a logic 1 is driven. There is no board-specific function for
these LEDs.
Tab le 2– 30 lists the user-defined LED schematic signal names and their corresponding
Stratix V GS pin numbers.
Table 2–30. User-Defined LED Schematic Signal Names and Functions
Board Reference
D21.3
D20.3
D19.3
D18.3
D10.3
D9.3
D8.3
D7.3
D21.4
D20.4
D19.4
D18.4
D10.4
D9.4
D8.4
D7.4
Schematic
Signal Name
USER_LED_G0
USER_LED_G1
USER_LED_G2
USER_LED_G3
USER_LED_G4
USER_LED_G5
USER_LED_G6
USER_LED_G7
USER_LED_R0
USER_LED_R1
USER_LED_R2
USER_LED_R3
USER_LED_R4
USER_LED_R5
USER_LED_R6
USER_LED_R7
I/O Standard
2.5-V J11
2.5-V U10
2.5-V U9
1.8-V AU24
2.5-V AF28
2.5-V AE29
1.8-V AR7
2.5-V AV10
2.5-V AH28
2.5-V AG30
1.8-V AL7
1.8-V AR24
1.8-V AM7
1.8-V AW7
1.8-V AL23
1.8-V AV7
Stratix V GS Device
Pin Number
Description
User-Defined LEDs.
Driving a logic 0 on the I/O
port turns the LED ON. Driving
a logic 1 on the I/O port turns
the LED OFF.
Tab le 2– 31 lists the user-defined LED component reference and the manufacturing
information.
Table 2–31. User-Defined LED Component Reference and Manufacturing Information
Board Reference Device Description Manufacturer
D7-D10, D18-D21
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Bi-color green/red LEDs, 0606,
SMT, Clear Lens, 2.1/2.0 V
Lite-On, Inc. LTST-C195GEKT www.us.liteon.com
Manufacturer
Part Number
Manufacturer
Website
Chapter 2: Board Components 2–29
General User Input/Output
HSMC User-Defined LEDs
The HSMC port A and B have two LEDs located nearby. The LEDs are labeled TX and
RX. The LEDs display data flow to and from the connected HSMC cards. The LEDs
are driven by the Stratix V GS device. There are no board-specific functions for the
HSMC LEDs.
Tab le 2– 32 lists the HSMC user-defined LED schematic signal names and their
corresponding Stratix V GS pin numbers.
Table 2–32. HSMC User-Defined LED Schematic Signal Names and Functions
Board
Reference
D3
D13
D11
D14
Schematic
Signal Name
HSMA_TX_LED
HSMA_RX_LED
HSMB_TX_LED
HSMB_RX_LED
I/O Standard
1.8-V AU8
1.8-V AV8
1.8-V AP6
1.8-V AR6
Stratix V GS Device
Pin Number
Description
User-Defined LEDs.
Labeled TX for HSMC Port A.
User-Defined LEDs.
Labeled RX for HSMC Port A.
User-Defined LEDs.
Labeled TX for HSMC Port B.
User-Defined LEDs.
Labeled RX for HSMC Port B.
Tab le 2– 33 lists the HSMC user-defined LED component reference and the
manufacturing information.
Table 2–33. HSMC User-Defined LED Component Reference and Manufacturing Information
Board Reference Description Manufacturer
D3, D11, D13, D14 Green LEDs, 0805, SMT, 2.0 V Lumex Inc. SML-LXT0805GW-TR www.lumex.com
Manufacturer
Part Number
Manufacturer
Website
Character LCD
The development board contains a single 14-pin 0.1" pitch dual-row header that
interfaces to a 16 character × 2 line Lumex LCD display. The LCD has a 14-pin
receptacle that mounts directly to the board's 14-pin header, so you can easily remove
it to access components under the display. You can also use the header for debugging
or other purposes.
Tab le 2– 34 summarizes the LCD pin assignments. The signal names and directions are
relative to the Stratix V GS.
Table 2–34. LCD Pin Assignments, Schematic Signal Names, and Functions
Board Reference
(J15)
4
5
6
7
8
9
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Schematic Signal
Name
LCD_D_Cn
LCD_WEn
LCD_CSn
LCD_DATA0
LCD_DATA1
LCD_DATA2
I/O Standard
2.5-V AH10 LCD data or command select
2.5-V AW10 LCD write enable
2.5-V AU9 LCD chip select
2.5-V AP10 LCD data bus
2.5-V AN10 LCD data bus
2.5-V AM10 LCD data bus
Stratix V GS Device
Pin Number
Description
Reference Manual
2–30 Chapter 2: Board Components
General User Input/Output
Table 2–34. LCD Pin Assignments, Schematic Signal Names, and Functions
Board Reference
(J15)
10
11
12
13
14
f For more information such as timing, character maps, interface guidelines, and other
Schematic Signal
Name
LCD_DATA3
LCD_DATA4
LCD_DATA5
LCD_DATA6
LCD_DATA7
I/O Standard
2.5-V AL10 LCD data bus
2.5-V AP9 LCD data bus
2.5-V AN9 LCD data bus
2.5-V AT9 LCD data bus
2.5-V AR9 LCD data bus
Stratix V GS Device
Pin Number
Description
Tab le 2– 35 shows the LCD pin definitions, and is an excerpt from the Lumex data
sheet.
related documentation, visit www.lumex.com.
Table 2–35. LCD Pin Definitions and Functions
Pin
Number
1V
2V
3V
Symbol
DD
SS
0
Level
—
—GND (0 V)
Power supply
Function
5 V
— For LCD drive
Register select signal
4RS H/L
H: Data input
L: Instruction input
5R/W H/L
H: Data read (module to MPU)
L: Data write (MPU to module)
6 E H, H to L Enable
7–14 DB0–DB7 H/L Data bus, software selectable 4-bit or 8-bit mode
1 The particular model used does not have a backlight and the LCD drive pin is
connected to 5 V for maximum pixel drive.
Tab le 2– 36 lists the LCD component references and the manufacturing information.
Table 2–36. LCD Component References and Manufacturing Information
Board
Reference
J15
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
2×7 pin, 100 mil, vertical header Samtec SSW-107-01-G-D www.samtec.com
2×16 character display, 5×8 dot matrix Lumex Inc. LCM-S01602DSR/C www.lumex.com
Description Manufacturer
Manufacturer
Part Number
Manufacturer
Website
Chapter 2: Board Components 2–31
Components and Interfaces
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Stratix V GS device. The development board supports the
following communication ports:
■ PCI Express
■ 10/100/1000 Ethernet
■ HSMC
■ SDI Video Output
■ 40G QSFP Module
PCI Express
The DSP Development Kit, Stratix V Edition is designed to fit entirely into a PC
motherboard with a ×8 PCI Express slot that can accommodate a full height short
form factor add-in card. This interface uses the Stratix V GS device's PCI Express hard
IP block, saving logic resources for the user logic application.
f For more information on using the PCI Express hard IP block, refer to the IP Compiler
for PCI Express User Guide.
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 as well as the connection speed of Gen1 at 2.5 Gbps/lane, Gen2 at 5.0 Gbps/lane,
or Gen3 at 8.0 Gbps/lane for a maximum of 64 Gbps full-duplex bandwidth.
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, it is not recommended to power from
both supplies at the same time. Ideal diode power sharing devices have been
designed into this board to prevent damages or back-current from one supply to the
other.
The
PCIE_REFCLK_P/N
signal is a 100-MHz differential input that is driven from the PC
motherboard to the board through the PCI Express edge connector. This signal
connects directly to a Stratix V GS
REFCLK
input pin pair using DC coupling. This
clock is terminated on the motherboard and therefore, no on-board termination is
required. This clock can have spread-spectrum properties that change its period
between 9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic
(HCSL).
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–32 Chapter 2: Board Components
V
MAX
= 1.15 V
V
CROSS MAX
= 550 mV
V
CROSS MIN
= 250 mV
V
MIN
= –0.30 V
REFCLK –
REFCLK +
Components and Interfaces
Figure 2–6 shows the PCI Express reference clock levels.
Figure 2–6. PCI Express Reference Clock Levels
The SMB and JTAG are optional signals in the PCI Express specification. The SMB
signals are wired to the Stratix V GS device and the JTAG signals control the JTAG
chain if enabled by the JTAG control DIP switch (SW3.4). The PCI Express control DIP
switch allows the presence detect grounding to be altered to enable a ×1, ×4, or ×8
width edge connector. The PCI Express control DIP switch does not support autonegotiation.
The PCI Express edge connector also has a presence detect feature to allow the
motherboard to determine if a card is installed. A jumper is provided to optionally
connect
PRSNT1n
to any of the 3
PRSNT2n
pins found within the x8 connector definition.
This is to address issues on some PC systems that would base the link-width
capability on the presence detect pins versus a query operation.
Tab le 2– 37 summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Stratix V GS.
Table 2–37. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference
(J18)
B14
B15
B19
B20
B23
B24
B27
B28
B33
B34
B37
B38
B41
B42
B45
B46
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Schematic Signal
Name
PCIE_RX_P0
PCIE_RX_N0
PCIE_RX_P1
PCIE_RX_N1
PCIE_RX_P2
PCIE_RX_N2
PCIE_RX_P3
PCIE_RX_N3
PCIE_RX_P4
PCIE_RX_N4
PCIE_RX_P5
PCIE_RX_N5
PCIE_RX_P6
PCIE_RX_N6
PCIE_RX_P7
PCIE_RX_N7
I/O Standard
Stratix V GS Device
Pin Number
1.4-V PCML AV38 Receive bus
1.4-V PCML AV39 Receive bus
1.4-V PCML AT38 Receive bus
1.4-V PCML AT39 Receive bus
1.4-V PCML AP38 Receive bus
1.4-V PCML AP39 Receive bus
1.4-V PCML AM38 Receive bus
1.4-V PCML AM39 Receive bus
1.4-V PCML AH38 Receive bus
1.4-V PCML AH39 Receive bus
1.4-V PCML AF38 Receive bus
1.4-V PCML AF39 Receive bus
1.4-V PCML AD38 Receive bus
1.4-V PCML AD39 Receive bus
1.4-V PCML AB38 Receive bus
1.4-V PCML AB39 Receive bus
Description
Chapter 2: Board Components 2–33
Components and Interfaces
Table 2–37. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference
(J18)
A16
A17
A21
A22
A25
A26
A29
A30
A35
A36
A39
A40
A43
A44
A47
A48
A5
A6
A7
A8
A1
B17
B31
B48
A14
A13
B5
B6
B11
A11
Schematic Signal
Name
PCIE_TX_P0
PCIE_TX_N0
PCIE_TX_P1
PCIE_TX_N1
PCIE_TX_P2
PCIE_TX_N2
PCIE_TX_P3
PCIE_TX_N3
PCIE_TX_P4
PCIE_TX_N4
PCIE_TX_P5
PCIE_TX_N5
PCIE_TX_P6
PCIE_TX_N6
PCIE_TX_P7
PCIE_TX_N7
PCIE_JTAG_TCK
PCIE_JTAG_TDI
PCIE_JTAG_TDO
PCIE_JTAG_TMS
PCIE_PRSNT1N
PCIE_PRSNT2N_X1
PCIE_PRSNT2N_X4
PCIE_PRSNT2N_X8
PCIE_REFCLK_N
PCIE_REFCLK_P
PCIE_SMBCLK
PCIE_SMBDAT
PCIE_WAKEN_R
PCIE_PERSTN
I/O Standard
Stratix V GS Device
Pin Number
Description
1.4-V PCML AU36 Transmit bus
1.4-V PCML AU37 Transmit bus
1.4-V PCML AR36 Transmit bus
1.4-V PCML AR37 Transmit bus
1.4-V PCML AN36 Transmit bus
1.4-V PCML AN37 Transmit bus
1.4-V PCML AL36 Transmit bus
1.4-V PCML AL37 Transmit bus
1.4-V PCML AG36 Transmit bus
1.4-V PCML AG37 Transmit bus
1.4-V PCML AE36 Transmit bus
1.4-V PCML AE37 Transmit bus
1.4-V PCML AC36 Transmit bus
1.4-V PCML AC37 Transmit bus
1.4-V PCML AA36 Transmit bus
1.4-V PCML AA37 Transmit bus
1.4-V PCML — JTAG chain clock
1.4-V PCML — JTAG chain data in
1.4-V PCML — JTAG chain data out
1.4-V PCML — JTAG chain mode select
LVTTL — Presence detect DIP switch
LVTTL — Presence detect DIP switch
LVTTL — Presence detect DIP switch
LVTTL — Presence detect DIP switch
HCSL AF35 Motherboard reference clock
HCSL AF34 Motherboard reference clock
LVTTL AN33 SMB clock
LVTTL AL34 SMB data
LVTTL AN32 Wake signal
LVTTL AC28 Reset
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–34 Chapter 2: Board Components
Components and Interfaces
10/100/1000 Ethernet
The development board supports a 10/100/1000 BASE-T Ethernet connection using a
Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC
function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to
the FPGA. The Stratix V GS device can communicate with the LVDS interfaces at up to
1.25 Gbps. The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires
a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45
with internal magnetics that can be used for driving copper lines with Ethernet traffic.
Figure 2–7 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Figure 2–7. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
S_OUT ±
MAC
±
S_IN
SGMII Interface
88E1111
Device
Transformer
Tab le 2– 38 lists the Ethernet PHY interface pin assignments.
Table 2–38. Ethernet PHY Pin Assignments, Signal Names and Functions
Board
Reference
(U19)
82
81
77
75
28
25
24
23
74
73
69
68
Schematic Signal Name I/O Standard
ENET_TX_P
ENET_TX_N
ENET_RX_P
ENET_RX_N
ENET_RESETn
ENET_MDC
ENET_MDIO
ENET_INTn
ENET_LED_LINK100
ENET_LED_LINK1000
ENET_LED_RX
ENET_LED_TX
LVDS AB27 SGMII transmit
LVDS AC27 SGMII transmit
LVDS AP34 SGMII receive
LVDS AR34 SGMII receive
2.5-V AA28 Device reset
2.5-V AA26 Management bus data clock
2.5-V AA27 Management bus data
2.5-V AA29 Management bus Interrupt
2.5-V — 100-Mb link LED
2.5-V — 1000-Mb link LED
2.5-V — RX data active LED
2.5-V — TX data active LED
Stratix V GS Device Pin
Number
RJ45
Description
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–35
Components and Interfaces
Tab le 2– 39 lists the Ethernet PHY interface component reference and manufacturing
information.
Table 2–39. Ethernet PHY Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U19 Ethernet PHY BASE-T device
Marvel
Semiconductor
High-Speed Mezzanine Cards (HSMC)
The development board contains two HSMC interfaces—port A and port B—to
provide 8 channels in port A and 4 channels in port B of 10.0 Gbps-capable
transceivers. Port A supports a full SPI4.2 interface (17 LVDS channels) and 3 input
and output clocks as well as SMBus and JTAG signals. The LVDS channels can be
used for CMOS signaling as well as LVDS. For Port B, other than the 3 input and
output clocks as well as SMBus and JTAG signals, it also covers the new DQS
standard to support daughtercards with external memory devices. For memory
support, the VCCIO banks for the HSMC port B is adjustable between 1.2 V, 1.5 V,
1.8 V, and 2.5 V. When the DQS features are not used, these channels can be used for
CMOS signaling.
The HSMC port A interface supports both single-ended and differential signaling.
The HSMC is an Altera-developed open specification, which allows you to expand
the functionality of the development board through the addition of daughtercards.
The HSMC port B is a new DQS standard to support both single-ended signaling and
external memory interfaces.
Manufacturing
Part Number
88E1111-B2-CAAIC000 www.marvell.com
Manufacturer
Website
f For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, cabling solutions, and mechanical
information, refer to the High Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–36 Chapter 2: Board Components
Components and Interfaces
Figure 2–8 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
Figure 2–8. HSMC Signal and Bank Diagram
Bank 3
Powe r
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Powe r
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. You can also use these pins as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Tab le 2– 40 lists the HSMC port A interface pin assignments, signal names, and
functions.
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
(J1)
40
98
158
96
156
39
97
157
95
155
30
32
Schematic Signal Name I/O Standard
HSMA_CLK_IN0
HSMA_CLK_IN_N1
HSMA_CLK_IN_N2
HSMA_CLK_IN_P1
HSMA_CLK_IN_P2
HSMA_CLK_OUT0
HSMA_CLK_OUT_N1
HSMA_CLK_OUT_N2
HSMA_CLK_OUT_P1
HSMA_CLK_OUT_P2
HSMA_RX_P0
HSMA_RX_N0
LVDS or 2.5-V AG28 Primary single-ended clock in
LVDS or 2.5-V AT8 LVDS or CMOS clock in 1
LVDS or 2.5-V G6 LVDS or CMOS clock in 2
LVDS or 2.5-V AR8 Secondary differential clock in
LVDS or 2.5-V G7 Primary source-synchronous clock in
LVDS or 2.5-V AJ10 Primary single-ended clock out
LVDS or 2.5-V AH9 LVDS or CMOS clock out 1
LVDS or 2.5-V G8 LVDS or CMOS clock out 2
LVDS or 2.5-V AG9 Secondary differential clock out
LVDS or 2.5-V G9 Primary source-synchronous clock out
1.4-V PCML AV2 Transceiver receive channel
1.4-V PCML AV1 Transceiver receive channel
Stratix V GS
Device Pin
Number
Description
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–37
Components and Interfaces
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
(J1)
26
28
22
24
18
20
14
16
10
12
6
8
2
4
29
31
25
27
21
23
17
19
13
15
9
11
5
7
1
3
41
42
43
44
35
38
37
36
Schematic Signal Name I/O Standard
HSMA_RX_P1
HSMA_RX_N1
HSMA_RX_P2
HSMA_RX_N2
HSMA_RX_P3
HSMA_RX_N3
HSMA_RX_P4
HSMA_RX_N4
HSMA_RX_P5
HSMA_RX_N5
HSMA_RX_P6
HSMA_RX_N6
HSMA_RX_P7
HSMA_RX_N7
HSMA_TX_P0
HSMA_TX_N0
HSMA_TX_P1
HSMA_TX_N1
HSMA_TX_P2
HSMA_TX_N2
HSMA_TX_P3
HSMA_TX_N3
HSMA_TX_P4
HSMA_TX_N4
HSMA_TX_P5
HSMA_TX_N5
HSMA_TX_P6
HSMA_TX_N6
HSMA_TX_P7
HSMA_TX_N7
HSMA_D0
HSMA_D1
HSMA_D2
HSMA_D3
JTAG_TCK
JTAG_FPGA_TDO_RETIMER
HSMA_JTAG_TDO
HSMA_JTAG_TMS
1.4-V PCML AP2 Transceiver receive channel
1.4-V PCML AP1 Transceiver receive channel
1.4-V PCML AM2 Transceiver receive channel
1.4-V PCML AM1 Transceiver receive channel
1.4-V PCML AK2 Transceiver receive channel
1.4-V PCML AK1 Transceiver receive channel
1.4-V PCML AH2 Transceiver receive channel
1.4-V PCML AH1 Transceiver receive channel
1.4-V PCML AF2 Transceiver receive channel
1.4-V PCML AF1 Transceiver receive channel
1.4-V PCML AD2 Transceiver receive channel
1.4-V PCML AD1 Transceiver receive channel
1.4-V PCML AB2 Transceiver receive channel
1.4-V PCML AB1 Transceiver receive channel
1.4-V PCML AU4 Transceiver transmit channel
1.4-V PCML AU3 Transceiver transmit channel
1.4-V PCML AN4 Transceiver transmit channel
1.4-V PCML AN3 Transceiver transmit channel
1.4-V PCML AL4 Transceiver transmit channel
1.4-V PCML AL3 Transceiver transmit channel
1.4-V PCML AJ4 Transceiver transmit channel
1.4-V PCML AJ3 Transceiver transmit channel
1.4-V PCML AG4 Transceiver transmit channel
1.4-V PCML AG3 Transceiver transmit channel
1.4-V PCML AE4 Transceiver transmit channel
1.4-V PCML AE3 Transceiver transmit channel
1.4-V PCML AC4 Transceiver transmit channel
1.4-V PCML AC3 Transceiver transmit channel
1.4-V PCML AA4 Transceiver transmit channel
1.4-V PCML AA3 Transceiver transmit channel
2.5-V AJ29 Dedicated CMOS I/O bit 0
2.5-V AK29 Dedicated CMOS I/O bit 1
2.5-V AR28 Dedicated CMOS I/O bit 2
2.5-V AP28 Dedicated CMOS I/O bit 3
2.5-V — JTAG clock
2.5-V — JTAG data input
2.5-V — JTAG data output
2.5-V — JTAG mode select
Stratix V GS
Device Pin
Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–38 Chapter 2: Board Components
Components and Interfaces
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
(J1)
160
34
33
50
56
62
68
74
80
86
92
104
110
116
122
128
134
140
146
152
48
54
60
66
72
78
84
90
102
108
114
120
126
132
138
144
150
49
Schematic Signal Name I/O Standard
HSMA_PRSNTn
HSMA_SCL
HSMA_SDA
HSMA_RX_D_N0
HSMA_RX_D_N1
HSMA_RX_D_N2
HSMA_RX_D_N3
HSMA_RX_D_N4
HSMA_RX_D_N5
HSMA_RX_D_N6
HSMA_RX_D_N7
HSMA_RX_D_N8
HSMA_RX_D_N9
HSMA_RX_D_N10
HSMA_RX_D_N11
HSMA_RX_D_N12
HSMA_RX_D_N13
HSMA_RX_D_N14
HSMA_RX_D_N15
HSMA_RX_D_N16
HSMA_RX_D_P0
HSMA_RX_D_P1
HSMA_RX_D_P2
HSMA_RX_D_P3
HSMA_RX_D_P4
HSMA_RX_D_P5
HSMA_RX_D_P6
HSMA_RX_D_P7
HSMA_RX_D_P8
HSMA_RX_D_P9
HSMA_RX_D_P10
HSMA_RX_D_P11
HSMA_RX_D_P12
HSMA_RX_D_P13
HSMA_RX_D_P14
HSMA_RX_D_P15
HSMA_RX_D_P16
HSMA_TX_D_N0
2.5-V AW8 Presence detect signal
2.5-V AM29 Management serial clock line
2.5-V AL29 Management serial data line
LVDS or 2.5-V AW11 Data bus
LVDS or 2.5-V AU12 Data bus
LVDS or 2.5-V AR12 Data bus
LVDS or 2.5-V AK12 Data bus
LVDS or 2.5-V AJ12 Data bus
LVDS or 2.5-V AG10 Data bus
LVDS or 2.5-V AE12 Data bus
LVDS or 2.5-V AC10 Data bus
LVDS or 2.5-V R9 Data bus
LVDS or 2.5-V L9 Data bus
LVDS or 2.5-V L8 Data bus
LVDS or 2.5-V G11 Data bus
LVDS or 2.5-V F9 Data bus
LVDS or 2.5-V E8 Data bus
LVDS or 2.5-V E11 Data bus
LVDS or 2.5-V C9 Data bus
LVDS or 2.5-V A10 Data bus
LVDS or 2.5-V AV11 Data bus
LVDS or 2.5-V AT12 Data bus
LVDS or 2.5-V AR11 Data bus
LVDS or 2.5-V AL12 Data bus
LVDS or 2.5-V AH12 Data bus
LVDS or 2.5-V AF10 Data bus
LVDS or 2.5-V AD12 Data bus
LVDS or 2.5-V AB10 Data bus
LVDS or 2.5-V T9 Data bus
LVDS or 2.5-V M9 Data bus
LVDS or 2.5-V M8 Data bus
LVDS or 2.5-V H11 Data bus
LVDS or 2.5-V G10 Data bus
LVDS or 2.5-V F8 Data bus
LVDS or 2.5-V F11 Data bus
LVDS or 2.5-V C8 Data bus
LVDS or 2.5-V B10 Data bus
LVDS or 2.5-V AU11 Data bus
Stratix V GS
Device Pin
Number
Description
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–39
Components and Interfaces
Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
(J1)
55
61
67
73
79
85
91
103
109
115
121
127
133
139
145
151
47
53
59
65
71
77
83
89
101
107
113
119
125
131
137
143
149
Schematic Signal Name I/O Standard
HSMA_TX_D_N1
HSMA_TX_D_N2
HSMA_TX_D_N3
HSMA_TX_D_N4
HSMA_TX_D_N5
HSMA_TX_D_N6
HSMA_TX_D_N7
HSMA_TX_D_N8
HSMA_TX_D_N9
HSMA_TX_D_N10
HSMA_TX_D_N11
HSMA_TX_D_N12
HSMA_TX_D_N13
HSMA_TX_D_N14
HSMA_TX_D_N15
HSMA_TX_D_N16
HSMA_TX_D_P0
HSMA_TX_D_P1
HSMA_TX_D_P2
HSMA_TX_D_P3
HSMA_TX_D_P4
HSMA_TX_D_P5
HSMA_TX_D_P6
HSMA_TX_D_P7
HSMA_TX_D_P8
HSMA_TX_D_P9
HSMA_TX_D_P10
HSMA_TX_D_P11
HSMA_TX_D_P12
HSMA_TX_D_P13
HSMA_TX_D_P14
HSMA_TX_D_P15
HSMA_TX_D_P16
LVDS or 2.5-V AN11 Data bus
LVDS or 2.5-V AL11 Data bus
LVDS or 2.5-V AF11 Data bus
LVDS or 2.5-V AE11 Data bus
LVDS or 2.5-V AE9 Data bus
LVDS or 2.5-V AC9 Data bus
LVDS or 2.5-V AC12 Data bus
LVDS or 2.5-V P8 Data bus
LVDS or 2.5-V N10 Data bus
LVDS or 2.5-V N9 Data bus
LVDS or 2.5-V J9 Data bus
LVDS or 2.5-V H10 Data bus
LVDS or 2.5-V D9 Data bus
LVDS or 2.5-V C10 Data bus
LVDS or 2.5-V A11 Data bus
LVDS or 2.5-V B8 Data bus
LVDS or 2.5-V AT11 Data bus
LVDS or 2.5-V AM11 Data bus
LVDS or 2.5-V AK11 Data bus
LVDS or 2.5-V AG12 Data bus
LVDS or 2.5-V AE10 Data bus
LVDS or 2.5-V AD9 Data bus
LVDS or 2.5-V AB9 Data bus
LVDS or 2.5-V AB12 Data bus
LVDS or 2.5-V R8 Data bus
LVDS or 2.5-V P10 Data bus
LVDS or 2.5-V N8 Data bus
LVDS or 2.5-V K9 Data bus
LVDS or 2.5-V J10 Data bus
LVDS or 2.5-V E9 Data bus
LVDS or 2.5-V D10 Data bus
LVDS or 2.5-V B11 Data bus
LVDS or 2.5-V A8 Data bus
Stratix V GS
Device Pin
Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–40 Chapter 2: Board Components
Components and Interfaces
Tab le 2– 41 lists the HSMC port B interface pin assignments, signal names, and
functions.
Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference
(J2)
30
32
26
28
22
24
18
20
29
31
25
27
21
23
17
19
158
96
156
39
97
157
95
155
50
54
56
60
62
74
78
80
84
86
104
108
Schematic Signal Name I/O Standard
HSMB_RX_P0
HSMB_RX_N0
HSMB_RX_P1
HSMB_RX_N1
HSMB_RX_P2
HSMB_RX_N2
HSMB_RX_P3
HSMB_RX_N3
HSMB_TX_P0
HSMB_TX_N0
HSMB_TX_P1
HSMB_TX_N1
HSMB_TX_P2
HSMB_TX_N2
HSMB_TX_P3
HSMB_TX_N3
HSMB_CLK_IN_N2
HSMB_CLK_IN_P1
HSMB_CLK_IN_P2
HSMB_CLK_OUT0
HSMB_CLK_OUT_N1
HSMB_CLK_OUT_N2
HSMB_CLK_OUT_P1
HSMB_CLK_OUT_P2
HSMB_A0
HSMB_A1
HSMB_A2
HSMB_A3
HSMB_A4
HSMB_A5
HSMB_A6
HSMB_A7
HSMB_A8
HSMB_A9
HSMB_A10
HSMB_A11
1.4-V PCML F2 Transceiver receive channel
1.4-V PCML F1 Transceiver receive channel
1.4-V PCML D2 Transceiver receive channel
1.4-V PCML D1 Transceiver receive channel
1.4-V PCML Y2 Transceiver receive channel
1.4-V PCML Y1 Transceiver receive channel
1.4-V PCML V2 Transceiver receive channel
1.4-V PCML V1 Transceiver receive channel
1.4-V PCML E4 Transceiver transmit channel
1.4-V PCML E3 Transceiver transmit channel
1.4-V PCML C4 Transceiver transmit channel
1.4-V PCML C3 Transceiver transmit channel
1.4-V PCML W4 Transceiver transmit channel
1.4-V PCML W3 Transceiver transmit channel
1.4-V PCML U4 Transceiver transmit channel
1.4-V PCML U3 Transceiver transmit channel
LVDS or 2.5-V N16 LVDS or CMOS clock in 2
LVDS or 2.5-V U15 Secondary differential clock in
LVDS or 2.5-V P16 Primary source-synchronous clock in
LVDS or 2.5-V L16 Primary single-ended clock out
LVDS or 2.5-V C16 LVDS or CMOS clock out 1
LVDS or 2.5-V A16 LVDS or CMOS clock out 2
LVDS or 2.5-V D16 Secondary differential clock out
LVDS or 2.5-V B16 Primary source-synchronous clock out
2.5-V CMOS N17 Memory address bit
2.5-V CMOS P17 Memory address bit
2.5-V CMOS H13 Memory address bit
2.5-V CMOS G14 Memory address bit
2.5-V CMOS L18 Memory address bit
2.5-V CMOS L19 Memory address bit
2.5-V CMOS K19 Memory address bit
2.5-V CMOS J18 Memory address bit
2.5-V CMOS A17 Memory address bit
2.5-V CMOS B17 Memory address bit
2.5-V CMOS G18 Memory address bit
2.5-V CMOS C18 Memory address bit
Stratix V GS
Device Pin Number
Description
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–41
Components and Interfaces
Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference
(J2)
110
114
116
128
43
132
134
138
140
151
149
44
150
40
98
152
48
72
102
126
47
49
53
55
59
61
65
67
71
73
77
79
83
85
89
91
101
103
Schematic Signal Name I/O Standard
HSMB_A12
HSMB_A13
HSMB_A14
HSMB_A15
HSMB_ADDR_CMD0
HSMB_BA0
HSMB_BA1
HSMB_BA2
HSMB_BA3
HSMB_C_N
HSMB_C_P
HSMB_CASN
HSMB_CKE
HSMB_CLK_IN0
HSMB_CLK_IN_N1
HSMB_CSN
HSMB_DM0
HSMB_DM1
HSMB_DM2
HSMB_DM3
HSMB_DQ0
HSMB_DQ1
HSMB_DQ2
HSMB_DQ3
HSMB_DQ4
HSMB_DQ5
HSMB_DQ6
HSMB_DQ7
HSMB_DQ8
HSMB_DQ9
HSMB_DQ10
HSMB_DQ11
HSMB_DQ12
HSMB_DQ13
HSMB_DQ14
HSMB_DQ15
HSMB_DQ16
HSMB_DQ17
2.5-V CMOS D18 Memory address bit
2.5-V CMOS A19 Memory address bit
2.5-V CMOS B19 Memory address bit
2.5-V CMOS C19 Memory address bit
2.5-V CMOS M18 Memory address or command
2.5-V CMOS E18 Memory bank address bit
2.5-V CMOS D19 Memory bank address bit
2.5-V CMOS F18 Memory bank address bit
2.5-V CMOS E19 Memory bank address bit
2.5-V CMOS M15 ODT
2.5-V CMOS N15 QVLD
2.5-V CMOS R16 Memory address or command
2.5-V CMOS G19 Memory address or command
LVDS or 2.5-V AF29 Primary single-ended clock in
LVDS or 2.5-V T16 LVDS or CMOS clock in 1
2.5-V CMOS H19 Memory address or command
2.5-V CMOS U11 Data mask
2.5-V CMOS J13 Data mask
2.5-V CMOS U12 Data mask
2.5-V CMOS H14 Data mask
2.5-V CMOS T12 Memory data bus
2.5-V CMOS R12 Memory data bus
2.5-V CMOS N12 Memory data bus
2.5-V CMOS N13 Memory data bus
2.5-V CMOS M12 Memory data bus
2.5-V CMOS L12 Memory data bus
2.5-V CMOS K12 Memory data bus
2.5-V CMOS J12 Memory data bus
2.5-V CMOS G12 Memory data bus
2.5-V CMOS G13 Memory data bus
2.5-V CMOS F12 Memory data bus
2.5-V CMOS E12 Memory data bus
2.5-V CMOS D12 Memory data bus
2.5-V CMOS C12 Memory data bus
2.5-V CMOS B13 Memory data bus
2.5-V CMOS A13 Memory data bus
2.5-V CMOS U13 Memory data bus
2.5-V CMOS T13 Memory data bus
Stratix V GS
Device Pin Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–42 Chapter 2: Board Components
Components and Interfaces
Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board
Reference
(J2)
107
109
113
115
119
121
125
127
131
133
137
139
143
145
68
92
122
146
66
90
120
144
35
38
37
36
160
42
34
33
41
Schematic Signal Name I/O Standard
HSMB_DQ18
HSMB_DQ19
HSMB_DQ20
HSMB_DQ21
HSMB_DQ22
HSMB_DQ23
HSMB_DQ24
HSMB_DQ25
HSMB_DQ26
HSMB_DQ27
HSMB_DQ28
HSMB_DQ29
HSMB_DQ30
HSMB_DQ31
HSMB_DQS_N0
HSMB_DQS_N1
HSMB_DQS_N2
HSMB_DQS_N3
HSMB_DQS_P0
HSMB_DQS_P1
HSMB_DQS_P2
HSMB_DQS_P3
JTAG_TCK
HSMB_JTAG_TDI
HSMB_JTAG_TDO
HSMB_JTAG_TMS
HSMB_PRSNTN
HSMB_RASN
HSMB_SCL
HSMB_SDA
HSMB_WEN
2.5-V CMOS N14 Memory data bus
2.5-V CMOS M14 Memory data bus
2.5-V CMOS U14 Memory data bus
2.5-V CMOS L15 Memory data bus
2.5-V CMOS J14 Memory data bus
2.5-V CMOS J15 Memory data bus
2.5-V CMOS G15 Memory data bus
2.5-V CMOS F14 Memory data bus
2.5-V CMOS F15 Memory data bus
2.5-V CMOS E14 Memory data bus
2.5-V CMOS B14 Memory data bus
2.5-V CMOS A14 Memory data bus
2.5-V CMOS C14 Memory data bus
2.5-V CMOS C15 Memory data bus
2.5-V CMOS K13 Memory data strobe (negative)
2.5-V CMOS C13 Memory data strobe (negative)
2.5-V CMOS P14 Memory data strobe (negative)
2.5-V CMOS D15 Memory data strobe (negative)
2.5-V CMOS L13 Memory data strobe (positive)
2.5-V CMOS D13 Memory data strobe (positive)
2.5-V CMOS R14 Memory data strobe (positive)
2.5-V CMOS E15 Memory data strobe (positive)
2.5-V AA31 JTAG clock
2.5-V — JTAG data input
2.5-V — JTAG data output
2.5-V — JTAG mode select
2.5-V AU7 Presence detect signal
2.5-V CMOS P13 Memory address or command
2.5-V CMOS AL30 Management serial clock line
2.5-V CMOS AK30 Management serial data line
1.4-V PCML M17 Memory address or command
Stratix V GS
Device Pin Number
Description
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–43
Components and Interfaces
Tab le 2– 42 lists the HSMC connector component reference and manufacturing
information.
Table 2–42. HSMC Connector Component Reference and Manufacturing Information
Board Reference Description Manufacturer
J1 and J2
HSMC, custom version of QSH-DP
family high-speed socket.
Samtec ASP-122953-01 www.samtec.com
SDI Video Output/Input
The serial digital interface (SDI) video port consists of a LMH0303 cable driver and a
LMH0384 receiver cable equalizer. The PHY devices from National Semiconductor
interface to single-ended 75-Ω SMB connectors.
The cable driver supports operation at 270 Mbit standard definition (SD), 1.5 Gbit
high definition (HD), and 3.0 Gbit dual-link HD modes. Control signals are allowed
for SD and HD modes selections, as well as device enable. The device can be clocked
by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to
incoming signals within 50 ppm using the UP and DN voltage control lines to the
VCXO.
Tab le 2– 43 shows the supported output standards for the SD and HD input.
Table 2–43. Supported Output Standards for SD and HD Input
SD_HD Input Supported Output Standards Rise TIme
0 SMPTE 424M, SMPTE 292M Faster
1 SMPTE 259M Slower
Manufacturing
Part Number
Manufacturer
Website
f For more information about the application circuit of the LMH0303 cable driver, refer
to the cable driver data sheet at www.national.com.
Tab le 2– 44 summarizes the SDI video output interface pin assignments, signal names,
and functions.
Table 2–44. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
(U25)
6
4
10
1
2
Schematic
Signal Name
SDI_TX_EN
SDI_TX_RSET
SDI_TX_SD_HDn
SDI_TX_P
SDI_TX_N
I/O Standard
2.5-V AK27 Device enable
3.3-V — Device reset
2.5-V AJ27 High definition select
1.4-V PCML E36 SDI video input P
1.4-V PCML E37 SDI video input N
Stratix V GS Device
Pin Number
Description
The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and 3.0 Gbit
dual-link HD modes. Control signals are allowed for bypassing or disabling the
device, as well as a carrier detect or auto-mute signal interface.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–44 Chapter 2: Board Components
BYPASS
MUTE
REF
1.0 μF
75 Ω
37.4 Ω
1.0 μF
1.0 μF
CD
SDI
SDI
SDO
SDO
CD
MUTE
MUTE
REF
BYPASS
AEC+
AEC–
75 Ω
MUTE
Coaxial Cable
SDI Adaptive
Cable Equalizer
To FPGA
5.6 nH
Components and Interfaces
Tab le 2– 45 shows the cable equalizer lengths.
Table 2–45. SDI Cable Equalizer Lengths
Data Rate (Mbps) Cable Type Maximum Cable Length (m)
270
1485 140
Belden 1694A
400
2970 120
Figure 2–9 is an excerpt from the LMH0384 cable equalizer data sheet which shows
the SDI cable equalizer.
Figure 2–9. SDI Cable Equalizer
Tab le 2– 46 summarizes the SDI video input interface pin assignments, signal names,
and functions.
Table 2–46. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
(U24)
7
14
11
10
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Schematic
Signal Name
SDI_RX_BYPASS
SDI_RX_EN
SDI_RX_P
SDI_RX_N
I/O Standard
Stratix V GS Device
Pin Number
2.5-V AB30 Equalizer bypass enable
2.5-V AB28 Device enable
1.4-V PCML F38 SDI video output P
1.4-V PCML F39 SDI video output N
Description
Chapter 2: Board Components 2–45
Components and Interfaces
Tab le 2– 47 lists the SDI connector component reference and manufacturing
information.
Table 2–47. HSMC Connector Component Reference and Manufacturing Information
Board
Reference
U25 3-Gbps HD/SD SDI cable driver National Semiconductor LMH0303SQ www.national.com
U24
3-Gbps HD/SD SDI adaptive cable
equalizer
Description Manufacturer
National Semiconductor LMH0384SQ www.national.com
Manufacturing
Part Number
Manufacturer
Website
40G QSFP Connector
The development board has a 40G QSFP connector that uses four transceiver channels
from the Stratix V GS device. These modules takes in serial data from the Stratix V GS
device and transform them to optical signals. The board includes a cage assembly for
the QSFP connector.
Tab le 2– 48 summarizes the QSFP connector pin assignments, signal names, and
functions.
Table 2–48. 40G QSFP Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference
(J12)
17
18
22
21
14
15
25
24
36
37
3
2
33
34
6
5
28
31
27
8
9
QSFP_RX_P0
QSFP_RX_N0
QSFP_RX_P1
QSFP_RX_N1
QSFP_RX_P2
QSFP_RX_N2
QSFP_RX_P3
QSFP_RX_N3
QSFP_TX_P0
QSFP_TX_N0
QSFP_TX_P1
QSFP_TX_N1
QSFP_TX_P2
QSFP_TX_N2
QSFP_TX_P3
QSFP_TX_N3
QSFP_INTERRUPTn
QSFP_LP_MODE
QSFP_MOD_PRSn
QSFP_MOD_SELn
QSFP_RSTn
Schematic
Signal Name
I/O Standard
CML P38 QSFP receiver data
CML P39 QSFP receiver data
CML M38 QSFP receiver data
CML M39 QSFP receiver data
CML K38 QSFP receiver data
CML K39 QSFP receiver data
CML H38 QSFP receiver data
CML H39 QSFP receiver data
CML N36 QSFP transmiter data
CML N37 QSFP transmiter data
CML L36 QSFP transmiter data
CML L37 QSFP transmiter data
CML J36 QSFP transmiter data
CML J37 QSFP transmiter data
CML G36 QSFP transmiter data
CML G37 QSFP transmiter data
3.3-V LVTTL AE27 QSFP interrupt
3.3-V LVTTL AD27 QSFP low power mode
3.3-V LVTTL AH27 Module present
3.3-V LVTTL AG27 Module select
3.3-V LVTTL AE30 Module reset
Stratix V GS Device
Pin Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–46 Chapter 2: Board Components
Memory
Table 2–48. 40G QSFP Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Board
Reference
(J12)
11
12
QSFP_SCL
QSFP_SDA
Schematic
Signal Name
I/O Standard
3.3-V LVTTL AD30 QSFP serial 2-wire clock
3.3-V LVTTL AC30 QSFP serial 2-wire data
Stratix V GS Device
Pin Number
Tab le 2– 49 lists the QSFP interface component reference and manufacturing
information.
Table 2–49. QSFP Interface Component Reference and Manufacturing Information
Board
Reference
J12
Description Manufacturer
QSFP cage Tyco Electronics 1888617-1 www.te.com
QSFP connector Tyco Electronics 1761987-9 www.te.com
Manufacturing
Part Number
Memory
This section describes the board’s memory interface support, signal names, types, and
connectivity relative to the Stratix V GS device. The board has the following memory
interfaces:
■ DDR3
Description
Manufacturer
Website
■ QDRII+
■ RLDRAM II
■ Flash
f For more information about the memory interfaces, refer to the External Memory
Interface Handbook page of the Altera website..
DDR3
The development board supports a 16Mx72x8 bank DDR3 SDRAM interface for very
high-speed sequential memory access. The 72-bit data bus comprises of four x16
devices and one x8 device with a single address or command bus. This interface
connects to the vertical I/O banks on the top edge of the FPGA.
The DDR3 devices shipped with this board are running at 800 MHz, for a total
theoretical bandwidth of over 1115.2 Gbps. These devices run at a minimum
frequency of 303 MHz.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–47
Memory
Tab le 2– 50 lists the DDR3 devices pin assignments, signal names, and functions.
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board Reference
(U12, U17, U21,
Schematic Signal
U23, U28)
DDR3 x16 / DDR3 x8 pins
T3
N7
R7
L7
R3
T8
R2
R8
P2
P8
N2
P3
P7
N3
M3
N8
M2
T2
J3
K3
L2
L3
K1
L8
K9
J7
K7
DDR3_A13
DDR3_A12
DDR3_A11
DDR3_A10
DDR3_A9
DDR3_A8
DDR3_A7
DDR3_A6
DDR3_A5
DDR3_A4
DDR3_A3
DDR3_A2
DDR3_A1
DDR3_A0
DDR3_BA2
DDR3_BA1
DDR3_BA0
DDR3_RESETn
DDR3_RASn
DDR3_CASn
DDR3_CSn
DDR3_WEn
DDR3_ODT
DDR3_ZQ
DDR3_CKE
DDR3_CLK_P
DDR3_CLK_N
Name
I/O Standard
Stratix V GS Device
Pin Number
Description
1.5-V SSTL Class I J31 Address bus
1.5-V SSTL Class I R30 Address bus
1.5-V SSTL Class I L31 Address bus
1.5-V SSTL Class I J30 Address bus
1.5-V SSTL Class I J29 Address bus
1.5-V SSTL Class I P31 Address bus
1.5-V SSTL Class I F30 Address bus
1.5-V SSTL Class I N31 Address bus
1.5-V SSTL Class I E31 Address bus
1.5-V SSTL Class I L30 Address bus
1.5-V SSTL Class I D31 Address bus
1.5-V SSTL Class I H31 Address bus
1.5-V SSTL Class I K31 Address bus
1.5-V SSTL Class I G31 Address bus
1.5-V SSTL Class I E30 Bank address bus
1.5-V SSTL Class I K30 Bank address bus
1.5-V SSTL Class I C31 Bank address bus
1.5-V SSTL Class I G30 Reset
1.5-V SSTL Class I B26 Row address select
1.5-V SSTL Class I B28 Column address select
1.5-V SSTL Class I B31 Chip select
1.5-V SSTL Class I C30 Write enable
1.5-V SSTL Class I A31 On-die termination enable
1.5-V SSTL Class I — ZQ impedance calibration
1.5-V SSTL Class I R31 Clock enable
1.5-V SSTL Class I N30 Differential output clock
1.5-V SSTL Class I M30 Differential output clock
DDR3 x16 pins
U28.E3
U28.F7
U28.F2
U28.F8
U28.H3
U28.H8
U28.G2
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
1.5-V SSTL Class I A28 Data bus byte lane 0
1.5-V SSTL Class I E28 Data bus byte lane 0
1.5-V SSTL Class I B29 Data bus byte lane 0
1.5-V SSTL Class I F29 Data bus byte lane 0
1.5-V SSTL Class I D28 Data bus byte lane 0
1.5-V SSTL Class I H28 Data bus byte lane 0
1.5-V SSTL Class I C28 Data bus byte lane 0
Reference Manual
2–48 Chapter 2: Board Components
Memory
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board Reference
(U12, U17, U21,
U23, U28)
U28.H7
U28.E7
U28.F3
U28.G3
U28.D7
U28.C3
U28.C8
U28.C2
U28.A7
U28.A2
U28.B8
U28.A3
U28.D3
U28.C7
U28.B7
U23.E3
U23.F7
U23.F2
U23.F8
U23.H3
U23.H8
U23.G2
U23.H7
U23.E7
U23.F3
U28.G3
U23.D7
U23.C3
U23.C8
U23.C2
U23.A7
U23.A2
U23.B8
U23.A3
U23.D3
U23.C7
U23.B7
U21.E3
Schematic Signal
Name
DDR3_DQ7
DDR3_DM0
DDR3_DQS_P0
DDR3_DQS_N0
DDR3_DQ8
DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DM1
DDR3_DQS_P1
DDR3DQS_N1
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DM2
DDR3_DQS_P2
DDR3_DQS_N2
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_DM3
DDR3_DQS_P3
DDR3_DQS_N3
DDR3_DQ32
I/O Standard
Stratix V GS Device
Pin Number
Description
1.5-V SSTL Class I G28 Data bus byte lane 0
1.5-V SSTL Class I A29 Write mask byte lane 0
1.5-V SSTL Class I H29 Data strobe P byte lane 0
1.5-V SSTL Class I G29 Data strobe N byte lane 0
1.5-V SSTL Class I K28 Data bus byte lane 1
1.5-V SSTL Class I M29 Data bus byte lane 1
1.5-V SSTL Class I L28 Data bus byte lane 1
1.5-V SSTL Class I R29 Data bus byte lane 1
1.5-V SSTL Class I P29 Data bus byte lane 1
1.5-V SSTL Class I V29 Data bus byte lane 1
1.5-V SSTL Class I N28 Data bus byte lane 1
1.5-V SSTL Class I U29 Data bus byte lane 1
1.5-V SSTL Class I J28 Write mask byte lane 1
1.5-V SSTL Class I U30 Data strobe P byte lane 1
1.5-V SSTL Class I T30 Data strobe N byte lane 1
1.5-V SSTL Class I G26 Data bus byte lane 2
1.5-V SSTL Class I D27 Data bus byte lane 2
1.5-V SSTL Class I F26 Data bus byte lane 2
1.5-V SSTL Class I C27 Data bus byte lane 2
1.5-V SSTL Class I C26 Data bus byte lane 2
1.5-V SSTL Class I J26 Data bus byte lane 2
1.5-V SSTL Class I E27 Data bus byte lane 2
1.5-V SSTL Class I H26 Data bus byte lane 2
1.5-V SSTL Class I A26 Write mask byte lane 2
1.5-V SSTL Class I G27 Data strobe P byte lane 2
1.5-V SSTL Class I F27 Data strobe N byte lane 2
1.5-V SSTL Class I J27 Data bus byte lane 3
1.5-V SSTL Class I N27 Data bus byte lane 3
1.5-V SSTL Class I T27 Data bus byte lane 3
1.5-V SSTL Class I M27 Data bus byte lane 3
1.5-V SSTL Class I U26 Data bus byte lane 3
1.5-V SSTL Class I P28 Data bus byte lane 3
1.5-V SSTL Class I U27 Data bus byte lane 3
1.5-V SSTL Class I R27 Data bus byte lane 3
1.5-V SSTL Class I L27 Write mask byte lane 3
1.5-V SSTL Class I U28 Data strobe P byte lane 3
1.5-V SSTL Class I T28 Data strobe N byte lane 3
1.5-V SSTL Class I B25 Data bus byte lane 4
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–49
Memory
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board Reference
(U12, U17, U21,
U23, U28)
U21.F7
U21.F2
U21.F8
U21.H3
U21.H8
U21.G2
U21.H7
U21.E7
U21.F3
U21.G3
U21.D7
U21.C3
U21.C8
U21.C2
U21.A7
U21.A2
U21.B8
U21.A3
U21.D3
U21.C7
U21.B7
U17.E3
U17.F7
U17.F2
U17.F8
U17.H3
U17.H8
U17.G2
U17.H7
U17.E7
U17.F3
U17.G3
U17.D7
U17.C3
U17.C8
U17.C2
U17.A7
U17.A2
Schematic Signal
Name
DDR3_DQ33
DDR3_DQ34
DDR3_DQ35
DDR3_DQ36
DDR3_DQ37
DDR3_DQ38
DDR3_DQ39
DDR3_DM4
DDR3DQS_P4
DDR3_DQS_N4
DDR3_DQ40
DDR3_DQ41
DDR3_DQ42
DDR3_DQ43
DDR3_DQ44
DDR3_DQ45
DDR3_DQ46
DDR3_DQ47
DDR3_DM5
DDR3_DQS_P5
DDR3_DQS_N5
DDR3_DQ48
DDR3_DQ49
DDR3_DQ50
DDR3_DQ51
DDR3_DQ52
DDR3_DQ53
DDR3_DQ54
DDR3_DQ55
DDR3_DM6
DDR3_DQS_P6
DDR3_DQS_N6
DDR3_DQ56
DDR3_DQ57
DDR3_DQ58
DDR3_DQ59
DDR3_DQ60
DDR3_DQ61
I/O Standard
Stratix V GS Device
Pin Number
Description
1.5-V SSTL Class I F24 Data bus byte lane 4
1.5-V SSTL Class I C25 Data bus byte lane 4
1.5-V SSTL Class I G24 Data bus byte lane 4
1.5-V SSTL Class I D24 Data bus byte lane 4
1.5-V SSTL Class I H25 Data bus byte lane 4
1.5-V SSTL Class I C24 Data bus byte lane 4
1.5-V SSTL Class I G25 Data bus byte lane 4
1.5-V SSTL Class I A25 Write mask byte lane 4
1.5-V SSTL Class I E24 Data strobe P byte lane 4
1.5-V SSTL Class I E25 Data strobe N byte lane 4
1.5-V SSTL Class I J25 Data bus byte lane 5
1.5-V SSTL Class I N26 Data bus byte lane 5
1.5-V SSTL Class I L26 Data bus byte lane 5
1.5-V SSTL Class I P26 Data bus byte lane 5
1.5-V SSTL Class I P25 Data bus byte lane 5
1.5-V SSTL Class I T25 Data bus byte lane 5
1.5-V SSTL Class I N25 Data bus byte lane 5
1.5-V SSTL Class I U25 Data bus byte lane 5
1.5-V SSTL Class I K25 Write mask byte lane 5
1.5-V SSTL Class I R25 Data strobe P byte lane 5
1.5-V SSTL Class I R26 Data strobe N byte lane 5
1.5-V SSTL Class I H22 Data bus byte lane 6
1.5-V SSTL Class I B23 Data bus byte lane 6
1.5-V SSTL Class I G22 Data bus byte lane 6
1.5-V SSTL Class I G23 Data bus byte lane 6
1.5-V SSTL Class I D22 Data bus byte lane 6
1.5-V SSTL Class I H23 Data bus byte lane 6
1.5-V SSTL Class I C22 Data bus byte lane 6
1.5-V SSTL Class I A23 Data bus byte lane 6
1.5-V SSTL Class I A22 Write mask byte lane 6
1.5-V SSTL Class I F23 Data strobe P byte lane 6
1.5-V SSTL Class I E23 Data strobe N byte lane 6
1.5-V SSTL Class I A20 Data bus byte lane 7
1.5-V SSTL Class I C20 Data bus byte lane 7
1.5-V SSTL Class I F20 Data bus byte lane 7
1.5-V SSTL Class I C21 Data bus byte lane 7
1.5-V SSTL Class I H20 Data bus byte lane 7
1.5-V SSTL Class I D21 Data bus byte lane 7
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–50 Chapter 2: Board Components
Memory
Table 2–50. DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board Reference
(U12, U17, U21,
U23, U28)
U17.B8
U17.A3
U17.D3
U17.C7
U17.B7
DDR3 x8 pins
U12.B3
U12.C7
U12.C2
U12.C8
U12.E3
U12.E8
U12.D2
U12.E7
U12.B7
U12.C3
U12.D3
Schematic Signal
Name
DDR3_DQ62
DDR3_DQ63
DDR3_DM7
DDR3_DQS_P7
DDR3_DQS_N7
DDR3_DQ64
DDR3_DQ65
DDR3_DQ66
DDR3_DQ67
DDR3_DQ68
DDR3_DQ69
DDR3_DQ70
DDR3_DQ71
DDR3_DM8
DDR3_DQS_P8
DDR3_DQS_N8
I/O Standard
1.5-V SSTL Class I G20 Data bus byte lane 7
1.5-V SSTL Class I E20 Data bus byte lane 7
1.5-V SSTL Class I B20 Write mask byte lane 7
1.5-V SSTL Class I G21 Data strobe P byte lane 7
1.5-V SSTL Class I F21 Data strobe N byte lane 7
1.5-V SSTL Class I M20 Data bus byte lane 8
1.5-V SSTL Class I L20 Data bus byte lane 8
1.5-V SSTL Class I N22 Data bus byte lane 8
1.5-V SSTL Class I J21 Data bus byte lane 8
1.5-V SSTL Class I N21 Data bus byte lane 8
1.5-V SSTL Class I K21 Data bus byte lane 8
1.5-V SSTL Class I N20 Data bus byte lane 8
1.5-V SSTL Class I L21 Data bus byte lane 8
1.5-V SSTL Class I M21 Write mask byte lane 8
1.5-V SSTL Class I K22 Data strobe P byte lane 8
1.5-V SSTL Class I J22 Data strobe N byte lane 8
Stratix V GS Device
Pin Number
Description
Tab le 2– 51 lists the DDR3 component reference and manufacturing information.
Table 2–51. DDR3 Component Reference and Manufacturing Information
Board
Reference
U17, U21,
U23, U28
U12 16 M × 8-bit × 8 banks, 800 MHz, CL11 Micron MT41J128M8JP-125 www.micron.com
16 M × 16-bit × 8 banks, 800 MHz, CL11 Micron MT41J128M16HA-125 www.micron.com
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
QDRII+
The development board supports a burst-of-4 QDRII+ SRAM memory device for
very-high-speed, low-latency memory access. The QDRII+ has a x18 interface,
providing addressing to a device of up to a 32 Mb.
The QDRII+ has separate read and write data ports with DDR signaling at up to
550 MHz. The pinout and footprint is compatible with a burst-of-2 QDRII SSRAM
memory device. Although the FPGA supports up to 350 MHz QDRII data, the fastest
RoHS compliant QDRII device being manufactured is only 333 MHz.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–51
Memory
Tab le 2– 52 lists the QDRII+ pin assignments, signal names, and functions.
Table 2–52. QDRII+ Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board Reference
(U5)
A2
A10
A3
A9
R7
R5
R4
R3
P8
P7
P5
P4
N7
N6
N5
C7
C5
B8
B4
R8
R9
N2
M3
L3
J3
G2
F3
D2
C3
B3
C11
D11
E10
G11
J11
K10
M11
Schematic
Signal Name
QDRII_A20
QDRII_A19
QDRII_A18
QDRII_A17
QDRII_A16
QDRII_A15
QDRII_A14
QDRII_A13
QDRII_A12
QDRII_A11
QDRII_A10
QDRII_A9
QDRII_A8
QDRII_A7
QDRII_A6
QDRII_A5
QDRII_A4
QDRII_A3
QDRII_A2
QDRII_A1
QDRII_A0
QDRII_D17
QDRII_D16
QDRII_D15
QDRII_D14
QDRII_D13
QDRII_D12
QDRII_D11
QDRII_D10
QDRII_D9
QDRII_D8
QDRII_D7
QDRII_D6
QDRII_D5
QDRII_D4
QDRII_D3
QDRII_D2
I/O Standard
Stratix V GS Device
Pin Number
Description
1.8-V HSTL Class I AA13 Address bus (reserved for 144M)
1.8-V HSTL Class I AP12 Address bus (reserved for 72M)
1.8-V HSTL Class I AA12 Address bus
1.8-V HSTL Class I AN12 Address bus
1.8-V HSTL Class I AL13 Address bus
1.8-V HSTL Class I AF14 Address bus
1.8-V HSTL Class I AC13 Address bus
1.8-V HSTL Class I AB13 Address bus
1.8-V HSTL Class I AW14 Address bus
1.8-V HSTL Class I AM13 Address bus
1.8-V HSTL Class I AE14 Address bus
1.8-V HSTL Class I AC14 Address bus
1.8-V HSTL Class I AJ13 Address bus
1.8-V HSTL Class I AH13 Address bus
1.8-V HSTL Class I AD14 Address bus
1.8-V HSTL Class I AN13 Address bus
1.8-V HSTL Class I AG13 Address bus
1.8-V HSTL Class I AT14 Address bus
1.8-V HSTL Class I AF13 Address bus
1.8-V HSTL Class I AP13 Address bus
1.8-V HSTL Class I AU14 Address bus
1.8-V HSTL Class I AU15 Write data bus
1.8-V HSTL Class I AR15 Write data bus
1.8-V HSTL Class I AR14 Write data bus
1.8-V HSTL Class I AP15 Write data bus
1.8-V HSTL Class I AT15 Write data bus
1.8-V HSTL Class I AN14 Write data bus
1.8-V HSTL Class I AN15 Write data bus
1.8-V HSTL Class I AM14 Write data bus
1.8-V HSTL Class I AL15 Write data bus
1.8-V HSTL Class I AG14 Write data bus
1.8-V HSTL Class I AD16 Write data bus
1.8-V HSTL Class I AE15 Write data bus
1.8-V HSTL Class I AA14 Write data bus
1.8-V HSTL Class I AA15 Write data bus
1.8-V HSTL Class I AC15 Write data bus
1.8-V HSTL Class I AB15 Write data bus
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–52 Chapter 2: Board Components
Memory
Table 2–52. QDRII+ Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board Reference
(U5)
N11
P10
B6
A6
A4
B7
A5
P3
N3
L2
K3
G3
F2
E3
D3
B2
B11
C10
E11
F11
J10
K11
L11
M10
P11
P6
R6
A11
A1
A8
H1
Schematic
Signal Name
QDRII_D1
QDRII_D0
QDRII_K_P
QDRII_K_N
QDRII_WPSn
QDRII_BWSn0
QDRII_BWSn1
QDRII_Q17
QDRII_Q16
QDRII_Q15
QDRII_Q14
QDRII_Q13
QDRII_Q12
QDRII_Q11
QDRII_Q10
QDRII_Q9
QDRII_Q8
QDRII_Q7
QDRII_Q6
QDRII_Q5
QDRII_Q4
QDRII_Q3
QDRII_Q2
QDRII_Q1
QDRII_Q0
QDRII_C_P
QDRII_C_N
QDRII_CQ_P
QDRII_CQ_N
QDRII_RPSn
QDRII_DOFFn
I/O Standard
Stratix V GS Device
Pin Number
Description
1.8-V HSTL Class I AB16 Write data bus
1.8-V HSTL Class I AD15 Write data bus
1.8-V HSTL Class I AK14 Write clock P
1.8-V HSTL Class I AL14 Write clock N
1.8-V HSTL Class I AK15 Write port select
1.8-V HSTL Class I AH15 Write byte write select 0
1.8-V HSTL Class I AJ15 Write byte write select 1
1.8-V HSTL Class I AM19 Read data bus
1.8-V HSTL Class I AN18 Read data bus
1.8-V HSTL Class I AP19 Read data bus
1.8-V HSTL Class I AR18 Read data bus
1.8-V HSTL Class I AP18 Read data bus
1.8-V HSTL Class I AR19 Read data bus
1.8-V HSTL Class I AL18 Read data bus
1.8-V HSTL Class I AK18 Read data bus
1.8-V HSTL Class I AJ19 Read data bus
1.8-V HSTL Class I AH19 Read data bus
1.8-V HSTL Class I AJ18 Read data bus
1.8-V HSTL Class I AH18 Read data bus
1.8-V HSTL Class I AG19 Read data bus
1.8-V HSTL Class I AG18 Read data bus
1.8-V HSTL Class I AE19 Read data bus
1.8-V HSTL Class I AD18 Read data bus
1.8-V HSTL Class I AE18 Read data bus
1.8-V HSTL Class I AD17 Read data bus
1.8-V HSTL Class I AT18 Clock P
1.8-V HSTL Class I AU18 Clock N
1.8-V HSTL Class I AN19 Echo clock P
1.8-V HSTL Class I AF19 Echo clock N
1.8-V HSTL Class I AG15 Read port select
1.8-V HSTL Class I AV13 DLL enable
Tab le 2– 53 lists the QDRII+ component reference and manufacturing information.
Table 2–53. QDRII+ Component Reference and Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U5 QDRII+, 2 M × 18, 550 MHZ Cypress CY7C2263KV18-550BZXI www.cypress.com
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–53
Memory
RLDRAM II
The development board supports a 32Mx18x8 bank CIO RLDRAM II SRAM interface
for very-high-speed sequential memory access. The 18-bit data bus comprises of a
single x18 device with a single address or command bus. This interface connects to the
vertical I/O banks on the bottom edge of the FPGA. The target speed is 533 MHz.
Tab le 2– 54 lists the RLDRAM II pin assignments, signal names, and functions.
Table 2–54. RLDRAM II Pin Assignments, Signal Names and Functions (Part 1 of 2)
Board Reference
(U20)
G12
G11
G10
H12
H11
F1
G2
G3
G1
H2
M12
M11
M10
L12
L11
P1
M2
M3
N1
N12
E12
E1
D1
J11
K11
H1
K12
J12
L2
K2
K1
P12
Schematic Signal Name I/O Standard
RLDC_A0
RLDC_A1
RLDC_A2
RLDC_A3
RLDC_A4
RLDC_A5
RLDC_A6
RLDC_A7
RLDC_A8
RLDC_A9
RLDC_A10
RLDC_A11
RLDC_A12
RLDC_A13
RLDC_A14
RLDC_A15
RLDC_A16
RLDC_A17
RLDC_A18
RLDC_A19
RLDC_A20
RLDC_A21
RLDC_A22
RLDC_BA0
RLDC_BA1
RLDC_BA2
RLDC_CK_N
RLDC_CK_P
RLDC_CSN
RLDC_DK_N
RLDC_DK_P
RLDC_DM
1.8-V HSTL Class I AD22 Address bus
1.8-V HSTL Class AW22 Address bus
1.8-V HSTL Class I AW23 Address bus
1.8-V HSTL Class I AD23 Address bus
1.8-V HSTL Class I AE22 Address bus
1.8-V HSTL Class I AU23 Address bus
1.8-V HSTL Class I AT23 Address bus
1.8-V HSTL Class I AT20 Address bus
1.8-V HSTL Class I AG23 Address bus
1.8-V HSTL Class I AM23 Address bus
1.8-V HSTL Class I AM20 Address bus
1.8-V HSTL Class I AW20 Address bus
1.8-V HSTL Class I AV20 Address bus
1.8-V HSTL Class I AG22 Address bus
1.8-V HSTL Class I AF23 Address bus
1.8-V HSTL Class I AR21 Address bus
1.8-V HSTL Class I AP22 Address bus
1.8-V HSTL Class I AR20 Address bus
1.8-V HSTL Class I AR22 Address bus
1.8-V HSTL Class I AN20 Address bus
1.8-V HSTL Class I AU20 Address bus
1.8-V HSTL Class I AV23 Address bus
1.8-V HSTL Class I AV22 Address bus
1.8-V HSTL Class I AE23 Bank address bus
1.8-V HSTL Class I AF22 Bank address bus
1.8-V HSTL Class I AK23 Bank address bus
1.8-V HSTL Class I AU21 Input clock
1.8-V HSTL Class I AT21 Input clock
1.8-V HSTL Class I AN23 Chip select
1.8-V HSTL Class I AR25 Data clock
1.8-V HSTL Class I AP25 Data clock
1.8-V HSTL Class I AB25 Data mask
Stratix V GS Device
Pin Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–54 Chapter 2: Board Components
Memory
Table 2–54. RLDRAM II Pin Assignments, Signal Names and Functions (Part 2 of 2)
Board Reference
(U20)
B10
C10
E10
F10
B3
C3
D3
E3
F3
N10
P10
R10
T10
U10
N3
P3
T3
U3
D10
R3
D11
R2
F12
L1
M1
V2
Schematic Signal Name I/O Standard
RLDC_DQ0
RLDC_DQ1
RLDC_DQ2
RLDC_DQ3
RLDC_DQ4
RLDC_DQ5
RLDC_DQ6
RLDC_DQ7
RLDC_DQ8
RLDC_DQ9
RLDC_DQ10
RLDC_DQ11
RLDC_DQ12
RLDC_DQ13
RLDC_DQ14
RLDC_DQ15
RLDC_DQ16
RLDC_DQ17
RLDC_QK_N0
RLDC_QK_N1
RLDC_QK_P0
RLDC_QK_P1
RLDC_QVLD
RLDC_REFN
RLDC_WEN
RLDC_ZQ
1.8-V HSTL Class I AW26 Write data
1.8-V HSTL Class I AN27 Write data
1.8-V HSTL Class I AN26 Write data
1.8-V HSTL Class I AM26 Write data
1.8-V HSTL Class I AV26 Write data
1.8-V HSTL Class I AU26 Write data
1.8-V HSTL Class I AU27 Write data
1.8-V HSTL Class I AT26 Write data
1.8-V HSTL Class I AT27 Write data
1.8-V HSTL Class I AC25 Write data
1.8-V HSTL Class I AC26 Write data
1.8-V HSTL Class I AD26 Write data
1.8-V HSTL Class I AE26 Write data
1.8-V HSTL Class I AF26 Write data
1.8-V HSTL Class I AA25 Write data
1.8-V HSTL Class I AG26 Write data
1.8-V HSTL Class I AG25 Write data
1.8-V HSTL Class I AH25 Write data
1.8-V HSTL Class I AR27 Output data clock
1.8-V HSTL Class I AK26 Output data clock
1.8-V HSTL Class I AP27 Output data clock
1.8-V HSTL Class I AJ26 Output data clock
1.8-V HSTL Class I AL26 Data valid
1.8-V HSTL Class I AM22 Reference command
1.8-V HSTL Class I AN22 Write enable
1.8-V HSTL Class I — Output impedance control
Stratix V GS Device
Pin Number
Description
Tab le 2– 55 lists the RLDRAM II component reference and manufacturing information.
Table 2–55. RLDRAM II Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U20 533 MHz CIO RLDRAM II Micron MT49H32M18BM-18 www.micron.com
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–55
Memory
Flash
The development board has two 512-Mb CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, test application
data, and user code space.
Each interface has a 16-bit data bus and the two devices combined allow for x32 FPP
configuration. This device is part of the shared flash and MAX (FM) bus, which
connects to the flash memory and MAX V CPLD System Controller.
Each 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps per device. The write performance is 270 µs for a single
word and 310 µs for a 32-word buffer. The erase time is 800 ms for a 128 K parameter
block.
Tab le 2– 56 lists the flash pin assignments, signal names, and functions.
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference
(U10, U11)
B8
B6
H8
G1
A8
C8
C7
B7
A7
D8
D7
C5
B5
A5
C4
D3
C3
B3
A3
C2
A2
D2
D1
C1
B1
A1
Schematic Signal
Name
FM_A26
FM_A25
FM_A24
FM_A23
FM_A22
FM_A21
FM_A20
FM_A19
FM_A18
FM_A17
FM_A16
FM_A15
FM_A14
FM_A13
FM_A12
FM_A11
FM_A10
FM_A9
FM_A8
FM_A7
FM_A6
FM_A5
FM_A4
FM_A3
FM_A2
FM_A1
I/O Standard
1.8-V AJ17 Address bus (for pin compatible 1 Gb devices)
1.8-V AP21 Address bus
1.8-V AH16 Address bus
1.8-V AE17 Address bus
1.8-V AE16 Address bus
1.8-V AK17 Address bus
1.8-V AL17 Address bus
1.8-V AT6 Address bus
1.8-V AU6 Address bus
1.8-V AV17 Address bus
1.8-V AW17 Address bus
1.8-V AV16 Address bus
1.8-V AW16 Address bus
1.8-V AU17 Address bus
1.8-V AU16 Address bus
1.8-V AR17 Address bus
1.8-V AT17 Address bus
1.8-V AN16 Address bus
1.8-V AP16 Address bus
1.8-V AM17 Address bus
1.8-V AN17 Address bus
1.8-V AG16 Address bus
1.8-V AF16 Address bus
1.8-V AL16 Address bus
1.8-V AM16 Address bus
1.8-V AV19 Address bus
Stratix V GS Device
Pin Number
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–56 Chapter 2: Board Components
Memory
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference
(U10, U11)
U11.E7
U11.G7
U11.H5
U11.F5
U11.F4
U11.F3
U11.E3
U11.E1
U11.H7
U11.G6
U11.G5
U11.E5
U11.E4
U11.G3
U11.E2
U11.F2
U10.E7
U10.G7
U10.H5
U10.F5
U10.F4
U10.F3
U10.E3
U10.E1
U10.H7
U10.G6
U10.G5
U10.E5
U10.E4
U10.G3
U10.E2
U10.F2
E6
U10.B4
U11.B4
F8
F6
U10.F7
Schematic Signal
Name
FM_D31
FM_D30
FM_D29
FM_D28
FM_D27
FM_D26
FM_D25
FM_D24
FM_D23
FM_D22
FM_D21
FM_D20
FM_D19
FM_D18
FM_D17
FM_D16
FM_D15
FM_D14
FM_D13
FM_D12
FM_D11
FM_D10
FM_D9
FM_D8
FM_D7
FM_D6
FM_D5
FM_D4
FM_D3
FM_D2
FM_D1
FM_D0
FLASH_CLK
FLASH_CEn0
FLASH_CEn1
FLASH_OEn
FLASH_ADVn
FLASH_RDYBSYn0
I/O Standard
Stratix V GS Device
Pin Number
1.8-V AT24 Data bus
1.8-V AV25 Data bus
1.8-V AW25 Data bus
1.8-V AL25 Data bus
1.8-V AL24 Data bus
1.8-V AJ24 Data bus
1.8-V AK24 Data bus
1.8-V AH24 Data bus
1.8-V AG24 Data bus
1.8-V AD24 Data bus
1.8-V AE24 Data bus
1.8-V AE25 Data bus
1.8-V AF25 Data bus
1.8-V AB24 Data bus
1.8-V AC24 Data bus
1.8-V AN24 Data bus
1.8-V AM25 Data bus
1.8-V AN25 Data bus
1.8-V AN25 Data bus
1.8-V AL20 Data bus
1.8-V AL21 Data bus
1.8-V AJ20 Data bus
1.8-V AJ21 Data bus
1.8-V AK21 Data bus
1.8-V AL22 Data bus
1.8-V AE20 Data bus
1.8-V AE21 Data bus
1.8-V AH21 Data bus
1.8-V AG21 Data bus
1.8-V AD20 Data bus
1.8-V AD21 Data bus
1.8-V AN21 Data bus
1.8-V AM8 Clock
1.8-V AV14 Chip enable
1.8-V AW13 Chip enable
1.8-V AJ7 Output enable
1.8-V AP7 Address valid
1.8-V AL6 Ready
Description
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–57
Power Supply
Table 2–56. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board
Reference
(U10, U11)
U11.F7
D4
G8
C6
Schematic Signal
Name
FLASH_RDYBSYn1
FLASH_RESETn
FLASH_WEn
FLASH_WPn
I/O Standard
1.8-V AN7 Ready
1.8-V AJ6 Reset
1.8-V AN8 Write enable
— — Write protect
Stratix V GS Device
Pin Number
Description
Tab le 2– 57 lists the flash memory component reference and manufacturing
information.
Table 2–57. Flash Memory Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U10, U11 512-Mbit synchronous flash Numonyx PC28F512P30BF www.numonyx.com
Manufacturing
Part Number
Manufacturer
Power Supply
The development board’s power is provided through a laptop style DC power input
or through the PCI Express edge connector. The DC voltage is stepped down to the
various power rails used by the components on the board and installed into the
HSMC connectors.
Website
An on-board multi-channel analog-to-digital converter (ADC) measures both the
voltage and current for several specific board rails. The power utilization is displayed
in a GUI that graphs power consumption versus time.
Tab le 2– 58 lists the maximum allowed draws of the power input.
Table 2–58. Power Input Maximum Allowed Draws
Source Voltage (V) Current (A) Maximum Voltage (V)
25 W PCI Express edge connector
75 W PCI Express edge connector
Laptop Supply—DC input 19.0 6.30 120.0
Power Distribution System
The power tree minimizes power board space for PCI Express board requirements
and gives the maximum power under 5.5 A for a 12 V PCI Express input and 3.0 A for
a 3.3 V PCI Express rail. The switching regulators are assumed to have 85% of
efficiency. Regulator inefficiencies and sharing are reflected in the currents shown,
which are conservative absolute maximum levels.
3.3 — —
12.0 — —
3.3 3.00 9.0
12.0 5.50 66.0
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–58 Chapter 2: Board Components
R
SENSE
R
SENSE
BEAD
R
SENSE
R
SENSE
R
SENSE
R
SENSE
R
SENSE
R
SENSE
BEAD
LTC3880
Switching
Regulator
(+/- 3 %)
12V
2.802A
1.279A
3.3V
3.3V
LT3083 3.0A
LDO
LT3022 1.0A
LDO
LT3029
Dual 0.5A
LDO
LTC3025-1
0.5A
Linear Regulator
LTC3025-1
0.5A
Linear Regulator
LT3009 20mA
LDO
3.3V -- PCI Express Motherboard
3.0A Maximum
DC INPUT
12V -- PCI Express Motherboard
5.5A Maximum
LTC3855
Dual
Channel
Controller
12V
3.3V
1.508A
5.0V
LTM4614
Dual 4A
Switching
Regulator
(+/- 2%)
LTM4628
Dual 8A
Switching
Regulator
(+/- 3%)
LTM4628
Dual 8A
Switching
Regulator
(+/- 3%)
1.080A
1.226A
3 x
LT3080-1
1.1A LDO
Power Sequencing:
VCC/VCCHIP/VCCHSSI
VCCPD/VCCPGM/VCCAUX/VCCA_FPLL
VCCIO
VCCR_GXB/VCCT_GXB
VCCA_GXB
VCCPT/VCCH_GXB/VCCD_FPLL
5.0V
S5_VCCR_GXB
VCCR_GXB
S5_VCCT_GXB
VCCT_GXB
S5_VCCINT
VCC, VCCHIP, VCCHSSI
S5_VCCIO_HSMB
VCCIO_HSMB
S5_VCCIO_2.5V
FPGA VCCIO1: 2.5 V Banks
S5_VCCIO_1.5V
1.5V_DDR3
VCCIO_1.8V
VCC_RLD_QDR,
VDDQ_RLD_QDR
S5_VCCA_GXB
VCCA_GXB
S5_VCCA_FPLL
VCCA_FPLL, VCCAUX
S5_VCCPD_PGM
VCCPD, VCCPGM
1.5V
VCCD_FPLL,
VCCH_GXB, VCCPT
5.0V
Character LCD, MAX3378,
Regulator Bias
1.5V
DDR3 VDD, EZ_USB
ADC_MONITOR
LT2418
12V
HSMA, HSMB, Fan
2.5V
Flash VDDQ, ENET VDD,
EPM2210 VCCIO2, RLD VEXT,
NB6L11S, 6 Oscillators
1.0V
ENET_DVDD
DDR3_VTT
QDR_RLD_VTT
1.8V
Flash, QDR_VDD, RLD_VDD,
EPM2210, EPCQ
3.3V
HSMA, HSMB, Temp. sense,
ICS8543, CLK Buffer, EZ_USB,
QSFP, SDI, Oscillator
0.018A
5.37V
0.010A
12V
2.095A
3.0V
0.296A
1.0V
0.253A
0.85V
27.726A
0.337A
This regulator varies from
1.2V/1.5V/1.8V/2.5V
0.9V, 27.726A
3.3V, 0.296A
1.5V
0.426A
0.299A
2.5V
1.8V
0.601A
2.5V
1.279A
1.8V
3.834A
3.3V
7.001A
0.9V
0.10A
0.75V
0.050A
1.5V
2.374A
2.5V
0.163A
2.5V
1.345A
0.010A
12V
2.455A
12V
3.3V
0.337A
3.3V
0.253A
2.599A
3.3V
0.725A
0.601A
ideal
diode mux
9.037A
12V
3.195A
3.3V
9.247A
ideal
diode mux
19V
LT3021
0.5A LDO
(+/ -3 %)
5.0V
0.296A
1.499A
1.0V
2.395A
5.0V
2.5V
1.2V, 2.395A
1.6V, 1.499A
3.934A
1.8V
2.193A
1.675A
1.741A
2.424A
7.001A
Green text indicates
the power requirements
for Stratix V ES devices.
.
1.5V
5.0V
2.03A
TPS51200
TPS51200
1.5V
DDR3_VREF
QDR/
RLD _VREF
3.3V
1
1
2
2
2
3
3
3
3
3
5
5
6
6
4
4
4
Power Supply
Figure 2–10 shows the power distribution system on the development board.
Figure 2–10. Power Distribution System
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–59
SCK
DSI
DSO
CSn
8 Ch.
Power Supply Load 0-7
Supply
0-7
R
SENSE
MAX V
CPLD
Stratix V GS
FPGA
LTC2418
EPM570G
USB
PHY
To User PC
Power GUI
JTAG Chain
SPI Bus
On-Board
USB-Blaster II
Feedback
14-pin
2x16
Character LCD
Power Supply
Power Measurement
There are 16 power supply rails which have on-board voltage, current, and wattage
sense capabilities. These 8-channel differential 24-bit ADC devices and rails are split
from the primary supply plane by a low-value sense resistor for the ADC to measure
voltage and current. A serial peripheral interface (SPI) bus connects these ADC
devices to the MAX V CPLD System Controller as well as the Stratix V GS.
Figure 2–11 shows the block diagram for the power measurement circuitry.
Figure 2–11. Power Measurement Circuit
Tab le 2– 59 lists the targeted rails. The schematic signal name specifies the name of the
rail being measured and the device pin specifies the devices attached to the rail. If no
subnet is named, the power is the total output power for that voltage.
Table 2–59. Power Rail Measurements Based on the GUI Selection (Part 1 of 2)
Number Schematic Signal Name Voltage (V) Device Pin Description
VCCIO_7A I/O supply bank 7A
S5_VCCIO_HSMB
0
1.2/1.5/1.8/2.5
VCCIO_7C I/O supply bank 7C (HSMC Port B)
VCCIO_7D I/O supply bank 7D (HSMC Port B)
1
S5_VCC_GXB
1.1
VCCR_GXB XCVR analog receive
VCCT_GXB XCVR analog transmit
VCCIO_3C I/O supply bank 3C (RLDRAM II)
VCCIO_3D I/O supply bank 3D (RLDRAM II)
2
S5_VCCIO_1.8V
1.8
VCCIO_4A I/O supply bank 4A
VCCIO_4C I/O supply bank 4C (QDR II/+)
VCCIO_4D I/O supply bank 4D (QDR II/+)
VCCPD I/O pre-drivers
3
S5_VCCPD_PGM
4
S5_VCCINT
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
2.5
0.90
VCCPGM Configuration I/O
VCCAUX Programmable power tech auxiliary
VCCA_FPLL PLL analog power
VCC FPGA core and periphery power
VCCHIP PCIe Hard IP digital power
VCCHSSI PCS power
Reference Manual
2–60 Chapter 2: Board Components
Temperature Sense
Table 2–59. Power Rail Measurements Based on the GUI Selection (Part 2 of 2)
Number Schematic Signal Name Voltage (V) Device Pin Description
VCCD_FPLL PLL digital power
5
S5_VCC_1p5
6
S5_VCCIO_2.5V
7
S5_VCCIO_1.5V
8
S5_VCCA_GXB
1.5
2.5
1.5
3.3 VCCA_GXB XCVR TX driver, RX receiver, CDR
VCCH_GXB XCVR block level transmit buffers
VCCPT Programmable power tech auxiliary
VCCIO_3A I/O supply bank 3A
VCCIO_3B I/O supply bank 3B
VCCIO_4B I/O supply bank 4B (HSMC Port A)
VCCIO_7B I/O supply bank 7B (HSMC Port A)
VCCIO_8A I/O supply bank 8A (DDR3 RZQ)
VCCIO_8B I/O supply bank 8B (DDR3)
VCCIO_8C I/O supply bank 8C (DDR3)
VCCIO_8D I/O supply bank 8D (DDR3)
Tab le 2– 60 lists the power measurement ADC component references and
manufacturing information.
Table 2–60. Power Measurement ADC Component References and Manufacturing Information
Board Reference Description Manufacturer
U52 8-channel differential 24-bit ADC Linear Technology LTC2418CGN#PBF www.linear.com
U1 1-channel differential 14-bit ADC Linear Technology LTC2990IMS#PBF www.linear.com
Manufacturing
Part Number
Temperature Sense
Temperature monitoring for the Stratix V GS die is achieved with a MAX1619
temperature sense device. The MAX1619 device connects to the MAX V CPLD
EPM2210 System Controller and the Stratix V GS device by a 2-wire SMB interface.
The MAX1619 device is located at address 0x1. This bus is also routed to a single
voltage and power monitor chip for the 12-V power rail at address 0x2.
The
OVERTEMPn
sense device based on a programmable threshold temperature. The
is driven to the MAX V System Controller, which controls the
MAX V System Controller can control fan speed is based on a register setting and can
also override the MAX1619 device. For more information on this control, refer to the
MAX V System Controller source code found in the development board installation
directory <install dir>\kits\stratixVGS_5sgsmd5kf40_dsp\examples\max5.
f For more information on the development board installation directory, refer to the
DSP Development Kit, Stratix V Edition User Guide.
and
TSENSE_ALERTn
signals are driven by the MAX1619 temperature
Manufacturer
OVERTEMPn
OVERTEMPn
Website
signal
signal. The
The remote sense routes to the FPGA diode pins to measure the voltage drop. For
very accurate temperature readings, the I/O adjacent to the FPGA diode sense pins
must be halted.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–61
Statement of China-RoHS Compliance
Tab le 2– 61 lists the temperature sense interface pin assignments, signal names, and
functions.
Table 2–61. Temperature Sense Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
(U45)
14
12
11
9
3
4
Schematic Signal
Name
SENSE_SMB_CLK
SENSE_SMB_DATA
TSENSE_ALERTn
OVERTEMPn
TEMPDIODE_P
TEMPDIODE_N
I/O
Standard
2.5-V
MAX V CPLD
System Controller
Pin Number
Stratix V GS
Device
Pin Number
D8 — SMB clock
A7 — SMB data
B5 —
Programmable alert for over
temperature
C8 — Fan enable
— R6 Temperature sense diode input
— P5 Temperature sense diode input
Tab le 2– 62 lists the temperature sense component reference and manufacturing
information.
Table 2–62. Temperature Sense Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U45
Temperature sense, remote and
local, programmable alert.
Maxim MAX1619MEE+T www.maxim-ic.com
Manufacturing
Part Number
Description
Manufacturer
Website
Statement of China-RoHS Compliance
Tab le 2– 63 lists hazardous substances included with the kit.
Table 2–63. Table of Hazardous Substances’ Name and Concentration Notes
Hexavalent
Chromium
(Cr6+)
Part Name
DSP Development Kit, Stratix V
Edition
Lead
(Pb)
Cadmium
(Cd)
X* 0 0 0 0 0
19 V power supply 0 0 0 0 0 0
Type USB-A to micro USB-B cable 0 0 0 0 0 0
User guide 0 0 0 0 0 0
Notes to Table 2–63:
(1) 0 indicates that the concentration of the hazardous substance in all homogeneous materials in the parts is below the relevant threshold of the
SJ/T11363-2006 standard.
(2) X* indicates that the concentration of the hazardous substance of at least one of all homogeneous materials in the parts is above the relevant
threshold of the SJ/T11363-2006 standard, but it is exempted by EU RoHS.
(1), (2)
Mercury
(Hg)
Polybrominated
biphenyls (PBB)
Polybrominated
diphenyl Ethers
(PBDE)
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–62 Chapter 2: Board Components
Statement of China-RoHS Compliance
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
This appendix catalogs revisions to the DSP Development Kit, Stratix V Edition.
Tab le A– 1 lists the versions of all releases of the DSP Development Kit, Stratix V
Edition.
Table A–1. DSP Development Kit, Stratix V Edition Revision History
Version Release Date Description
Engineering silicon July 2012 Initial release.
A. Board Revision History
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
A–2 Appendix A: Board Revision History
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
This chapter provides additional information about the document and Altera.
Document Revision History
The following table shows the revision history for this document.
Date Version Changes
July 2012 1.0 Initial release.
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the
following table.
Additional Information
Contact
Technical support Website www.altera.com/support
Technical training
Product literature Website www.altera.com/literature
Nontechnical support (general) Email nacomp@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
(1)
(software licensing) Email authorization@altera.com
Contact Method Address
Website www.altera.com/training
Email custrain@altera.com
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue Meaning
Bold Type with Initial Capital
Letters
bold type
Italic Type with Initial Capital Letters Indicate document titles. For example, Stratix IV Design Guidelines.
italic type
Initial Capital Letters
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Info–2 Additional InformationAdditional Information
Typographic Conventions
Visual Cue Meaning
“Subheading Title”
Quotation marks indicate references to sections in a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Indicates signal, port, register, bit, block, and primitive names. For example,
tdi
, and
input
. The suffix n denotes an active-low signal. For example,
resetn
data1
.
,
Indicates command line commands and anything that must be typed exactly as it
Courier type
appears. For example,
c:\qdesigns\tutorial\chiptrip.gdf
.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword
TRI
example,
).
SUBDESIGN
), and logic function names (for
r An angled arrow instructs you to press the Enter key.
1., 2., 3., and
a., b., c., and so on
■ ■ ■ Bullets indicate a list of items when the sequence of the items is not important.
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
1 The hand points to information that requires special attention.
h The question mark directs you to a software help system with related information.
f The feet direct you to another document or website with related information.
m The multimedia icon directs you to a related multimedia presentation.
c
w
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
The feedback icon allows you to submit feedback to Altera about the document.
Methods for collecting feedback vary as appropriate for each document.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
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