Altera DSP Development Kit, Stratix V Edition User Manual
DSP Development Kit, Stratix V Edition
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
MNL-01070-1.0
Feedback Subscribe
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Board Components
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Featured Device: Stratix V GS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
MAX V CPLD System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming over On-Board USB-Blaster II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19
JTAG Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
PCI Express Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Load Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Memory Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
General User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28
HSMC User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–34
High-Speed Mezzanine Cards (HSMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35
SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43
40G QSFP Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46
QDRII+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–50
RLDRAM II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–53
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–55
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
iv Contents
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–57
Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–59
Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–60
Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–61
Appendix A. Board Revision History
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
This document describes the hardware features of the DSP Development Kit,
®
Stratix
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The DSP Development Kit, Stratix V Edition provides a hardware platform for
developing and prototyping high-performance and high-bandwidth application
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of Stratix V DSP designs.
1. Overview
V Edition, including the detailed pin-out and component reference
Two High-Speed Mezzanine Card (HSMC) connectors are available to add additional
functionality via a variety of HSMC cards available from both Altera
®
and various
partners.
f To see a list of the latest HSMC cards available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the PCI Express hard IP
implementation, partial reconfiguration, and programmable power technology
ensure that designs implemented in the Stratix V DSPs operate faster, with lower
power than in previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Stratix V device family, refer to the Stratix V Device Handbook.
■ PCI Express hard IP implementation, refer to the Stratix V Hard IP for PCI Express
User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
1–2 Chapter 1: Overview
Board Component Blocks
Board Component Blocks
The board features the following major component blocks:
■ Altera Stratix V FPGA (5SGSMD5K2F40C2N) in the 1517-pin FineLine BGA
package
■ 457,000 LEs
■ 172,600 adaptive logic modules (ALMs)
■ 39-Mbits embedded memory
■ 36 transceivers (14.1 Gbps)
■ 174 full-duplex LVDS channels
■ 24 phase locked loops (PLLs)
■ 3,180 18x18-bit multipliers
■ 900-mV core voltage
■ 864 user I/Os
■ 1 PCI Express hard IP blocks
■ MAX
®
V CPLD (5M2210ZF256C4) System Controller in the 256-pin FineLine BGA
package
■ 2,210 LEs
■ 203 user I/Os
■ 1.8-V core voltage
■ FPGA configuration circuitry
■ MAX
II CPLD (EPM570GM100) and Flash Fast Passive Parallel (FPP)
configuration
■ On-Board USB-Blaster
TM
II for use with the Quartus® II Programmer, Nios®II
Software Build Tools, and System Console.
■ On-Board clocking circuitry
■ 50-MHz, 100-MHz, 125-MHz, and programmable oscillators
■ SMA connector for clock input (LVPECL)
■ Memory devices
■ 1152-Mbyte DDR3 SDRAM with a 72-bit data bus
■ 72-Mbyte CIO RLDRAM II with a 18-bit data bus
■ 4.5-Mbyte QDRII+ SRAM with a 18-bit data bus (footprint is compatible for
9-Mbyte QDRII with a 18-bit data bus)
■ Two 512-Mbyte synchronous flash with a 16-bit data bus
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 1: Overview 1–3
Board Component Blocks
■ Communication ports
■ PCI Express (PCIe) x8 edge connector
■ Two H S MC po rt s
■ One universal HSMC port A
■ One DQS-type HSMC port B
■ SMB for SDI input and output
■ QSFP
■ USB 2.0
■ Gigabit Ethernet
■ LCD header
■ General user I/O
■ 16 user LEDs
■ Two-line character LCD display
■ Six configuration status LED
■ One transmit/receive LED (TX/RX) per HSMC interface
■ Five PCI Express LEDs
■ Four Ethernet LEDs
■ Push buttons and DIP switches
■ One CPU reset push button
■ Three general user push buttons
■ Two configuration push buttons
■ Eight user DIP switches
■ Four MAX
V control DIP switches
■ Power
■ 19-V (laptop) DC input
■ PCI Express edge connector power
■ On-Board power measurement circuitry
■ System monitoring
■ Power—voltage, current, wattage
■ Temperature—FPGA die, local board
■ Mechanical
■ PCI Express short form factor
■ PCI Express chassis or bench-top operation
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
1–4 Chapter 1: Overview
Port A
Port B
1152 MB
DDR3
4.5 MB
QDRII+ SRAM
Push Buttons
and Switches
LED
CPLD
64 MB
Flash
64 MB
Flash
x8 Edge
Programmable
Oscillators
50 MHz, 100 MHz,
148 MHz, 156 MHz
QSFP
REFCLK
SMA IN
GigE
PHY
SDI
TX/TX
On-Board
USB- Blaster II
and USB Interface
x4 XCVR
x1 (LVPECL)
x1
x1 XCVR
x72
x18
72 MB CIO
RLDRAM II
x18
EPCQ
x4
x4
x8
x16
x4
XCVR x8
x32 Config
x32
x80
CLKIN x3
CLKOUT x3
XCVR x8
x80
CLKIN x3
CLKOUT x3
XCVR x6
ADDR
JTAG Chain
5SGSMD5K2F40C2N
Micro-USB
2.0
x19 USB Interface
LVDS/Single-Ended
DQS/Single-Ended
x16
x16
Development Board Block Diagram
Development Board Block Diagram
Figure 1–1 shows the block diagram of the DSP Development Kit, Stratix V Edition.
Figure 1–1. DSP Development Kit, Stratix V Edition Block Diagram
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
2. Board Components
This chapter introduces all the important components on the DSP Development Kit,
Stratix V Edition. Figure 2–1 illustrates major component locations and Ta bl e 2– 1
provides a brief description of all features of the board.
1 A complete set of schematics, a physical layout database, and GERBER files for the
development board reside in the DSP Development Kit, Stratix V Edition documents
directory.
f For information about powering up the board and installing the demo software, refer
to the DSP Development Kit, Stratix V Edition User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Stratix V GS” on page 2–5
■ “MAX V CPLD System Controller” on page 2–6
■ “Configuration, Status, and Setup Elements” on page 2–12
■ “Clock Circuitry” on page 2–23
■ “General User Input/Output” on page 2–26
■ “Components and Interfaces” on page 2–31
■ “Memory” on page 2–46
■ “Power Supply” on page 2–57
■ “Statement of China-RoHS Compliance” on page 2–61
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–2 Chapter 2: Board Components
HSMC Port B (J2)
Power Switch (SW2)
DC Input Jack (J4)
QDRII+ x18 (U5)
DDR3 Memory
x8 (U12)
x16 (U17, U21, U23, U28)
JTAG Header (J10)
Clock Input
SMA Connector
(J13, J14)
CPU Reset Push Button (S4)
MAX V CPLD
System Controller (U4)
Character LCD (J15)
PCI Express
Edge Connector
(J18)
RLDRAM II x18
Memory
(U20)
Fan Power Header
(J11)
Transceiver TX SMA
Connectors (J3, J6)
Flash x32 Memory
(U10, U11)
Load, Error, and Configuration
Done LEDs (D15-D17)
HSMC Port A (J1)
SDI Video Port
(J16, J17)
Gigabit Ethernet Port (J9)
On-Board USB-Blaster II
Connector (J7)
Program Load and Program Select Push Buttons (S2, S3)
MAX V Reset Push Button (S1)
Stratix V GS FPGA (U15)
General User Push Buttons (S5, S6, S7)
User DIP Switch (SW1)
Program Select LEDs (D4-D6)
40G QSFP Connector
and Cage Assembly (J12)
Board Overview
Board Overview
This section provides an overview of the DSP Development Kit, Stratix V Edition,
including an annotated board image and component descriptions. Figure 2–1
provides an overview of the development board features.
Figure 2–1. Overview of the DSP Development Kit, Stratix V Edition Features
Tab le 2– 1 describes the components and lists their corresponding board references.
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 1 of 4)
Board Reference Type Description
Featured Devices
U15 FPGA 5SGSMD5K2F40C2N, 1517-pin BGA.
U4 CPLD 5M2210ZF256C4, 256-pin BGA.
Configuration, Status, and Setup Elements
J10 JTAG header
J7 On-Board USB-Blaster II Micro-USB 2.0 connector for programming and debugging the FPGA.
SW3 JTAG DIP switch
SW4 FPGA mode select DIP switch Sets the Stratix V
SW5 Board settings DIP switch
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Provides access to the JTAG chain by using an external USB-Blaster
cable (disables the on-board USB-Blaster II).
Enables and disables devices in the JTAG chain. This switch is located
on the back of the board.
MSEL[4:0]
Controls the MAX V CPLD System Controller functions such as clock
select, clock enable, factory or user design load from flash and
FACTORY
signal command sent at power up. This switch is located at
the bottom of the board.
pins.
Chapter 2: Board Components 2–3
Board Overview
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 2 of 4)
Board Reference Type Description
SW6 PCI Express DIP switch
Controls the PCI Express lane width by connecting
together on the PCI Express edge connector. This switch is located at
prsnt
pins
the back of the board.
S3 Program select push button
S2 Program load push button
Toggles the program LEDs which selects the program image that loads
from flash memory to the FPGA.
Configures the FPGA from flash memory image based on the program
LEDs.
Illuminates to show the LED sequence that determines which flash
D4, D5, D6 Program LEDs
memory image loads to the FPGA when you press the program load
push button.
D17 Configuration done LED Illuminates when the FPGA is configured.
D15 Load LED Illuminates during FPGA configuration.
D16 Error LED Illuminates when the FPGA configuration from flash fails.
D24 Power LED Illuminates when 5-V power is present.
Indicate the transmit or receive activity of the System Console USB
D25, D26 System Console TX/RX LEDs
interface. The TX and RX LEDs would flicker if the link is in use and
active. The LEDs are either off when not in use or on when in use but
idle.
Indicate the transmit or receive activity of the JTAG chain. The TX and
D27, D28 JTAG TX/RX LEDs
RX LEDs would flicker if the link is in use and active. The LEDs are
either off when not in use or on when in use but idle.
D29, D30, D31,
D32
Ethernet LEDs Indicate the connection speed as well as transmit or receive activity.
D3, D13 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D1 HSMC port A Present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D11, D14 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.
D2 HSMC port B Present LED Illuminates when a daughtercard is plugged into the HSMC port B.
D33, D34 PCI Express Gen2/Gen3 LED
D35, D36, D37 PCI Express Link LEDs
You can configure these LEDs to illuminate when PCI Express is in
Gen2 or Gen3 mode.
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
X1 125 M oscillator
U38 Quad-output oscillator
U46 Quad-output oscillator
X6 148.5 M oscillator
125.000-MHz crystal oscillator for Gigabit Ethernet, Serial RapidIO™
(SRIO), or PCI Express.
Programmable oscillator with default frequencies of 100 MHz,
156.25 MHz, 625 MHz, and 270 MHz.
Programmable oscillator with default frequencies of 125 MHz,
644.53125 MHz, 282.5 MHz, and 125 MHz.
148.500-MHz voltage controlled crystal oscillator for SDI video. This
oscillator is programmable to any frequency between 20-810 MHz.
100.000-MHz (programmable to any frequency between 20–810 MHz)
X4 100 M oscillator
crystal oscillator for PCI Express or general use such as memories.
Multiplex with
CLKIN_SMA_P
or
CLKIN_SMA_N
based on CLK_SEL
switch value.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–4 Chapter 2: Board Components
Board Overview
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 3 of 4)
Board Reference Type Description
X3 50 M oscillator 50.000-MHz crystal oscillator for general purpose logic.
J13, J14 Clock input SMAs
Drives LVPECL-compatible clock inputs into the clock multiplexer
buffer.
U4 100 M oscillator 100-MHz crystal oscillator for the MAX V CPLD System Controller.
General User Input and Output
D7-D10,
D18-D21
User LEDs
Eight bi-color LEDs (green and red) for 16 user LEDs. Illuminates when
driven low.
SW1 User DIP switch Octal user DIP switches. When the switch is ON, a logic 0 is selected.
S1 MAX V reset push button The default reset for the MAX V CPLD System Controller.
S4 CPU reset push button The default reset for the FPGA logic.
S5, S6, S7 General user push buttons Three user push buttons. Driven low when pressed.
Memory Devices
U12, U17, U21,
U23, U28
DDR3 x72
A 1152-Mbyte DDR3 SDRAM with a 72-bit data bus. The 72-bit data
bus consists of four x16 devices and one x8 device with a single
address or command bus.
A 4.5-Mbyte QDRII+ SRAM with a 18-bit data bus. The device has a
U5 QDRII+ x18
separate 18-bit read and 18-bit write port with DDR signalling at up to
550 MHz.
U20 RLDRAM II x18
A 72-Mbyte CIO RLDRAM II with a 18-bit data bus. The 18-bit data bus
consists of a single x18 device with a single address or command bus.
Two 512-Mbyte synchronous flash devices with a 16-bit data buses for
U10, U11 Flash x32
non-volatile memory. The board supports two flash devices of 16-bit
interface each, which combine to allow for 1-Gbyte synchronous flash
with a 32-bit data bus.
Communication Ports
J18 PCI Express edge connector
Made of gold-plated edge fingers for up to ×8 signaling in either Gen1,
Gen2, or Gen3 mode.
J12 QSFP connector Provides four transceiver channels for a 40G QSFP module.
J1 HSMC port A
J2 HSMC port B
Provides eight transceiver channels and 84 CMOS or 17 LVDS
channels per the HSMC specification.
Provides four transceiver channels and 84 CMOS or a DQ/DQS
interface.
RJ-45 connector which provides a 10/100/1000 Ethernet connection
J9 Gigabit Ethernet port
via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed
Ethernet MAC MegaCore function in SGMII mode.
Video and Display Ports
Two 75-Ω system management bus (SMB) connectors which provide a
J16, J17 SDI video port
full-duplex SDI interface through a LMH0303 driver and LMH0384
cable equalizer.
J15 Character LCD header
A single 14-pin 0.1" pitch dual-row header which interfaces to the 16
character × 2 line LCD module.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–5
Featured Device: Stratix V GS
Table 2–1. DSP Development Kit, Stratix V Edition Components (Part 4 of 4)
Board Reference Type Description
Power Supply
J18 PCI Express edge connector
J4 DC input jack Accepts a 19-V DC power supply.
SW2 Power switch
Interfaces to a PCI Express root port such as an appropriate PC
motherboard.
Switch to power on or off the board when power is supplied from the
DC input jack.
Featured Device: Stratix V GS
The Stratix V GS development board features the Stratix V GS 5SGSMD5K2F40C2N
device (U15) in a 1517-pin FineLine BGA package.
f For more information about the Stratix V device family, refer to the Stratix V Device
Handbook.
Tab le 2– 2 describes the features of the Stratix V GS 5SGSMD5K2F40C2N device.
Table 2–2. Stratix V GS 5SGSMD5K2F40C2N Features
ALMs
172,600 457,000 690,400 2,014 5.27 3,180 24 36
Equivalent
LEs
Registers
M20K
Blocks
MLAB
Blocks (Mb)
18-bit × 18-bit
Multipliers
PLLs
Transceiver
Channels
(14.1 Gbps)
Tab le 2– 3 lists the Stratix V GS component reference and manufacturing information.
Table 2–3. Stratix V GS Component Reference and Manufacturing Information
Board
Reference
U15
Description Manufacturer
FPGA, Stratix V GS F1517, 457K
LEs, leadfree
Corporation 5SGSMD5K2F40C2NC2N www.altera.com
Altera
Manufacturing
Part Number
I/O Resources
Tab le 2– 4 lists the Stratix V GS device pin count and usage by function on the
development board.
Table 2–4. Stratix V GS Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
DDR3 1.5-V SSTL 126 1 Diff ×9DQS
RLDRAM II 1.8-V SSTL 57 1 Diff ×3 DQS
QDRII+ SRAM 1.8-V HSTL 67 1 Diff ×2 DQS
MAX V System Controller 1.5-V CMOS 8 —
Flash 1.8-V CMOS 68 —
PCI Express ×8 2.5-V CMOS + XCVR 43 1 REFCLK
Package Type
1517-pin
FineLine BGA
Manufacturer
Website
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–6 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–4. Stratix V GS Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
HSMC Port A 2.5-V CMOS + LVDS + XCVR 118 1 REFCLK
HSMC Port B 2.5-V CMOS + DQS + XCVR 104 1 REFCLK
Gigabit Ethernet 2.5-V CMOS + LVDS 8 —
On-Board USB-Blaster II
1.5-V CMOS 18 —
3.3-V CMOS 1 —
SDI Video 2.5-V CMOS + XCVR 8 1 REFCLK
QSFP 2.5-V CMOS + XCVR 23 1 REFCLK
Buttons 1.8/2.5-V CMOS 4 1 DEV_CLRn
Switches 1.8-V CMOS 8 —
Character LCD 2.5-V CMOS 11 —
LEDs 1.8/2.5-V CMOS 16 —
Clocks or Oscillators 1.8-V CMOS + LVDS 25 9 REFCLK
Device I/O Total:
MAX V CPLD System Controller
The board utilizes the 5M2210ZF256C4 System Controller, an Altera MAX V CPLD,
for the following purposes:
■ FPGA configuration from flash memory
■ Power consumption monitoring
■ Temp e ra tu re m onito ri ng
■ Fan control
■ Control registers for clocks
■ Control registers for remote system update
713
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–7
MAX V CPLD System Controller
Figure 2–2 illustrates the MAX V CPLD System Controller's functionality and external
circuit connections as a block diagram.
Figure 2–2. MAX V CPLD System Controller Block Diagram
MAX V System Controller
PC
On-Board
USB-Blaster II
Power
Measurement
Results
Temperature
Measurement
Results
JTAG Control
Encoder
LTC2418
Controller
LTC2990
Controller
MAX1619
Controller
SLD-HUB
Virtual-JTAG
Decoder
Information
Register
Control
Register
PFL
Si570
Controller
Si571
Controller
Si5538
Controller
FSM BUS
FPGA
Flash
Flash
GPIO
Si570
Programmable
Oscillator
Si571
Oscillator
Si5338
Oscillator
Si5338
Oscillator
Programmable
Programmable
Programmable
Tab le 2– 5 lists the I/O signals present on the MAX V CPLD System Controller. The
signal names and functions are relative to the MAX V device (U4).
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 1 of 6)
Schematic Signal Name
5M2210_JTAG_TMS
CLK125_EN
CLK50_EN
CLK_CONFIG
CLK_ENABLE
CLK_SEL
CLKIN_50
CLOCK_SCL
CLOCK_SDA
CPU_RESETn
FACTORY_LOAD
FACTORY_REQUEST
MAX V CPLD
Pin Number
N4 — 2.5-V MAX V JTAG TMS
B9 — 2.5-V 125 MHz oscillator enable
E9 — 2.5-V 50 MHz oscillator enable
J5 — 2.5-V 100 MHz configuration clock input
A15 — 2.5-V DIP - clock oscillator enable
A13 — 2.5-V DIP - clock select SMA or oscillator
J12 AN6 1.8-V 50 MHz clock input
C9 — 2.5-V Programmable oscillator I2C clock
D9 — 2.5-V Programmable oscillator I2C data
D10 AM34 2.5-V FPGA reset push button
A2 — 2.5-V
R14 — 1.8-V
Stratix V GS
Pin Number
I/O
Standard
Description
DIP - load factory image or user1 image
from flash at power-up
On-Board USB-Blaster II request to send
FACTORY command
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–8 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 2 of 6)
Schematic Signal Name
FACTORY_STATUS
FLASH_ADVn
FLASH_CEn0
FLASH_CEn1
FLASH_CLK
FLASH_OEn
FLASH_RDYBSYN0
FLASH_RDYBSYN1
FLASH_RESETn
FLASH_WEn
FM_A0
FM_A1
FM_A2
FM_A3
FM_A4
FM_A5
FM_A6
FM_A7
FM_A8
FM_A9
FM_A10
FM_A11
FM_A12
FM_A13
FM_A14
FM_A15
FM_A16
FM_A17
FM_A18
FM_A19
FM_A20
FM_A21
FM_A22
FM_A23
FM_A24
FM_A25
FM_D0
FM_D1
MAX V CPLD
Pin Number
N12 — 1.8-V
Stratix V GS
Pin Number
I/O
Standard
Description
On-Board USB-Blaster II FACTORY
command status
N7 AP7 1.8-V FM bus flash memory address valid
R5 AV14 1.8-V FM bus flash memory chip enable 0
M7 AW13 1.8-V FM bus flash memory chip enable 1
R6 AM8 1.8-V FM bus flash memory clock
M6 AJ7 1.8-V FM bus flash memory output enable
T5 AL6 1.8-V FM bus flash memory chip ready 0
R7 AN7 1.8-V FM bus flash memory chip ready 1
P7 AJ6 1.8-V FM bus flash memory reset
N6 AN8 1.8-V FM bus flash memory write enable
E14 AW19 1.8-V FM address bus
C14 AV19 1.8-V FM address bus
C15 AM16 1.8-V FM address bus
E13 AL16 1.8-V FM address bus
E12 AF16 1.8-V FM address bus
D15 AG16 1.8-V FM address bus
F14 AN17 1.8-V FM address bus
D16 AM17 1.8-V FM address bus
F13 AP16 1.8-V FM address bus
E15 AN16 1.8-V FM address bus
E16 AT17 1.8-V FM address bus
F15 AR17 1.8-V FM address bus
G14 AU16 1.8-V FM address bus
F16 AU17 1.8-V FM address bus
G13 AW16 1.8-V FM address bus
G15 AV16 1.8-V FM address bus
G12 AW17 1.8-V FM address bus
G16 AV17 1.8-V FM address bus
H14 AU6 1.8-V FM address bus
H15 AT6 1.8-V FM address bus
H13 AL17 1.8-V FM address bus
H16 AK17 1.8-V FM address bus
J13 AE16 1.8-V FM address bus
R3 AE17 1.8-V FM address bus
P5 AH16 1.8-V FM address bus
T2 AP21 1.8-V FM address bus
J14 AN21 1.8-V FM data bus
J15 AD21 1.8-V FM data bus
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–9
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 3 of 6)
Schematic Signal Name
FM_D2
FM_D3
FM_D4
FM_D5
FM_D6
FM_D7
FM_D8
FM_D9
FM_D10
FM_D11
FM_D12
FM_D13
FM_D14
FM_D15
FM_D16
FM_D17
FM_D18
FM_D19
FM_D20
FM_D21
FM_D22
FM_D23
FM_D24
FM_D25
FM_D26
FM_D27
FM_D28
FM_D29
FM_D30
FM_D31
FPGA_CONF_DONE
FPGA_CONFIG_D0
FPGA_CONFIG_D1
FPGA_CONFIG_D2
FPGA_CONFIG_D3
FPGA_CONFIG_D4
FPGA_CONFIG_D5
FPGA_CONFIG_D6
FPGA_CONFIG_D7
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
K16 AD20 1.8-V FM data bus
K13 AG21 1.8-V FM data bus
K15 AH21 1.8-V FM data bus
K14 AE21 1.8-V FM data bus
L16 AE20 1.8-V FM data bus
L11 AL22 1.8-V FM data bus
L15 AK21 1.8-V FM data bus
L12 AJ21 1.8-V FM data bus
M16 AJ20 1.8-V FM data bus
L13 AL21 1.8-V FM data bus
M15 AL20 1.8-V FM data bus
L14 AN25 1.8-V FM data bus
N16 AM25 1.8-V FM data bus
M13 AP24 1.8-V FM data bus
N15 AN24 1.8-V FM data bus
N14 AC24 1.8-V FM data bus
P15 AB24 1.8-V FM data bus
P14 AF25 1.8-V FM data bus
D13 AE25 1.8-V FM data bus
D14 AE24 1.8-V FM data bus
F11 AD24 1.8-V FM data bus
J16 AG24 1.8-V FM data bus
F12 AH24 1.8-V FM data bus
K12 AK24 1.8-V FM data bus
M14 AJ24 1.8-V FM data bus
N13 AL24 1.8-V FM data bus
R1 AL25 1.8-V FM data bus
P4 AW25 1.8-V FM data bus
N5 AV25 1.8-V FM data bus
P6 AT24 1.8-V FM data bus
K1 AH6 2.5-V FPGA configuration done
D3 AP33 2.5-V FPGA configuration data
C2 AT33 2.5-V FPGA configuration data
C3 AR33 2.5-V FPGA configuration data
E3 AU34 2.5-V FPGA configuration data
D2 AU33 2.5-V FPGA configuration data
E4 AN31 2.5-V FPGA configuration data
D1 AM31 2.5-V FPGA configuration data
E5 AU32 2.5-V FPGA configuration data
Description
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–10 Chapter 2: Board Components
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 4 of 6)
Schematic Signal Name
FPGA_CONFIG_D8
FPGA_CONFIG_D9
FPGA_CONFIG_D10
FPGA_CONFIG_D11
FPGA_CONFIG_D12
FPGA_CONFIG_D13
FPGA_CONFIG_D14
FPGA_CONFIG_D15
FPGA_CONFIG_D16
FPGA_CONFIG_D17
FPGA_CONFIG_D18
FPGA_CONFIG_D19
FPGA_CONFIG_D20
FPGA_CONFIG_D21
FPGA_CONFIG_D22
FPGA_CONFIG_D23
FPGA_CONFIG_D24
FPGA_CONFIG_D25
FPGA_CONFIG_D26
FPGA_CONFIG_D27
FPGA_CONFIG_D28
FPGA_CONFIG_D29
FPGA_CONFIG_D30
FPGA_CONFIG_D31
FPGA_CVP_CONFDONE
FPGA_DCLK
FPGA_nCONFIG
FPGA_nSTATUS
FPGA_PR_DONE
FPGA_PR_ERROR
FPGA_PR_READY
FPGA_PR_REQUEST
HSMA_PRSNTn
HSMB_PRSNTn
M570_CLOCK
M570_PCIE_JTAG_EN
MAX5_BEN0
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
Description
F3 AT32 2.5-V FPGA configuration data
E1 AR31 2.5-V FPGA configuration data
F4 AP31 2.5-V FPGA configuration data
F2 AW34 2.5-V FPGA configuration data
F1 AV34 2.5-V FPGA configuration data
F6 AW31 2.5-V FPGA configuration data
G2 AV31 2.5-V FPGA configuration data
G3 AW32 2.5-V FPGA configuration data
G1 AV32 2.5-V FPGA configuration data
G4 AJ33 2.5-V FPGA configuration data
H2 AH33 2.5-V FPGA configuration data
G5 AL33 2.5-V FPGA configuration data
H3 AK33 2.5-V FPGA configuration data
J1 AK32 2.5-V FPGA configuration data
J2 AJ32 2.5-V FPGA configuration data
H5 AH31 2.5-V FPGA configuration data
K2 AG31 2.5-V FPGA configuration data
K5 AF31 2.5-V FPGA configuration data
L1 AE31 2.5-V FPGA configuration data
L2 AJ30 2.5-V FPGA configuration data
K3 AH30 2.5-V FPGA configuration data
M2 AR30 2.5-V FPGA configuration data
L4 AP30 2.5-V FPGA configuration data
L3 AU30 2.5-V FPGA configuration data
N3 AT29 2.5-V FPGA configuration via protocol done
J3 AC31 2.5-V FPGA configuration clock
N1 AK35 2.5-V FPGA configuration active
J4 AM5 2.5-V FPGA configuration ready status
H1 AT30 2.5-V FPGA partial reconfiguration done
P2 AU29 2.5-V FPGA partial reconfiguration error
E2 AN29 2.5-V FPGA partial reconfiguration ready
F5 AN30 2.5-V FPGA partial reconfiguration request
B8 AW8 2.5-V HSMC port A present
A8 AU7 2.5-V HSMC port B present
P11 — 1.8-V
P12 — 1.8-V
25-MHz clock to on-board USB-Blaster for
sending FACTORY command
A low signal disables the on-board
USB-Blaster when PCIe masters the JTAG
P10 U31 1.8-V MAX V byte enable 0
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–11
MAX V CPLD System Controller
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 5 of 6)
Schematic Signal Name
MAX5_BEN1
MAX5_BEN2
MAX5_BEN3
MAX5_CLK
MAX5_CSN
MAX5_OEN
MAX5_WEN
MAX_CONF_DONE
MAX_ERROR
MAX_LOAD
MAX_RESETn
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
OVERTEMP
OVERTEMPn
PCIE_JTAG_EN
PGM_CONFIG
PGM_LED0
PGM_LED1
PGM_LED2
PGM_SEL
SDI_RX_BYPASS
SDI_RX_EN
SDI_TX_EN
SECURITY_MODE
SENSE_CS0n
SENSE_SCK
SENSE_SDI
SENSE_SDO
SENSE_SMB_CLK
SENSE_SMB_DATA
SI570_EN
MAX V CPLD
Pin Number
Stratix V GS
Pin Number
I/O
Standard
Description
R11 T31 1.8-V MAX V byte enable 1
T12 N33 1.8-V MAX V byte enable 2
N11 M33 1.8-V MAX V byte enable 3
T11 E34 1.8-V MAX V clock
R10 B32 1.8-V MAX V chip select
M10 A32 1.8-V MAX V output enable
N10 A34 1.8-V MAX V write enable
E11 — 1.8-V FPGA configuration done LED
A4 — 1.8-V FPGA configuration error LED
A6 — 1.8-V FPGA configuration active LED
M9 — 1.8-V MAX V reset push button
B10 AA9 2.5-V DIP - FPGA mode select 0
B3 AA10 2.5-V DIP - FPGA mode select 1
C10 AD8 2.5-V DIP - FPGA mode select 2
C12 AG8 2.5-V DIP - FPGA mode select 3
C6 AH7 2.5-V DIP - FPGA mode select 4
B7 — 2.5-V Temperature monitor fan enable
C8 — 2.5-V
Temperature monitor over-temperature
indicator LED
C7 — 2.5-V DIP switch to enable the PCIe JTAG master
D12 — 2.5-V
Loads the flash memory image identified by
the PGM LEDs
B14 — 2.5-V Flash memory PGM select indicator 0
C13 — 2.5-V Flash memory PGM select indicator 1
B16 — 2.5-V Flash memory PGM select indicator 2
B13 — 2.5-V Toggles the
PGM_LED[0:2]
sequence
D5 AB30 2.5-V SDI equalization bypass
E8 AB28 2.5-V SDI receive enable
D11 AK27 2.5-V SDI transmit enable
R12 — 1.8-V
DIP - On-board USB-Blaster II send
FACTORY command at power up.
E7 — 2.5-V Power monitor chip select
A5 — 2.5-V Power monitor SPI clock
D7 — 2.5-V Power monitor SPI data in
B6 — 2.5-V Power monitor SPI data out
D8 — 2.5-V Temperature monitor SMB clock
A7 — 2.5-V Temperature monitor SMB data
A10 — 2.5-V Si570 programmable oscillator enable
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–12 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Table 2–5. MAX V CPLD System Controller Device Pin-Out (Part 6 of 6)
Schematic Signal Name
SI571_EN
TSENSE_ALERTn
MAX V CPLD
Pin Number
D4 — 2.5-V Si571 programmable VCXO enable
B5 — 2.5-V Temperature monitor alert
Stratix V GS
Pin Number
I/O
Standard
Description
Tab le 2– 6 lists the MAX V CPLD System Controller component reference and
manufacturing information.
Table 2–6. MAX V CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference Description Manufacturer
U4
MAX V CPLD 2210 LE
256FBGA LF 1.8V VCCINT
Altera
Corporation 5M2210ZF256C4N www.altera.com
Manufacturing
Part Number
Manufacturer
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX V CPLD System Controller
device programming methods that the DSP Development Kit, Stratix V Edition
supports.
Website
The development board supports three configuration methods:
■ On-Board USB-Blaster II is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied
micro-USB cable.
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program load push button (S2).
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
FPGA Programming over On-Board USB-Blaster II
The on-board USB-Blaster II is implemented using a micro-USB type-B connector (J7),
a USB 2.0 PHY device, and an Altera MAX II CPLD EPM570GM100 (U14). This allows
the configuration of the FPGA using a USB cable which connects directly between the
USB port on the board (J7) and a USB port on a PC running the Quartus II software.
The on-board USB-Blaster II normally masters the JTAG chain.
f For more information about the on-board USB-Blaster II, refer to the on-board
USB-Blaster II page of the Altera Wiki website.
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
Chapter 2: Board Components 2–13
Configuration, Status, and Setup Elements
MAX II CPLD EPM570GM100
The MAX II CPLD is dedicated to the on-board USB-Blaster II functionality. The
CPLD connects to the CY7C68013A USB 2.0 PHY device on one side and drives the
JTAG and System Console direct USB signals out the other side through the general
purpose I/O (GPIO) pins.
Tab le 2– 7 lists the I/O signals present on the MAX II CPLD EPM570GM100.
Table 2–7. MAX II CPLD EPM570GM100 On-Board USB-Blaster II I/O Signals
Schematic Signal Name Type Description
SC_RX
SC_TX
JTAG_RX
JTAG_TX
C_JTAG_TCK
C_JTAG_TMS
C_JTAG_TDI
C_JTAG_TDO
USB_CLK
USB_OEn
USB_RESETn
USB_DATA(7:0)
USB_RDn
USB_WRn
USB_EMPTY
USB_FULL
USB_ADDR(1:0)
USB_SCL
USB_SDA
FACTORY_REQUEST
FACTORY_STATUS
M570_CLOCK
1.5-V CMOS output USB system console receive LED
1.5-V CMOS output USB system console transmit LED
1.5-V CMOS output USB-Blaster II JTAG receive LED
1.5-V CMOS output USB-Blaster II JTAG transmit LED
2.5-V CMOS output GPIO for on-board JTAG chain clock
2.5-V CMOS output GPIO for on-board JTAG chain mode
2.5-V CMOS output GPIO for on-board JTAG chain data in
2.5-V CMOS input GPIO for on-board JTAG chain data out
1.5-V CMOS input USB System Console clock
1.5-V CMOS input USB System Console FPGA output enable
1.5-V CMOS input USB System Console reset
1.5-V CMOS inout (8 bits) USB System Console FIFO data bus
1.5-V CMOS input USB System Console read from FIFO
1.5-V CMOS input USB System Console write to FIFO
1.5-V CMOS output USB System Console FIFO empty
1.5-V CMOS output USB System Console FIFO full
1.5-V CMOS input/output USB System Console address bus
1.5-V CMOS input/output USB System Console configuration clock
1.5-V CMOS input/output USB System Console configuration data
1.5-V CMOS input Send FACTORY command
1.5-V CMOS output FACTORY command status
1.5-V CMOS input 25-MHz input clock for FACTORY command
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
2–14 Chapter 2: Board Components
Cypress
On-Board
USB-Blaster II
GPIO
TCK
Stratix V GS
FPGA
Analog
Switch
MAX V
System
Controller
HSMC
Port A
HSMC
Port B
GPIO
TMS
GPIO
TDO
GPIO
TDI
JTAG Master
GPIO
DISABLE
ENABLE
ENABLE
ENABLE
ENABLE
JTAG Slave
JTAG Slave
Installed
HSMC
Card
Installed
HSMC
Card
TCK
TMS
TDI
TDO
TCK
2.5 V
TMS
TDI
TDO
TCK
TMS
TDI
TDO
TCK
TMS
TDI
TDO
JTAG Slave
JTAG Slave
Analog
Switch
Analog
Switch
ALWAYS
ENABLED
(in chain)
DIP Switch
DIP Switch
DIP Switch
DIP Switch
10-pin
JTAG Header
Flash
Memory
PCI Express
Edge
Connector
JTAG Master
PCI Express
Motherboard
TCK
TMS
TDI
TDO
Level
Translator
2.5 V
2.5 V
Configuration, Status, and Setup Elements
JTAG Chain
The on-board USB-Blaster II is automatically disabled when you connect an external
USB-Blaster to the JTAG chain or when you enable JTAG from the PCI Express edge
connector. Figure 2–3 illustrates the JTAG chain.
Figure 2–3. JTAG Chain
Each jumper shown in Figure 2–3 is located in the JTAG DIP switch (SW3) on the back
of the board. To connect a device or interface in the chain, their corresponding switch
must be in the OFF position. Push all the switches in the ON position to only have the
FPGA in the chain. Note that the MAX V CPLD System Controller must be in the
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
chain to use some of the GUI interfaces.
Chapter 2: Board Components 2–15
Configuration, Status, and Setup Elements
1 By default, the on-board USB-Blaster II clocks
TCK
at 24 MHz. For the on-board
USB-Blaster II to function correctly, you must set the Quartus II clock constraint on the
internal_tck
input signal to 24 MHz.
System Console USB Interface
The System Console USB interface is a fast parallel interface. Together with the soft
logic supplied by Altera, this interface provides a system console master for debug
access.
The system console controls the debug master via signals shown in Tab le 2–8 to give
fast access to an Avalon
®
Memory-Mapped (Avalon-MM) master bus that the Qsys
system integration tool generates.
f For more information about the system console, refer to the Analyzing and Debugging
Designs with the System Console chapter in volume 3 of the Quartus II Handbook.
Tab le 2– 8 lists the System Console USB interface pin connections relative to the FPGA.
Table 2–8. System Console USB Interface Pin Connections
Stratix V GS Device Pin Number Schematic Signal Name Direction Note
AV28
H34
G32, G33, F32, E32, A37, A36, C34, A35
N34
P34
J33
K33
E33
G34, K34
J34
F33
usb_clk
usb_reset_n
usb_data[7:0]
usb_full
usb_empty
usb_wr_n
usb_rd_n
usb_oe_n
usb_addr
usb_scl
usb_sda
input 48 MHz
input —
bidirectional G32(MSB), A35 (LSB)
output —
output —
input —
input —
input —
bidirectional Reserved
bidirectional —
bidirectional —
Flash Programming
Flash programming is possible through a variety of methods using the Stratix V GS
device.
The first method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware (page 1) of the flash over the network.
July 2012 Altera Corporation DSP Development Kit, Stratix V Edition
Reference Manual
Loading...