ALTERA Cyclone III Device Family User Guide

Cyclone® III Device Family Pin Connection Guidelines

PCG-01003- 1.1

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The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Cyclone® III Device Family Pin Connection Guidelines

PCG-01003- 1.1 Note (1)

You should create a Quartus® II design, enter your device I/O assignments and compile the design. Quartus II will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Cyclone III Devices Pin Name Cyclone III LS Devices Pin Name

Supply and Reference Pins

VCCINT VCCINT Power These are internal logic array voltage supply pins. All VCCINT pins must be connected to 1.2 V supply. Decoupling depends on the

VCCIO[1..8] VCCIO[1..8] Power These are I/O supply voltage pins for banks 1 through 8. Each bank can

VREFB[1..8]N[0..2] Note 2 VREFB[1..8]N[0..2] I/O Input reference voltage for each I/O bank. If a bank uses a voltage-

VCCA[1..4] Note 3 VCCA[1..4] Power Analog power for PLLs[1..4]. All VCCA pins must be powered and all VCCA

VCCD_PLL[1..4] Note 3 VCCD_PLL[1..4] Power Digital power for PLLs[1..4]. The designer must power up these pins, even if

Pin Type (1st, 2nd, & 3rd Function) Pin Description Connection Guidelines

design decoupling requirements of the specific board. See Note 5.

Connect these pin to 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V supplies, support a different voltage level. VCCIO supplies power to the input and output buffers for all I/O standards. VCCIO powers up the JTAG pins (TCK, TMS, TDI, and TDO) and the following configuration pins.. nCONFIG, DCLK, DATA[0..15], nCE, nCEO, nWE, nRESET, nOE, FLASH_nCE, nCSO, and CLKUSR.

referenced I/O standard for input operation, then these pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not used in the bank, the VREF pins are available as user I/O pins.

pins must be powered up and powered down at the same time even if not all the PLLs are used. Designer is advised to keep isolated from other VCC for better jitter performance.

the PLL is not used.

depending on the I/O standard assigned to the I/O bank. Decoupling depends on

the design decoupling requirements of the specific board. See Note 5.

If VREF pins are not used, the designer should connect them to either the VCCIO

of the I/O bank in which the pin resides or GND. Decoupling depends on the

design decoupling requirements of the specific board. See Note 5. When VREF

pins are used as I/O, they have higher capacitance than regular I/O pins which will

slow the edge rates and affect I/O timing.

The designer must connect these pins to 2.5 V, even if the PLL is not used. These

pins must be powered up and powered down at the same time. Connect

VCCA[1..4] pins together. VCCA supply to the chip should be isolated. See Note 6

for details. See Note 7 for recommended decoupling.

The designer must connect these pins to 1.2 V, even if the PLL is not used.

Connect VCCD_PLL[1..4] pins together. VCCD_PLL supply to the chip should be

isolated. See Note 6 for details. See Note 8 for recommended decoupling.

NA VCCBAT Power Battery back-up power supply for design security volatile key register. The

RUP[1..4] RUP[1..4] I/O, Input Reference pins for on-chip termination (OCT) block in I/O banks 2, 4, 5, and

RDN[1..4] RDN[1..4] I/O, Input Reference pins for on-chip termination (OCT) block in I/O banks 2, 4, 5, and

GND GND Ground Device ground pins. All GND pins should be connected to the board GND plane. GNDA[1..4] Note 3 GNDA[1..4] Ground Ground for PLLs[1..4] and other analog circuits in the device. The designer can consider connecting the GNDA pins to the GND plane without

NC NC No Connect No Connect. Do not connect these pins to any signal. These pins should be left unconnected,

nominal voltage for this supply is 3.0 V.

7. The external precision resistor RUP must be connected to the designated RUP pin within the same bank when used. If the RUP pin is not used, this pin can function as a regular I/O pin.

7. The external precision resistor RDN must be connected to the designated RDN pin within the same bank when used. If the RDN pin is not used, this pin can function as a regular I/O pin.

Pin Connection Guidelines Page 2 of 9

Connect this pin to a 3.0 V non-volatile battery power source if using the volatile

key. Its valid operating range is from 1.2 to 3.3-V. When not using the volatile key

tie this to either 1.8-V, 2.5-V or 3.0-V power supply.

When using OCT tie these pins to the required banks VCCIO through either a 25 

or 50  resistor, depending on the desired I/O standard. When the device does

not use this dedicated input for the external precision resistor or as an I/O, it is

recommended that the pin be connected to VCCIO of the bank in which the RUP

pin resides or GND.

When using OCT tie these pins to GND through either a 25  or 50  resistor

depending on the desired I/O standard. When the device does not use this

dedicated input for the external precision resistor or as an I/O, it is recommended

that the pin be connected to GND.

isolating the analog ground plane on the board provided the digital GND plane(s)

are stable, quiet, and with no ground bounce effect.

except when device migration requires a different connection to support different

density devices.

Cyclone® III Device Family Pin Connection Guidelines

PCG-01003- 1.1 Note (1)

Cyclone III Devices Pin Name Cyclone III LS Devices Pin Name

Dedicated Configuration/JTAG Pins

DCLK DCLK Input (PS, FPP)

Pin Type (1st, 2nd, & 3rd Function) Pin Description Connection Guidelines

Output (AS, AP Note 13)

DCLK is the dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into Cyclone III device. In AS and AP Note 13 modes, DCLK is an output from the Cyclone III device that provides timing for the configuration interface.

DCLK should not be left floating. In JTAG configuration and schemes that use an

external host, designer should drive it high or low, whichever is more convenient

on the board. In AS and AP Note 13 mode, the DCLK has an internal pull-up

resistor (typically 25-K) that is always active.

DATA0 DATA0 Input (PS,FPP,AS)

MSEL[0..3] MSEL[0..3] Input Configuration input pins that set the Cyclone III device configuration scheme.

nCE nCE Input Dedicated active-low chip enable. When nCE is low, the device is enabled.

nCONFIG nCONFIG Input Dedicated configuration control input. Pulling this pin low during user-mode

CONF_DONE CONF_DONE Bidirectional

nSTATUS nSTATUS Bidirectional

TCK TCK Input Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting

TMS TMS Input Dedicated JTAG input pin. The JTAG circuitry can be disabled by

Bidirectional open-drain (AP Note 13)

(open-drain)

Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. In AS mode, DATA0 has an internal pull-up resistor that is always active. After AS configuration, DATA0 is a dedicated input pin with optional user control. After PS or PP configuration, DATA0 is available as a user I/O pin and the state of this pin depends on the Dual-Purpose Pin settings. After AP Note 13 configuration, DATA0 is a dedicated bidirectional pin with optional user control.

Some of the smaller devices or package options do not support the AP Note 13 flash programming and do not have the MSEL3 pin.

When nCE is high, the device is disabled.

will cause the FPGA to lose its configuration data, enter a reset state and tristate all I/O pins. Returning this pin to a logic high level will initiate reconfiguration.

This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode.

This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization.

TCK to GND.

connecting TMS to VCC.

If you are using a serial configuration device in AS configuration mode, you must

connect a 25- series resistor at the near end of the serial configuration device for

the DATA0. If DATA0 is not used, it should be driven high or low, whichever is

more convenient on the board.

These pins are internally connected to 5-K resistor to GND. Do not leave these

pins floating. When these pins are unused connect them to GND. Depending on

the configuration scheme used, these pins should be tied to VCCA or GND. Refer

to Chapter 9 of Cyclone III Device Family Handbook: Configuration, Design

Security, and Remote System Upgrades in Cyclone III Devices. If only JTAG

configuration is used, then connect these pins to GND.

In multi-device configuration, nCE of the first device is tied directly to GND while

its nCEO pin drives the nCE of the next device in the chain. In single device

configuration, nCE is tied directly to GND. The nCE pin must also be held low for

successful JTAG programming of the device. If you are combining JTAG and AS

configuration schemes, then the nCE should be tied to GND through a 10-K 

resistor.

If you are using PS configuration scheme with a download cable, connect this pin

through a 10-K resistor to VCCA. For other configuration schemes, if this pin is

not used, this pin must be connected directly or through a 10-K  resistor to

VCCIO.

This pin is not available as a user I/O pin. CONF_DONE should be pulled high by

an external 10-K pull-up resistor.

This pin is not available as a user I/O pin. nSTATUS should be pulled high by an

external 10-K pull-up resistor.

Connect this pin to a 1-K resistor to GND.

When interfacing with 2.5 V/3.0 V/3.3 V configuration voltage standards, connect

this pin through a 10-K resistor to VCCA. For configuration voltage of 1.5 V and

1.8 V, connect this pin through a 10-K  resistor to VCCIO supply instead. See

Note 10.

Pin Connection Guidelines Page 3 of 9

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ALTERA Cyclone III Device Family User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

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Pin Connection Guidelines Page 2 of 9