ALTERA Cyclone III Data sheet

July 2012 CIII52001-3.5
CIII52001-3.5
1. Cyclone III Device Datasheet
This chapter describes the electric characteristics, switching characteristics, and I/O timing for Cyclone

Electrical Characteristics

The following sections provide information about the absolute maximum ratings, recommended operating conditions, DC characteristics, and other specifications for Cyclone III devices.

Operating Conditions

When Cyclone III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Cyclone III devices, system designers must consider the operating requirements in this document. Cyclone III devices are offered in commercial, industrial, and automotive grades. Commercial devices are offered in –6 (fastest), –7, and –8 speed grades. Industrial and automotive devices are offered only in –7 speed grade.
1 In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix, industrial with “I” prefix, and automotive with “A” prefix. Commercial devices are therefore indicated as C6, C7, and C8 per respective speed grades. Industrial and automotive devices are indicated as I7 and A7, respectively.
®
III devices. A glossary is also included for your reference.

Absolute Maximum Ratings

Absolute maximum ratings define the maximum operating conditions for Cyclone III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions. Tabl e 1– 1 lists the absolute maximum ratings for Cyclone III devices.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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1–2 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
1 Conditions beyond those listed in Table 1–1 cause permanent damage to the device.
Additionally, device operation at the absolute maximum ratings for extended periods of time has adverse effects on the device.
Table 1–1. Cyclone III Devices Absolute Maximum Ratings
(1)
Symbol Parameter Min Max Unit
V
CCINT
V
CCIO
V
CCA
V
CCD_PLL
V
I
I
OUT
V
ESDHBM
V
ESDCDM
T
STG
T
J
Note to Tab le 1– 1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the
Supply voltage for internal logic –0.5 1.8 V
Supply voltage for output buffers –0.5 3.9 V
Supply voltage (analog) for phase-locked loop (PLL) regulator
–0.5 3.75 V
Supply voltage (digital) for PLL –0.5 1.8 V
DC input voltage –0.5 3.95 V
DC output current, per pin –25 40 mA
Electrostatic discharge voltage using the human body model
Electrostatic discharge voltage using the charged device model
±2000 V
±500 V
Storage temperature –65 150 °C
Operating junction temperature –40 125 °C
power supply.
Maximum Allowed Overshoot or Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in Ta ble 1 –2 and undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods shorter than 20 ns. Tab le 1– 2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. The maximum allowed overshoot duration is specified as percentage of high-time over the lifetime of the device.
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–3
3.3 V
4.1 V
4.2 V
T
ΔT
Electrical Characteristics
1 A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to
4.2 V can only be at 4.2 V for 10.74% over the lifetime of the device; for device lifetime of 10 years, this amounts to 10.74/10ths of a year.
Table 1–2. Cyclone III Devices Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame
(1)
Symbol Parameter Condition Overshoot Duration as % of High Time Unit
= 3.95 V 100 %
V
I
V
= 4.0 V 95.67 %
I
V
= 4.05 V 55.24 %
I
V
= 4.10 V 31.97 %
I
V
= 4.15 V 18.52 %
I
V
= 4.20 V 10.74 %
I
V
= 4.25 V 6.23 %
V
i
AC Input
Voltage
Note to Tab le 1– 2:
(1) Figure 1–1 shows the methodology to determine the overshoot duration. In the example in Figure 1–1, overshoot
voltage is shown in red and is present on the input pin of the Cyclone III device at over 4.1 V but below 4.2 V. From
Table 1–1, for an overshoot of 4.1 V, the percentage of high time for the overshoot can be as high as 31.97% over
a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device is in an idle state, lifetimes are increased.
I
V
= 4.30 V 3.62 %
I
V
= 4.35 V 2.1 %
I
V
= 4.40 V 1.22 %
I
V
= 4.45 V 0.71 %
I
V
= 4.50 V 0.41 %
I
V
= 4.60 V 0.14 %
I
V
= 4.70 V 0.047 %
I
Figure 1–1 shows the methodology to determine the overshoot duration.
Figure 1–1. Cyclone III Devices Overshoot Duration
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–4 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics

Recommended Operating Conditions

This section lists the functional operation limits for AC and DC parameters for Cyclone III devices. The steady-state voltage and current values expected from Cyclone III devices are provided in Tab le 1 –3 . All supplies must be strictly monotonic without plateaus.
Table 1–3. Cyclone III Devices Recommended Operating Conditions
(1), (2)
Symbol Parameter Conditions Min Typ Max Unit
(3)
V
CCINT
V
CCIO
V
CCA
V
CCD_PLL
V
I
V
O
(3),
(3)
Supply voltage for internal logic 1.15 1.2 1.25 V
Supply voltage for output buffers, 3.3-V operation
Supply voltage for output buffers, 3.0-V operation
Supply voltage for output buffers, 2.5-V operation
(4)
Supply voltage for output buffers, 1.8-V operation
Supply voltage for output buffers, 1.5-V operation
Supply voltage for output buffers, 1.2-V operation
Supply (analog) voltage for PLL regulator
(3)
Supply (digital) voltage for PLL 1.15 1.2 1.25 V
3.135 3.3 3.465 V
2.85 3 3.15 V
2.375 2.5 2.625 V
1.71 1.8 1.89 V
1.425 1.5 1.575 V
1.14 1.2 1.26 V
2.375 2.5 2.625 V
Input voltage –0.5 3.6 V
Output voltage 0 V
CCIO
V
For commercial use 0 85 °C
T
J
Operating junction temperature
For industrial use –40 100 °C
For extended temperature –40 125 °C
For automotive use –40 125 °C
Standard power-on reset
(5)
t
RAMP
I
Diode
Notes to Table 1–3:
(1) V
CCIO
must be powered up and powered down at the same time.
(2) V
CCD_PLL
(3) The V (4) All input buffers are powered by the V (5) POR time for Standard POR ranges between 50–200 ms. Each individual power supply should reach the recommended operating range within
50 ms.
(6) POR time for Fast POR ranges between 3–9 ms. Each individual power supply should reach the recommended operating range within 3 ms.
Power supply ramp time
Magnitude of DC current across PCI-clamp diode when enabled
for all I/O banks must be powered up during device operation. All V
must always be connected to V
must rise monotonically.
CC
through a decoupling capacitor and ferrite bead.
CCINT
supply.
CCIO
(POR)
Fast POR
(6)
——10mA
pins must be powered to 2.5 V (even when PLLs are not used), and
CCA
50 µs 50 ms
50 µs 3 ms
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–5
Electrical Characteristics

DC Characteristics

This section lists the I/O leakage current, pin capacitance, on-chip termination (OCT) tolerance, and bus hold specifications for Cyclone III devices.
Supply Current
Standby current is the current the device draws after the device is configured with no inputs or outputs toggling and no activity in the device. Use the Excel-based early power estimator (EPE) to get the supply current estimates for your design because these currents vary largely with the resources used. Tab le 1 –4 lists I/O pin leakage current for Cyclone III devices.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Table 1–4. Cyclone III Devices I/O Pin Leakage Current
Symbol Parameter Conditions Min Typ Max Unit
I
I
I
OZ
Notes to Table 1–4:
(1) This value is specified for normal device operation. The value varies during device power-up. This applies for all
(2) 10 A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the
Input pin leakage current VI = 0 V to V
Tristated I/O pin leakage current
V
settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
CCIO
observed when the diode is on.
V
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.
Tab le 1– 5 lists bus hold specifications for Cyclone III devices.
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 1 of 2)
Parameter Condition
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold low, sustaining
> V
V
IN
IL
(maximum)
8 — 12 — 30—50—70—70—A
current
Bus-hold high, sustaining
< V
V
IN
IL
(minimum)
–8 –12 –30 –50 –70 –70 A
current
= 0 V to V
O
(1)
V
CCIO
(1), (2)
CCIOMAX
CCIOMAX
(V)
–10 10 A
–10 10 A
Unit1.2 1.5 1.8 2.5 3.0 3.3
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–6 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Table 1–5. Cyclone III Devices Bus Hold Parameter (Part 2 of 2)
(1)
V
CCIO
Parameter Condition
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold low, overdrive
0 V < V
IN
< V
125 175 200 300 500 500 A
CCIO
current
Bus-hold high, overdrive
0 V < V
IN
< V
–125 –175 –200 –300 –500 –500 A
CCIO
current
Bus-hold trip point
Note to Table 1–5:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
OCT Specifications
Tab le 1– 6 lists the variation of OCT without calibration across process, temperature,
and voltage.
(V)
Unit1.2 1.5 1.8 2.5 3.0 3.3
Table 1–6. Cyclone III Devices Series OCT without Calibration Specifications
Resistance Tolerance
Description V
CCIO
(V)
Commercial
Max
Industrial and Automotive
Max
Unit
3.0 ±30 ±40 %
2.5 ±30 ±40 %
Series OCT without calibration
1.8 +40 ±50 %
1.5 +50 ±50 %
1.2 +50 ±50 %
OCT calibration is automatically performed at device power-up for OCT enabled I/Os.
Tab le 1– 7 lists the OCT calibration accuracy at device power-up.
Table 1–7. Cyclone III Devices Series OCT with Calibration at Device Power-Up Specifications
Calibration Accuracy
Description V
CCIO
(V)
Commercial Max
Industrial and Automotive
Max
Unit
3.0 ±10 ±10 %
Series OCT with calibration at device power-up
2.5 ±10 ±10 %
1.8 ±10 ±10 %
1.5 ±10 ±10 %
1.2 ±10 ±10 %
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–7
Electrical Characteristics
The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up. Use Table 1–8 and Equation 1–1 to determine the final OCT resistance considering the variations after calibration at device power-up.
Tab le 1– 8 lists the change percentage of the OCT resistance with voltage and
temperature.
Table 1–8. Cyclone III Devices OCT Variation After Calibration at Device Power-Up
Nominal Voltage dR/dT (%/°C) dR/dV (%/mV)
3.0 0.262 –0.026
2.5 0.234 –0.039
1.8 0.219 –0.086
1.5 0.199 –0.136
1.2 0.161 –0.288
Equation 1–1.
(1), (2), (3), (4), (5), (6)
RV = (V2 – V1) × 1000 × dR/dV
RT = (T2 – T1) × dR/dT
For Rx < 0; MFx = 1/ (|Rx|/100 + 1)
For Rx > 0; MFx = Rx/100 + 1
× MF
(11)
T
(12)
MF = MFV × MF
R
= R
final
initial
(7)
(8)
(9)
(10)
Notes to Equation 1–1:
(1) T2 is the final temperature.
is the initial temperature.
(2) T
1
(3) MF is multiplication factor. (4) R (5) R (6) Subscript × refers to both (7) R (8) R (9) dR/dT is the change percentage of resistance with temperature after calibration at device power-up. (10) dR/dV is the change percentage of resistance with voltage after calibration at device power-up. (11) V (12) V
is final resistance.
final
is initial resistance.
initial
and T.
V
is variation of resistance with voltage.
V
is variation of resistance with temperature.
T
is final voltage.
2
is the initial voltage.
1
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–8 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Example 1–1 shows you the example to calculate the change of 50 I/O impedance
from 25°C at 3.0 V to 85°C at 3.15 V:
Example 1–1.
R
= (3.15 – 3) × 1000 × –0.026 = –3.83
V
R
= (85 – 25) × 0.262 = 15.72
T
Because R
MF
Because R
MF
is negative,
V
= 1 / (3.83/100 + 1) = 0.963
V
is positive,
T
= 15.72/100 + 1 = 1.157
T
MF = 0.963 × 1.157 = 1.114
R
= 50 × 1.114 = 55.71
final
Pin Capacitance
Tab le 1– 9 lists the pin capacitance for Cyclone III devices.
Table 1–9. Cyclone III Devices Pin Capacitance
Symbol Parameter
C
IOTB
C
IOLR
C
LVD SLR
C
VREFLR
(1)
C
VREFTB
(1)
C
CLKTB
C
CLKLR
Notes to Table 1–9:
(1) When
(2) C
Input capacitance on top/bottom I/O pins 7 6 pF
Input capacitance on left/right I/O pins 7 5 pF
Input capacitance on left/right I/O pins with dedicated LVDS output
Input capacitance on left/right dual-purpose when used as V
or user I/O pin
REF
Input capacitance on top/bottom dual-purpose when used as V
or user I/O pin
REF
Input capacitance on top/bottom dedicated clock input pins
Input capacitance on left/right dedicated clock input pins 6 5 pF
VREF
higher pin capacitance.
VREFTB
pin is used as regular input or output, a reduced performance of toggle rate and t
for EP3C25 is 30 pF.
VREF
VREF
pin
pin
Typical –
QFP
Typical –
FBGA
Unit
87pF
21 21 pF
23
(2)
23
(2)
pF
76pF
is expected due to
CO
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–9
Electrical Characteristics
Internal Weak Pull-Up and Weak Pull-Down Resistor
Tab le 1– 10 lists the weak pull-up and pull-down resistor values for Cyclone III
devices.
Table 1–10. Cyclone III Devices Internal Weak Pull-Up and Weak Pull-Down Resistor
(1)
Symbol Parameter Conditions Min Typ Max Unit
= 3.3 V ± 5%
V
CCIO
V
= 3.0 V ± 5%
Value of I/O pin pull-up resistor before
R
_PU
and during configuration, as well as user mode if the programmable pull-up resistor option is enabled
R
_PD
Value of I/O pin pull-down resistor before and during configuration
CCIO
V
= 2.5 V ± 5%
CCIO
V
= 1.8 V ± 5%
CCIO
V
= 1.5 V ± 5%
CCIO
V
= 1.2 V ± 5%
CCIO
V
= 3.3 V ± 5%
CCIO
V
= 3.0 V ± 5%
CCIO
V
= 2.5 V ± 5%
CCIO
V
= 1.8 V ± 5%
CCIO
V
= 1.5 V ± 5%
CCIO
Notes to Table 1–10:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pin. Weak pull-down feature is only available for JTAG
TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V (3) R
(4) R
= (V
_PU
Minimum condition: –40°C; V
Typical condition: 25°C; V
Maximum condition: 125°C; V
= VI/I
_PD
Minimum condition: –40°C; V
Typical condition: 25°C; V
Maximum condition: 125°C; V
CCIO–VI
R_PD
)/I
R_PU
= V
CCIO
= VCC, VI = 0 V;
CCIO
CCIO
CCIO
= VCC, VI = VCC–5%;
CCIO
CCIO
+ 5%, VI = V
CC
= V
– 5%, VI = 0 V; in which VI refers to the input voltage at the I/O pin.
CC
= V
+ 5%, VI = 50 mV;
CC
= V
– 5%, VI = VCC– 5%; in which VI refers to the input voltage at the I/O pin.
CC
+ 5% – 50 mV;
CC
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(2), (3)
(4)
(4)
(4)
(4)
(4)
CCIO
72541k
72847k
83561k
10 57 108 k
13 82 163 k
19 143 351 k
61930k
62236k
62543k
73571k
850112k
.
Hot Socketing
Tab le 1– 11 lists the hot-socketing specifications for Cyclone III devices.
Table 1–11. Cyclone III Devices Hot-Socketing Specifications
Symbol Parameter Maximum
I
IOPIN(DC)
I
IOPIN(AC)
Note to Tab le 1– 11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C
dv/dt, in which C is I/O pin capacitance and dv/dt is the slew rate.
July 2012 Altera Corporation Cyclone III Device Handbook
DC current per I/O pin 300 A
AC current per I/O pin 8 mA
(1)
Volume 2
1–10 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
Schmitt Trigger Input
Cyclone III devices support Schmitt trigger input on
nCE, CONF_DONE
, and
DCLK
pins. A Schmitt trigger feature introduces hysteresis to the
TDI, TMS, TCK, nSTATUS, nCONFIG
,
input signal for improved noise immunity, especially for signal with slow edge rate.
Tab le 1– 12 lists the hysteresis specifications across supported V
range for Schmitt
CCIO
trigger inputs in Cyclone III devices.
Table 1–12. Hysteresis Specifications for Schmitt Trigger Input in Cyclone III Devices
Symbol Parameter Conditions Minimum Typical Maximum Unit
= 3.3 V 200 mV
V
CCIO
V
= 2.5 V 200 mV
V
SCHMITT
Hysteresis for Schmitt trigger input
CCIO
V
= 1.8 V 140 mV
CCIO
V
= 1.5 V 110 mV
CCIO

I/O Standard Specifications

The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH and V supported by Cyclone III devices. Table 1–13 through Tab le 1– 18 provide the I/O standard specifications for Cyclone III devices.
), and current drive characteristics (IOH and IOL) for various I/O standards
OL
Table 1–13. Cyclone III Devices Single-Ended I/O Standard Specifications
I/O Standard
(V) V
V
CCIO
(V) V
IL
Min Typ Max Min Max Min Max Max Min
(3)
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL and LVCMOS
(3)
1.8-V LVTTL and LVCMOS
1.5-V LVCMOS 1.425 1.5 1.575 –0.3
1.2-V LVCMOS 1.14 1.2 1.26 –0.3
3.0-V PCI 2.85 3.0 3.15
3.0-V PCI-X 2.85 3.0 3.15
Notes to Table 1–13:
(1) For voltage referenced receiver input waveform and explanation of terms used in Tab le 1 –1 3, refer to “Single-ended Voltage referenced I/O Standard”
in “Glossary” on page 1–27. (2) AC load CL = 10 pF. (3) For more detail about interfacing Cyclone III devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
Devices with 3.3/3.0/2.5-V LVTTL and LVCMOS I/O Systems.
3.135 3.3 3.465 0.8 1.7 3.6 0.45 2.4 4 –4
(3)
3.135 3.3 3.465 0.8 1.7 3.6 0.2 V
(3)
2.85 3.0 3.15 –0.3 0.8 1.7 V
(3)
2.85 3.0 3.15 –0.3 0.8 1.7 V
2.375 2.5 2.625 –0.3 0.7 1.7 3.6 0.4 2.0 1 –1
1.71 1.8 1.89 –0.3
0.35 * V
0.35 * V
0.35 * V
0.3 * V
0.35* V
CCIO
CCIO
CCIO
CCIO
CCIO
0.65 * V
CCIO
0.65 * V
CCIO
0.65 * V
CCIO
0.5 * V
CCIO
0.5 * V
CCIO
(1), (2)
(V) V
IH
+ 0.3 0.45 2.4 4 –4
CCIO
+ 0.3 0.2 V
CCIO
2.25 0.45
V
+ 0.3
CCIO
V
+ 0.3
CCIO
V
+ 0.3 0.1 * V
CCIO
V
+ 0.3 0.1 * V
CCIO
(V) V
OL
0.25 * V
CCIO
0.25 * V
CCIO
CCIO
CCIO
(V)
OH
– 0.2 2 –2
CCIO
– 0.2 0.1 –0.1
CCIO
V
CCIO
0.45
0.75 * V
CCIO
0.75 * V
CCIO
0.9 * V
CCIO
0.9 * V
CCIO
I
(mA)
I
OL
(mA)
2–2
2–2
2–2
1.5 –0.5
1.5 –0.5
OH
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–11
Electrical Characteristics
Table 1–14. Cyclone III Devices Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
V
(V) V
I/O
Standard
SSTL-2 Class I, II
SSTL-18 Class I, II
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
Notes to Table 1–14:
(1) For an explanation of terms used in Table 1–14, refer to “Glossary” on page 1–27.
of transmitting device must track V
(2) V
TT
(3) Value shown refers to DC input reference voltage, V (4) Value shown refers to AC input reference voltage, V
CCIO
Min Typ Max Min Typ Max Min Typ Max
2.375 2.5 2.625 1.19 1.25 1.31
1.7 1.8 1.9 0.833 0.9 0.969
1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95
1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79
1.14 1.2 1.26
0.48 * V
0.47 * V
of the receiving device.
REF
CCIO
CCIO
REF(DC)
REF(AC)
(3)
0.5 * V
(4)
0.5 * V
. .
(V) V
REF
V
REF
0.04
V
REF
0.04
CCIO
CCIO
(3)
0.52 * V
(4)
0.53 * V
CCIO
CCIO
(3)
(4)
Table 1–15. Cyclone III Devices Single-Ended SSTL and HSTL I/O Standards Signal Specifications
(1)
TT
0.5 * V
CCIO
V
V
(V)
REF
REF
(2)
V
+
REF
0.04
V
+
REF
0.04
I/O
Standard
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
(V) V
V
IL(DC)
(V) V
IH(DC)
(V) V
IL(AC)
(V) V
IH(AC)
(V) V
OL
OH
Min Max Min Max Min Max Min Max Max Min
V
–0.15
–0.15
V
REF
0.18
V
REF
0.18
V
REF
0.125
V
REF
0.125
V
REF
0.1
V
REF
0.1
V
REF
0.1
V
REF
0.1
V
REF
0.08
V
REF
0.08
+
REF
0.18
V
+
REF
0.18
V
+
REF
0.125
V
+
REF
0.125
V
+
REF
0.1
V
+
REF
0.1
V
+
REF
0.1
V
+
REF
0.1
V
+
REF
0.08
V
+
REF
0.08
——
——
——
——
——
——
——
——
V
+ 0.15 –0.24
CCIO
V
+ 0.15 –0.24
CCIO
V
REF
0.35
V
REF
0.35
V
REF
0.25
V
REF
0.25
V
REF
0.2
V
REF
0.2
V
REF
0.2
V
REF
0.2
V
REF
0.15
V
REF
0.15
V
0.35
V
0.35
V
0.25
V
0.25
V
V
V
V
V
0.15
V
0.15
REF
REF
REF
REF
REF
0.2
REF
0.2
REF
0.2
REF
0.2
REF
REF
+
+
+
+
+
+
+
+
—0.28
—0.4
—0.4
—0.4
—0.4
+
V
+
CCIO
0.24
+
V
+
CCIO
0.24
VTT –
0.57
VTT –
0.76
VTT –
0.475
0.25 × V
CCIO
0.25 × V
CCIO
VTT +
0.57
V
0.76
VTT +
0.475
V
CCIO
0.28
V
CCIO
V
CCIO
V
CCIO
V
CCIO
0.75 × V
0.75 × V
TT
0.4
0.4
0.4
0.4
CCIO
CCIO
(V)
+
I
I
OL
(mA)
OH
(mA)
8.1 –8.1
16.4 –16.4
6.7 –6.7
13.4 –13.4
8–8
16 –16
8–8
16 –16
8–8
14 –14
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–12 Chapter 1: Cyclone III Device Datasheet
Electrical Characteristics
f For more illustrations of receiver input and transmitter output waveforms, and for
other differential I/O standards, refer to the High-Speed Differential Interfaces in
Cyclone III Devices chapter.
Table 1–16. Cyclone III Devices Differential SSTL I/O Standard Specifications
I/O Standard
V
CCIO
(V) V
Swing(DC)
(V) V
X(AC)
(V)
Min Typ Max Min Max Min Typ Max Min Max Min Typ Max
V
CCIO
+ 0.2
V
CCIO
+ 0.175
SSTL-2 Class I, II
SSTL-18 Class I, II
Note to Table 1–16:
(1) Differential SSTL requires a V
2.375 2.5 2.625 0.36 V
1.7 1.8 1.90 0.25 V
REF
input.
CCIOVCCIO
V
CCIO
/2 – 0.2
/2 –
CCIO
0.175
Table 1–17. Cyclone III Devices Differential HSTL I/O Standard Specifications
V
(V) V
CCIO
(V) V
DIF(DC)
(V) V
X(AC)
I/O Standard
Min Typ Max Min Max Min Typ Max Min Typ Max
HSTL-18 Class I, II
HSTL-15 Class I, II
HSTL-12 Class I, II
Note to Table 1–17:
(1) Differential HSTL requires a V
1.71 1.8 1.89 0.2 0.85 0.95 0.85 0.95 0.4
1.425 1.5 1.575 0.2 0.71 0.79 0.71 0.79 0.4
1.14 1.2 1.26 0.16 V
input.
REF
CCIO
0.48 * V
CCIO
0.52 * V
CCIO
/2
/2
(1)
V
Swing(AC)
(V)
V
0.7
V
0.5
(1)
0.48 * V
CCIO
CCI
O
CCI
O
V
/2 –
CCIO
0.125
V
/2 –
CCIO
0.125
(V) V
CM(DC)
0.52 * V
V
OX(AC)
CCIO
(V)
V
+ 0.125
V
+ 0.125
DIF(AC)
Mi
n
0.3
CCIO
CCIO
Max
0.48 * V
/2
/2
(V)
CCIO
(V)
(2)
MAX
MAX
MAX
(1)
(Part 1 of 2)
1.80
1.80
1.80
(mV)
(3)
V
OD
(3)
V
(V)
OS
—— — — — —0.55
—— — — — —0.55
247 600 1.125 1.25 1.375 0.55
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
V
(V) V
I/O
Standard
CCIO
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
LVPECL (Row I/Os)
(4)
2.375 2.5 2.625 100
LVPECL (Column
(4)
I/Os)
LVDS (Row I/Os)
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
2.375 2.5 2.625 100
2.375 2.5 2.625 100
(mV) V
ID
0.05 D
1.05 D
0.05 D
1.05 D
0.05 D
1.05 D
IcM
500 Mbps 1.80
MAX
500 Mbps  D 700 Mbps
> 700 Mbps 1.55
MAX
 500 Mbps 1.80
MAX
500 Mbps D 700 Mbps
> 700 Mbps 1.55
MAX
 500 Mbps 1.80
MAX
500 Mbps D 700 Mbps
> 700 Mbps 1.55
MAX
Chapter 1: Cyclone III Device Datasheet 1–13
Electrical Characteristics
(V)
(2)
MAX
(1)
(Part 2 of 2)
1.80
V
(mV)
OD
247 600 1.125 1.25 1.3750.55
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
I/O
Standard
LVDS (Column I/Os)
(V) V
V
CCIO
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
2.375 2.5 2.625 100
(mV) V
ID
0.05 D
1.05 D
IcM
500 Mbps 1.80
MAX
500 Mbps D 700 Mbps
> 700 Mbps 1.55
MAX
BLVDS (Row I/Os)
(5)
2.375 2.5 2.625 100
BLVDS (Column
(5)
I/Os)
2.375 2.5 2.625 100
mini-LVDS (Row I/Os)
(6)
2.375 2.5 2.625 300 600 1.0 1.2 1.4
mini-LVDS (Column
(6)
I/Os)
®
RSDS (Row
(6)
I/Os)
2.375 2.5 2.625 300 600 1.0 1.2 1.4
2.375 2.5 2.625 100 200 600 0.5 1.2 1.5
RSDS (Column
(6)
I/Os)
®
PPDS (Row I/Os)
(6)
2.375 2.5 2.625 100 200 600 0.5 1.2 1.5
2.375 2.5 2.625 100 200 600 0.5 1.2 1.4
PPDS (Column
(6)
I/Os)
Notes to Table 1–18:
(1) For an explanation of terms used in Table 1–18, refer to “Transmitter Output Waveform” in “Glossary” on page 1–27. (2) V
IN
range: 90  RL  110  .
(3) R
L
(4) LVPECL input standard is only supported at clock input. Output standard is not supported. (5) No fixed V (6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
2.375 2.5 2.625 100 200 600 0.5 1.2 1.4
range: 0 V  VIN 1.85 V.
, VOD, and VOS specifications for BLVDS. They are dependent on the system topology.
IN
(3)
(3)
V
(V)
OS
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–14 Chapter 1: Cyclone III Device Datasheet

Switching Characteristics

Power Consumption

You can use the following methods to estimate power for a design:
the Excel-based EPE.
the Quartus II PowerPlay power analyzer feature.
The interactive Excel-based EPE is used prior to designing the device to get a magnitude estimate of the device power. The Quartus II PowerPlay power analyzer provides better quality estimates based on the specifics of the design after place-and­route is complete. The PowerPlay power analyzer can apply a combination of user­entered, simulation-derived, and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
f For more information about power estimation tools, refer to the Early Power Estimator
User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook.
Switching Characteristics
This section provides the performance characteristics of the core and periphery blocks for Cyclone III devices. All data is final and is based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions.

Core Performance Specifications

Clock Tree Specifications

Tab le 1– 19 lists the clock tree specifications for Cyclone III devices.
Table 1–19. Cyclone III Devices Clock Tree Performance
Device
EP3C5 500 437.5 402 MHz
EP3C10 500 437.5 402 MHz
EP3C16 500 437.5 402 MHz
EP3C25 500 437.5 402 MHz
EP3C40 500 437.5 402 MHz
EP3C55 500 437.5 402 MHz
EP3C80 500 437.5 402 MHz
EP3C120
Note to Tab le 1– 19:
(1) EP3C120 offered in C7, C8, and I7 grades only.
C6 C7 C8
(1)
Performance
Unit
437.5 402 MHz
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–15
Switching Characteristics

PLL Specifications

Tab le 1– 20 describes the PLL specifications for Cyclone III devices when operating in
the commercial junction temperature range (0°C to 85°C), the industrial junction temperature range (–40°C to 100°C), and the automotive junction temperature range (–40°Cto 125°C). For more information about PLL block, refer to “PLL Block” in
“Glossary” on page 1–27.
Table 1–20. Cyclone III Devices PLL Specifications
Symbol Parameter Min Typ Max Unit
(2)
f
IN
f
INPFD
(3)
f
VCO
f
INDUTY
t
INJITTER_CCJ
f
OUT_EXT
(2)
(4)
(external clock output)
Input clock frequency 5 472.5 MHz
PFD input frequency 5 325 MHz
PLL internal VCO operating range 600 1300 MHz
Input clock duty cycle 40 60 %
Input clock cycle-to-cycle jitter for F
Input clock cycle-to-cycle jitter for F
PLL output frequency 472.5 MHz
PLL output frequency (–6 speed grade) 472.5 MHz
f
(to global clock)
OUT
PLL output frequency (–7 speed grade) 450 MHz
PLL output frequency (–8 speed grade) 402.5 MHz
t
OUTDUTY
t
LOCK
Duty cycle for external clock output (when set to 50%) 45 50 55 %
Time required to lock from end of device configuration 1 ms
Time required to lock dynamically (after switchover,
t
DLOCK
reconfiguring any non-post-scale counters/delays or areset is deasserted)
Dedicated clock output period jitter
t
OUTJITTER_PERIOD_DEDCLK
(5)
100 MHz
F
OUT
F
< 100 MHz 30 mUI
OUT
Dedicated clock output cycle-to-cycle jitter
t
OUTJITTER_CCJ_DEDCLK
(5)
100 MHz
F
OUT
F
< 100 MHz 30 mUI
OUT
Regular I/O period jitter
t
OUTJITTER_PERIOD_IO
(5)
100 MHz
F
OUT
F
< 100 MHz 75 mUI
OUT
Regular I/O cycle-to-cycle jitter
t
OUTJITTER_CCJ_IO
t
PLL_PSERR
t
ARESET
t
CONFIGPLL
(5)
100 MHz
F
OUT
F
< 100 MHz 75 mUI
OUT
Accuracy of PLL phase shift ±50 ps
Minimum pulse width on areset signal. 10 ns
Time required to reconfigure scan chains for PLLs 3.5
(1)
(Part 1 of 2)
100 MHz 0.15 UI
INPFD
< 100 MHz ±750 ps
INPFD
—— 1 ms
300 ps
300 ps
650 ps
650 ps
(6)
SCANCLK
cycles
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–16 Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications
(1)
(Part 2 of 2)
Symbol Parameter Min Typ Max Unit
f
SCANCLK
Notes to Table 1–20:
(1) V (2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (3) The V
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps. (5) Peak-to-peak jitter with a probability level of 10
(6) With 100 MHz
should always be connected to V
CCD_PLL
frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V
CO
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
jitter of the PLL, when an input jitter of 30 ps is applied.
scanclk
frequency.
scanclk
CCINT
frequency 100 MHz
through decoupling capacitor and ferrite bead.
post-scale
specification.
VCO
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
CO

Embedded Multiplier Specifications

Tab le 1– 21 describes the embedded multiplier specifications for Cyclone III devices.
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications
Mode
9 × 9-bit multiplier
18 × 18-bit multiplier
Resources Used Performance
Unit
Number of Multipliers C6 C7, I7, A7 C8
1 340 300 260 MHz
1 287 250 200 MHz

Memory Block Specifications

Tab le 1– 22 describes the M9K memory block specifications for Cyclone III devices.
Table 1–22. Cyclone III Devices Memory Block Performance Specifications
Resources Used Performance
Memory Mode
LEs
M9K
Memory
FIFO 256 × 36 47 1 315 274 238 MHz
M9K Block
Single-port 256 × 36 0 1 315 274 238 MHz
Simple dual-port 256 × 36 CLK 0 1 315 274 238 MHz
True dual port 512 × 18 single CLK 0 1 315 274 238 MHz

Configuration and JTAG Specifications

Tab le 1– 23 lists the configuration mode specifications for Cyclone III devices.
Table 1–23. Cyclone III Devices Configuration Mode Specifications
Programming Mode DCLK F
Passive Serial (PS) 133 MHz
Fast Passive Parallel (FPP)
Note to Tab le 1– 23:
(1) EP3C40 and smaller density members support 133 MHz.
(1)
C6 C7, I7, A7 C8 Unit
max
Unit
100 MHz
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–17
Switching Characteristics
Tab le 1– 24 lists the active configuration mode specifications for Cyclone III devices.
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications
Programming Mode DCLK Range Unit
Active Parallel (AP) 20 – 40 MHz
Active Serial (AS) 20 – 40 MHz
Tab le 1– 25 lists the JTAG timing parameters and values for Cyclone III devices.
Table 1–25. Cyclone III Devices JTAG Timing Parameters
(1)
Symbol Parameter Min Max Unit
t
JCP
t
JCH
t
JCL
t
JPSU_TDI
t
JPSU_TMS
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
Notes to Table 1–25:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27. (2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
TCK clock period 40 ns
TCK clock high time 20 ns
TCK clock low time 20 ns
JTAG port setup time for TDI 1 ns
JTAG port setup time for TMS 3 ns
JTAG port hold time 10 ns
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
(2)
(2)
(2)
—15ns
—15ns
—15ns
Capture register setup time 5 ns
Capture register hold time 10 ns
Update register clock to output 25 ns
Update register high impedance to valid output 25 ns
Update register valid output to high impedance 25 ns
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.

Periphery Performance

This section describes periphery performance, including high-speed I/O, external memory interface, and IOE programmable delay.
I/O performance supports several system interfacing, for example, the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speeds with typical DDR SDRAM memory interface setup. I/O using general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load.
1 Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–18 Chapter 1: Cyclone III Device Datasheet
Switching Characteristics

High-Speed I/O Specifications

Tab le 1– 26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
(1), (2)
C6 C7, I7 C8, A7
Symbol Modes
Unit
Min Typ Max Min Typ Max Min Typ Max
×10 5 180 5 155.5 5 155.5 MHz
×8 5 180 5 155.5 5 155.5 MHz
f
HSCLK
(input clock frequency)
×7 5 180 5 155.5 5 155.5 MHz
×4 5 180 5 155.5 5 155.5 MHz
×2 5 180 5 155.5 5 155.5 MHz
×1 5 360 5 311 5 311 MHz
×10 100 360 100 311 100 311 Mbps
×8 80 360 80 311 80 311 Mbps
Device operation in Mbps
×7 70 360 70 311 70 311 Mbps
×4 40 360 40 311 40 311 Mbps
×2 20 360 20 311 20 311 Mbps
×1 10 360 10 311 10 311 Mbps
t
DUTY
45 55 45 55 45 55 %
TCCS 200 200 200 ps
Output jitter (peak to peak)
t
RISE
t
FALL
(3)
t
LOCK
Notes to Table 1–26:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter. (2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
pin of all I/O banks.
(3) t
is the time required for the PLL to lock from the end of device configuration.
LOCK
20 – 80%, C 5pF
20 – 80%, C 5pF
500 500 550 ps
=
LOAD
LOAD
=
500 500 500 ps
500 500 500 ps
——111ms
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
(1)
(Part 1 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Unit
Min Typ Max Min Typ Max Min Typ Max
×10 5 85 5 85 5 85 MHz
×8 5 85 5 85 5 85 MHz
(input
f
HSCLK
clock frequency)
×7 5 85 5 85 5 85 MHz
×4 5 85 5 85 5 85 MHz
×2 5 85 5 85 5 85 MHz
×1 5 170 5 170 5 170 MHz
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–19
Switching Characteristics
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
(1)
(Part 2 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Min Typ Max Min Typ Max Min Typ Max
×10 100 170 100 170 100 170 Mbps
×8 80 170 80 170 80 170 Mbps Device operation in Mbps
×7 70 170 70 170 70 170 Mbps
×4 40 170 40 170 40 170 Mbps
×2 20 170 20 170 20 170 Mbps
×1 10 170 10 170 10 170 Mbps
t
DUTY
45 55 45 55 45 55 %
TCCS 200 200 200 ps
Output jitter (peak to
500 500 550 ps peak)
t
RISE
t
FALL
(2)
t
LOCK
Notes to Table 1–27:
(1) Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks. (2) t
LOCK
20 – 80%,
C
= 5 pF
LOAD
20 – 80%,
C
= 5 pF
LOAD
——111ms
is the time required for the PLL to lock from the end of device configuration.
500 500 500 ps
500 500 500 ps
Unit
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications
(1), (2)
(Part 1 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Min Typ Max Min Typ Max Min Typ Max
×10 5 200 5 155.5 5 155.5 MHz
×8 5 200 5 155.5 5 155.5 MHz
f
(input
HSCLK
clock frequency)
×7 5 200 5 155.5 5 155.5 MHz
×4 5 200 5 155.5 5 155.5 MHz
×2 5 200 5 155.5 5 155.5 MHz
×1 5 400 5 311 5 311 MHz
×10 100 400 100 311 100 311 Mbps
×8 80 400 80 311 80 311 Mbps Device operation in Mbps
×7 70 400 70 311 70 311 Mbps
×4 40 400 40 311 40 311 Mbps
×2 20 400 20 311 20 311 Mbps
×1 10 400 10 311 10 311 Mbps
t
DUTY
45 55 45 55 45 55 %
TCCS 200 200 200 ps
Unit
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–20 Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications
(1), (2)
(Part 2 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Unit
Min Typ Max Min Typ Max Min Typ Max
Output jitter (peak to
500 500 550 ps peak)
t
RISE
t
FALL
(3)
t
LOCK
Notes to Table 1–28:
(1) Applicable for true and emulated mini-LVDS transmitter. (2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
at the output pin of all I/O banks.
(3) t
LOCK
20 – 80%,
C
= 5 pF
LOAD
20 – 80%,
C
= 5 pF
LOAD
——111ms
is the time required for the PLL to lock from the end of device configuration.
500 500 500 ps
500 500 500 ps
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–21
Switching Characteristics
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications
(1)
C6 C7, I7 C8, A7
Symbol Modes
Min Max Min Max Min Max
×10 5 420 5 370 5 320 MHz
×8 5 420 5 370 5 320 MHz
f
(input
HSCLK
clock frequency)
×7 5 420 5 370 5 320 MHz
×4 5 420 5 370 5 320 MHz
×2 5 420 5 370 5 320 MHz
×1 5 420 5 402.5 5 402.5 MHz
×10 100 840 100 740 100 640 Mbps
×8 80 840 80 740 80 640 Mbps
HSIODR
×7 70 840 70 740 70 640 Mbps
×4 40 840 40 740 40 640 Mbps
×2 20 840 20 740 20 640 Mbps
×1 10 420 10 402.5 10 402.5 Mbps
t
DUTY
455545554555%
TCCS 200 200 200 ps
Output jitter (peak to peak)
(2)
t
LOCK
Notes to Table 1–29:
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). (2) t
is the time required for the PLL to lock from the end of device configuration.
LOCK
500 500 550 ps
— —1—1—1ms
Unit
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
(1)
(Part 1 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Min Max Min Max Min Max
×10 5 320 5 320 5 275 MHz
×8 5 320 5 320 5 275 MHz
f
(input
HSCLK
clock frequency)
×7 5 320 5 320 5 275 MHz
×4 5 320 5 320 5 275 MHz
×2 5 320 5 320 5 275 MHz
×1 5 402.5 5 402.5 5 402.5 MHz
×10 100 640 100 640 100 550 Mbps
×8 80 640 80 640 80 550 Mbps
HSIODR
×7 70 640 70 640 70 550 Mbps
×4 40 640 40 640 40 550 Mbps
×2 20 640 20 640 20 550 Mbps
×1 10 402.5 10 402.5 10 402.5 Mbps
t
DUTY
455545554555%
TCCS 200 200 200 ps
Unit
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–22 Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
(1)
(Part 2 of 2)
C6 C7, I7 C8, A7
Symbol Modes
Min Max Min Max Min Max
Output jitter (peak to peak)
(2)
t
LOCK
Notes to Table 1–30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks. (2) t
is the time required for the PLL to lock from the end of device configuration.
LOCK
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
500 500 550 ps
— —1—1—1ms
(1)
C6 C7, I7 C8, A7
Symbol Modes
Min Max Min Max Min Max
×10 5 437.5 5 370 5 320 MHz
×8 5 437.5 5 370 5 320 MHz
(input
f
HSCLK
clock frequency)
×7 5 437.5 5 370 5 320 MHz
×4 5 437.5 5 370 5 320 MHz
×2 5 437.5 5 370 5 320 MHz
×1 5 437.5 5 402.5 5 402.5 MHz
×10 100 875 100 740 100 640 Mbps
×8 80 875 80 740 80 640 Mbps
HSIODR
×7 70 875 70 740 70 640 Mbps
×4 40 875 40 740 40 640 Mbps
×2 20 875 20 740 20 640 Mbps
×1 10 437.5 10 402.5 10 402.5 Mbps
SW 400 400 400 ps
Input jitter tolerance
(2)
t
LOCK
Notes to Table 1–31:
(1) LVDS receiver is supported at all banks. (2) t
is the time required for the PLL to lock from the end of device configuration.
LOCK
500 500 550 ps
— —1—1—1ms
Unit
Unit

External Memory Interface Specifications

Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–23
Switching Characteristics
Tab le 1– 32 lists the FPGA sampling window specifications for Cyclone III devices.
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side
(1)
Column I/Os Row I/Os Wraparound Mode
Memory Standard
Setup Hold Setup Hold Setup Hold
C6
DDR2 SDRAM 580 550 690 640 850 800
DDR SDRAM 585 535 700 650 870 820
QDRII SRAM 785 735 805 755 905 855
C7
DDR2 SDRAM 705 650 770 715 985 930
DDR SDRAM 675 620 795 740 970 915
QDRII SRAM 900 845 910 855 1085 1030
C8
DDR2 SDRAM 785 720 930 870 1115 1055
DDR SDRAM 800 740 915 855 1185 1125
QDRII SRAM 1050 990 1065 1005 1210 1150
I7
DDR2 SDRAM 765 710 855 800 1040 985
DDR SDRAM 745 690 880 825 1000 945
QDRII SRAM 945 890 955 900 1130 1075
A7
DDR2 SDRAM 805 745 1020 960 1145 1085
DDR SDRAM 880 820 955 935 1220 1160
QDRII SRAM 1090 1030 1105 1045 1250 1190
Note to Table 1–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Tab le 1– 33 lists the transmitter channel-to-channel skew specifications for Cyclone III
devices.
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side
Memory
Standard
I/O Standard
Column I/Os (ps) Row I/Os (ps) Wraparound Mode (ps)
Lead Lag Lead Lag Lead Lag
(1)
(Part 1 of 2)
C6
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I 790 380 790 380 890 480
SSTL-18 Class II 870 490 870 490 970 590
SSTL-2 Class I 750 320 750 320 850 420
SSTL-2 Class II 860 350 860 350 960 450
1.8 V HSTL Class I 780 410 780 410 880 510
1.8 V HSTL Class II 830 510 830 510 930 610
C7
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–24 Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side
Memory
Standard
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
I/O Standard
SSTL-18 Class I 915 410 915 410 1015 510
SSTL-18 Class II 1025 545 1025 545 1125 645
SSTL-2 Class I 880 340 880 340 980 440
SSTL-2 Class II 1010 380 1010 380 1110 480
1.8 V HSTL Class I 910 450 910 450 1010 550
1.8 V HSTL Class II 1010 570 1010 570 1110 670
Column I/Os (ps) Row I/Os (ps) Wraparound Mode (ps)
Lead Lag Lead Lag Lead Lag
(1)
(Part 2 of 2)
C8
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I 1040 440 1040 440 1140 540
SSTL-18 Class II 1180 600 1180 600 1280 700
SSTL-2 Class I 1010 360 1010 360 1110 460
SSTL-2 Class II 1160 410 1160 410 1260 510
1.8 V HSTL Class I 1040 490 1040 490 1140 590
1.8 V HSTL Class II 1190 630 1190 630 1290 730
I7
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-18 Class I 961 431 961 431 1061 531
SSTL-18 Class II 1076 572 1076 572 1176 672
SSTL-2 Class I 924 357 924 357 1024 457
SSTL-2 Class II 1061 399 1061 399 1161 499
1.8 V HSTL Class I 956 473 956 473 1056 573
1.8 V HSTL Class II 1061 599 1061 599 1161 699
A7
DDR2 SDRAM
(2)
DDR SDRAM
QDRII SRAM
Notes to Table 1–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
SSTL-18 Class I 1092 462 1092 462 1192 562
SSTL-18 Class II 1239 630 1239 630 1339 730
SSTL-2 Class I 1061 378 1061 378 1161 478
SSTL-2 Class II 1218 431 1218 431 1318 531
1.8 V HSTL Class I 1092 515 1092 515 1192 615
1.8 V HSTL Class II 1250 662 1250 662 1350 762
Tab le 1– 34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications
(1), (2)
(Part 1 of 2)
Parameter Symbol Min Max Unit
Clock period jitter t
Cycle-to-cycle period jitter t
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
JIT(per)
JIT(cc)
-125 125 ps
-200 200 ps
Chapter 1: Cyclone III Device Datasheet 1–25
Switching Characteristics
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications
(1), (2)
(Part 2 of 2)
Parameter Symbol Min Max Unit
Duty cycle jitter t
Notes to Table 1–34:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard. (2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
JIT(duty)
-150 150 ps

Duty Cycle Distortion Specifications

Tab le 1– 35 lists the worst case duty cycle distortion for Cyclone III devices.
Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins
C6 C7, I7 C8, A7
Symbol
Min Max Min Max Min Max
Output Duty Cycle 455545554555 %
Notes to Table 1–35:
(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated
and general purpose I/O pins.
(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of
I/O standard and current strength.
(1), (2)
Unit

OCT Calibration Timing Specification

Tab le 1– 36 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone III devices.
Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device
Power-Up
(1)
Symbol Description Maximum Unit
t
OCTCAL
Notes to Table 1–36:
(1) OCT calibration takes place after device configuration, before entering user mode.
Duration of series OCT with calibration at device power-up

IOE Programmable Delay

Tab le 1– 37 and Table 1–38 list IOE programmable delay for Cyclone III devices.
Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins
Number
of
Settings
Min
Offset
A7, I7 C6 C6 C7 C8 I7 A7
7 0 1.211 1.314 2.175 2.32 2.386 2.366 2.49 ns
8 0 1.203 1.307 2.19 2.387 2.54 2.43 2.545 ns
Parameter
Input delay from pin to internal cells
Input delay from pin to input register
Paths
Affected
Pad to I/O dataout to core
Pad to I/O input register
(1), (2)
20 µs
(Part 1 of 2)
Max Offset
UnitFast Corner Slow Corner
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–26 Chapter 1: Cyclone III Device Datasheet

I/O Timing

Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins
(1), (2)
(Part 2 of 2)
Max Offset
Number
of
Settings
Min
Offset
Parameter
Paths
Affected
A7, I7 C6 C6 C7 C8 I7 A7
Delay from output register to output pin
Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 1–37:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.
Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins
I/O output register to pad
Pad to global clock network
2 0 0.479 0.504 0.915 1.011 1.107 1.018 1.048 ns
12 0 0.664 0.694 1.199 1.378 1.532 1.392 1.441 ns
(1), (2)
Max Offset
Number
of
Settings
Min
Offset
Parameter
Paths
Affected
A7, I7 C6 C6 C7 C8 I7 A7
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Input delay from dual-purpose clock pin to fan-out destinations
Notes to Table 1–38:
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software. (2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software
Pad to I/O dataout to core
Pad to I/O input register
I/O output register to pad
Pad to global clock network
7 0 1.209 1.314 2.174 2.335 2.406 2.381 2.505 ns
8 0 1.207 1.312 2.202 2.402 2.558 2.447 2.557 ns
2 0 0.51 0.537 0.962 1.072 1.167 1.074 1.101 ns
12 0 0.669 0.698 1.207 1.388 1.542 1.403 1.45 ns
UnitFast Corner Slow Corner
UnitFast Corner Slow Corner
I/O Timing
You can use the following methods to determine the I/O timing:
the Excel-based I/O Timing.
the Quartus II timing analyzer.
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–27
V
IL
V
REF
V
IH
VSWING

Glossary

f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone III Devices
Literature website.
Glossary
Tab le 1– 39 lists the glossary for this chapter.
Table 1–39. Glossary (Part 1 of 5)
Letter Term Definitions
A ——
B ——
C ——
D ——
E ——
F f
HSCLK
GCLK Input pin directly to Global Clock network.
G
GCLK PLL Input pin to Global Clock network through PLL.
H HSIODR HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input Waveforms for the SSTL
I
Differential I/O Standard
J JTAG Waveform
TMS
Signal
to be
Captured
Signal
to be
Driven
TDI
TCK
TDO
t
JCP
JCH
t
t
JPZX
JSZX
t
JSSU
t
JCL
t
t
JPSU_TDI
t
JPSU_TMS
t
JPCO
t
JSH
t
JSCO
t
t
JPH
JSXZ
t
JPXZ
K ——
L ——
M ——
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–28 Chapter 1: Cyclone III Device Datasheet
Core Clock
Phase tap
Reconfigurable in User Mode
Key
CLK
N
M
PFD
VCOCP LF
CLKOUT Pins
GCLK
f
INPFD
f
IN
f
VCO f
OUT
f
OUT _EXT
Switchover
Counters
C0..C4
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p - n
V
ID
Glossary
Table 1–39. Glossary (Part 2 of 5)
Letter Term Definitions
N ——
O ——
The following block diagram highlights the PLL Specification parameters.
P PLL Block
Q ——
R
L
Receiver differential input discrete resistor (external to Cyclone III devices).
Receiver Input Waveform for LVDS and LVPECL Differential Standards.
Receiver Input Waveform
R
RSKM (Receiver input skew margin)
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2.
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–29
V
IH(AC
)
V
IH(D C)
V
REF
V
IL(DC)
V
IL(AC
)
V
OH
V
OL
V
CCIO
V
SS
Glossary
Table 1–39. Glossary (Part 3 of 5)
Letter Term Definitions
Single-ended Voltage referenced I/O
S
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing.
SW (Sampling Window)
t
C
TCCS (Channel­to-channel-skew)
HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window.
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges, including t
variation and clock skew. The clock is included in the TCCS measurement.
CO
tcin Delay from clock pad to I/O input register.
t
CO
Delay from clock pad to I/O output.
tcout Delay from clock pad to I/O output register.
T
t
DUTY
t
FALL
t
H
Timing Unit Interval (TUI)
t
INJITTER
t
OUTJITTER_DEDCLK
t
OUTJITTER_IO
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
C
/w).
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
tpllcin Delay from PLL inclk pad to I/O input register.
tpllcout Delay from PLL inclk pad to I/O output register.
Volume 2
July 2012 Altera Corporation Cyclone III Device Handbook
1–30 Chapter 1: Cyclone III Device Datasheet
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
OH
Negative Channel (n) = V
OL
Ground
V
OD
V
OD
V
OD
0 V
V
os
p - n
Glossary
Table 1–39. Glossary (Part 4 of 5)
Letter Term Definitions
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O Standards
Transmitter Output Waveform
t
t
RISE
SU
Signal Low-to-high transition time (20–80%).
Input register setup time.
U ——
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–31
Glossary
Table 1–39. Glossary (Part 5 of 5)
Letter Term Definitions
V
CM(DC)
V
DIF(AC)
V
DIF(DC)
V
ICM
V
ID
V
IH
V
IH(AC)
V
IH(DC)
V
IL
V
IL (AC)
V
IL (DC)
V
IN
V
OCM
V
OD
V
V
OH
V
OL
V
OS
V
OX (AC)
V
REF
V
REF (AC)
V
REF (DC)
V
SWING (AC)
V
SWING (DC)
V
TT
V
X (AC)
DC Common Mode Input Voltage.
AC differential Input Voltage: The minimum AC input differential voltage required for switching.
DC differential Input Voltage: The minimum DC input differential voltage required for switching.
Input Common Mode Voltage: The common mode of the differential signal at the receiver.
Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver.
Voltage Input High: The minimum positive voltage applied to the input which is accepted by the device as a logic high.
High-level AC input voltage.
High-level DC input voltage.
Voltage Input Low: The maximum positive voltage applied to the input which is accepted by the device as a logic low.
Low-level AC input voltage.
Low-level DC input voltage.
DC input voltage.
Output Common Mode Voltage: The common mode of the differential signal at the transmitter.
Output differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. V
= VOH – VOL.
OD
Voltage Output High: The maximum positive voltage from an output which the device considers is accepted as the minimum positive high level.
Voltage Output Low: The maximum positive voltage from an output which the device considers is accepted as the maximum positive low level.
Output offset voltage: VOS = (VOH + VOL) / 2.
AC differential Output cross point voltage: The voltage at which the differential output signals must cross.
Reference voltage for SSTL, HSTL I/O Standards.
AC input reference voltage for SSTL, HSTL I/O Standards. V peak-to-peak AC noise on V
should not exceed 2% of V
REF
REF(AC)
REF(DC)
.
= V
REF(DC)
+ noise. The
DC input reference voltage for SSTL, HSTL I/O Standards.
AC differential Input Voltage: AC Input differential voltage required for switching. For the SSTL Differential I/O Standard, refer to Input Waveforms.
DC differential Input Voltage: DC Input differential voltage required for switching. For the SSTL Differential I/O Standard, refer to Input Waveforms.
Termination voltage for SSTL, HSTL I/O Standards.
AC differential Input cross point Voltage: The voltage at which the differential input signals must cross.
W ——
X ——
Y ——
Z ——
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–32 Chapter 1: Cyclone III Device Datasheet

Document Revision History

Document Revision History
Tab le 1– 40 lists the revision history for this document.
Table 1–40. Document Revision History (Part 1 of 3)
Date Version Changes
July 2012 3.5 Updated minimum f
Updated “Supply Current” on page 1–5 and “Periphery Performance” on page 1–17.
December 2011 3.4
Updated Table 1–3, Table 1–4, Table 1–13, Table 1–16, Table 1–17, Table 1–20, and
Table 1–25.
January 2010 3.3
Removed Table 1-32 and Table 1-33.
Added Literature: External Memory Interfaces reference.
December 2009 3.2 Minor changes to the text.
July 2009 3.1 Minor edit to the hyperlinks.
Changed chapter title from DC and Switching Characteristics to “Cyclone III Device Data
Sheet” on page 1–1.
Updated (Note 1) to Table 1–23 on page 1–17.
Updated “External Memory Interface Specifications” on page 1–23.
June 2009 3.0
October 2008 2.2
Replaced Table 1–32 on page 1–23.
Replaced Table 1–33 on page 1–23.
Added Table 1–36 on page 1–26.
Updated “I/O Timing” on page 1–28.
Removed “Typical Design Performance” section.
Removed “I/O Timing” subsections.
Updated chapter to new template.
Updated Table 1–1, Table 1–3, and Table 1–18.
Added (Note 7) to Table 1–3.
Added the “OCT Calibration Timing Specification” section.
Updated “Glossary” section.
Updated Table 1–38.
Added BLVDS information (I/O standard) into Table 1–39, Table 1–40, Table 1–41,
Table 1–42.
July 2008 2.1
Updated Table 1–43, Table 1–46, Table 1–47, Table 1–48, Table 1–49, Table 1–50,
Table 1–51, Table 1–52, Table 1–53, Table 1–54, Table 1–55, Table 1–56, Table 1–57, Table 1–58, Table 1–59, Table 1–60, Table 1–61, Table 1–62, Table 1–63, Table 1–68, Table 1–69, Table 1–74, Table 1–75, Table 1–80, Table 1–81, Table 1–86, Table 1–87, Table 1–92, Table 1–93, Table 1–94, Table 1–95, Table 1–96, Table 1–97, Table 1–98, and Table 1–99.
value to 5 MHz.
HSCLK
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
Chapter 1: Cyclone III Device Datasheet 1–33
Document Revision History
Table 1–40. Document Revision History (Part 2 of 3)
Date Version Changes
Updated “Operating Conditions” section and included information on automotive device.
Updated Table 1–3, Table 1–6, and Table 1–7, and added automotive information.
Under “Pin Capacitance” section, updated Table 1–9 and Table 1–10.
Added new “Schmitt Trigger Input” section with Table 1–12.
Under “I/O Standard Specifications” section, updated Table 1–13, 1–12 and 1–12.
May 2008 2.0
Under “Switching Characteristics” section, updated Table 1–19, 1–15, 1–16, 1–16, 1–17,
1–18, 1–19, 1–20, 1–21, 1–21, 1–23, 1–23, 1–23, 1–24, and 1–25.
Updated Figure 1–5 and 1–29.
Deleted previous Table 1-35 “DDIO Outputs Half-Period Jitter”.
Under “I/O Timing” section, updated Table 1–38, 1–29, 1–32, 1–33, 1–26, and 1–26.
Under “Typical Design Performance” section updated Table 1–46 through 1–145.
Under “Core Performance Specifications”, updated Tables 1-18 and 1-19.
Under “Preliminary, Correlated, and Final Timing”, updated Table 1-37.
December 2007 1.5
Under “Typical Design Performance”, updated Tables 1-45, 1-46, 1-51, 1-52, 1-57, 1-58,
Tables 1-63 through 1-68. 1-69, 1-70, 1-75, 1-76, 1-81, 1-82, Tables 1-87 through 1-92, Tables 1-99, 1-100, 1-107, and 1-108.
October 2007 1.4
Updated the C
Updated Table 1-21.
Under “High-Speed I/O Specification” section, updated Tables 1-25 through 1-30.
Updated Tables 1-31 through 1-38.
Added new Table 1-32.
Under “Maximum Input and Output Clock Toggle Rate” section, updated Tables 1-40
value in Table 1-9.
VREFTB
through 1-42.
Under “IOE Programmable Delay” section, updated Tables 1-43 through 1-44.
Under “User I/O Pin Timing Parameters” section, updated Tables 1-45 through 1-92.
Under “Dedicated Clock Pin Timing Parameters” section, updated Tables 1-93 through 1-
108.
July 2007 1.3
Updated Table 1-1 with V
Updated R
Added Note (3) to Table 1-12.
Updated t
Updated Table 1-43 and Table 1-44.
Added “Document Revision History” section.
information in Tables 1-10.
CONF_PD
information in Table 1-19.
DLOCK
ESDHBM
and V
ESDCDM
information.
June 2007 1.2 Updated Cyclone III graphic in cover page.
July 2012 Altera Corporation Cyclone III Device Handbook
Volume 2
1–34 Chapter 1: Cyclone III Device Datasheet
Document Revision History
Table 1–40. Document Revision History (Part 3 of 3)
Date Version Changes
Corrected current unit in Tables 1-1, 1-12, and 1-14.
Added Note (3) to Table 1-3.
May 2007 1.1
Updated Table 1-4 with I
Updated Table 1-9 and added Note (2).
Updated Table 1-19.
Updated Table 1-22 and added Note (1).
Changed I/O standard from 1.5-V LVTTL/LVCMOS and 1.2-V LVTTL/LVCMOS to 1.5-V
CCINT0
, I
CCA0
, I
CCD_PLL0
, and I
information.
CCIO0
LVCMOS and 1.2-V LVCMOS in Tables 1-41, 1-42, 1-43, 1-44, and 1-45.
Updated Table 1-43 with changes to LVPEC and LVDS and added Note (5).
Updated Tables 1-46, 1-47, Tables 1-54 through 1-95, and Tables 1-98 through 1-111.
Removed speed grade –6 from Tables 1-90 through 1-95, and from Tables 1-110 through
1-111.
Added a waveform (Receiver Input Waveform) in glossary under letter “R” (Table 1-112).
March 2007 1.0 Initial release.
Cyclone III Device Handbook July 2012 Altera Corporation Volume 2
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