Altera Cyclone II DSP Development Board User Manual
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
www.altera.com
Cyclone II DSP Development Board
Reference Manual
Document Version: 6.0.1
Document Date: August 2006
Copyright © 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera
Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
MNL-CII012805-1.1
ii Reference Manual Altera Corporation
Cyclone II DSP Development Board Preliminary August 2006
Contents
About This Manual
Revision History ........................................................................................................................................ v
How to Contact Altera .............................................................................................................................. v
Typographic Conventions ...................................................................................................................... vi
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features Overview ................................................................................................................................. 1–1
Components ...................................................................................................................................... 1–1
Chapter 2. Cyclone II DSP Development Board Components
Introduction ............................................................................................................................................ 2–1
Components & Interfaces ..................................................................................................................... 2–1
Featured Device ..................................................................................................................................... 2–9
User Interfaces ........................................................................................................................................ 2–9
User-Defined LEDs (D2 Through D9) ......................................................................................... 2–10
User Defined DIP Switch (S1) ....................................................................................................... 2–11
User-Defined Pushbuttons (SW2 Through SW5) ...................................................................... 2–12
Seven-Segment Display (U32,U33) .............................................................................................. 2–13
Audio CODEC Converter (U11) .................................................................................................. 2–14
Audio Jacks (J10, J14, J16) .............................................................................................................. 2–14
VGA Output Connector (J21) ....................................................................................................... 2–15
VGA Triple Video D/A Output Converter (U21) ..................................................................... 2–15
D/A Converter SMA Connector (J31 & J43) .............................................................................. 2–17
D/A Converter Clock Buffer (U27 & 30) .................................................................................... 2–17
D/A Converter (U25 & U30) ........................................................................................................ 2–17
A/D Converter Data Format Select Jumper (J30 & J38) ........................................................... 2–21
A/D Converter SMA Connector (J32 & J44) .............................................................................. 2–21
A/D Converter Clock Buffer (U29 & U28) ................................................................................. 2–22
A/D Converter (U26 & U31) ........................................................................................................ 2–22
Memory Components ......................................................................................................................... 2–26
DDR2 SDRAM DIMM (J8) ............................................................................................................2–26
DIMM_SYNC_CLK SMA Connector (J11) ................................................................................. 2–36
SSRAM Sleep & Run Modes (J24) ................................................................................................ 2–37
EPCS Select (J29) ............................................................................................................................. 2–37
EPCS64 Flash Memory Devices (U17, U36) ................................................................................ 2–38
Synchronous SRAM Device (U22) ............................................................................................... 2–39
Memory Mapping to the TMS320C6416 Digital Signal Processor .......................................... 2–42
Expansion Connectors ........................................................................................................................ 2–43
Expansion Prototype Connector (J15, J22 & J23) ....................................................................... 2–43
Expansion TI-EVM Connectors (U34, U40) ................................................................................ 2–47
Altera Corporation Reference Manual iii
August 2006 Cyclone II DSP Development Board
Contents
General Connectors ............................................................................................................................. 2–50
JTAG Connector (J9) ...................................................................................................................... 2–50
Active Serial Interface (ASI) Connector (J13) ............................................................................. 2–52
Mictor Connector (J12) ................................................................................................................... 2–53
Status LEDs & Reset/Power Switches ..............................................................................................2–57
Power (D1) & Status (D10) LEDs ................................................................................................. 2–57
Power Switch (SW1) ....................................................................................................................... 2–57
User Defined Reset (SW6) Push-Button ...................................................................................... 2–57
System Reset (SW7) Push-Button ................................................................................................. 2–58
Clock Circuitry ..................................................................................................................................... 2–59
Setting the Clocks ........................................................................................................................... 2–60
CLK SMA Connector (J17) ............................................................................................................ 2–61
On-Board/Custom Clock Oscillators Select Jumper (J18) ........................................................ 2–61
Clock Select Jumper (J19) .............................................................................................................. 2–62
Socket for a Custom Clock Oscillator (J20) ................................................................................. 2–62
D/A Converter CLK SMA Connector (J26) ................................................................................ 2–62
A/D Converter CLK SMA Connector (J27) ................................................................................ 2–62
D/A Converter CLK Select Jumper (J35 & J34) ......................................................................... 2–62
A/D Converter CLK Select Jumper (J37 & J36) ......................................................................... 2–62
D/A Converter Power Select Jumper (J33) ................................................................................ 2–63
Clock Buffer (U16) .......................................................................................................................... 2–64
On-Board Clock Oscillator (U20) .................................................................................................2–64
Power Supply ....................................................................................................................................... 2–65
DC Power Input Jack (J1) .............................................................................................................. 2–65
Voltage Limiter Switches (U13-U15, U18 & U19) ...................................................................... 2–66
On-Board Power Regulators (U2, U7, U8, U9, U10, U23 & U24) ............................................ 2–66
Bench Power Supplies Using Banana Jacks ................................................................................ 2–67
Power Plane Connectors (J2-J6, J39 Through J42) ...................................................................... 2–69
Appendix A. DDR2 SDRAM DIMM Connector Pin Out Table
Introduction ........................................................................................................................................... A–1
Appendix B. SSRAM Pin-Out Table
Introduction ........................................................................................................................................... B–1
Appendix C. Cyclone II EP2C70 Device Pin-Out Table
Introduction ........................................................................................................................................... C–1
Appendix D. Restoring the Factory Design
Introduction ........................................................................................................................................... D–1
Factory-Programmed Factory Design .......................................................................................... D–1
User Designs .................................................................................................................................... D–1
Reprogramming the Factory Design to the EPSC64 Device (U17) .......................................... D–1
iv Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
About This Manual
Revision History
Chapter Date Version Changes Made
All May 2005 1.0.0 First publication
All August 2006 6.0.1 Updated for Quartus II Release 6.0 Service Pack 1
How to Contact Altera
Information Type USA & Canada All Other Locations
Technical support www.altera.com/mysupport/ www.altera.com/mysupport/
Product literature www.altera.com www.altera.com
Altera literature services lit_req@altera.com lit_req@altera.com
Non-technical customer
service
FTP site ftp.altera.com ftp.altera.com
The table below displays the revision history for the chapters in this
manual.
For technical support or other information about Altera® products, go to
the Altera world-wide web site at www.altera.com. You can also contact
Altera through your local sales representative or any of the sources listed
below.
800-800-EPLD (3753)
7:00 a.m. to 5:00 p.m. Pacific Time
800-767-3753 + 1 408-544-7000
+1 408-544-8767
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
7:00 a.m. to 5:00 p.m. (GMT -8:00)
Pacific Time
Altera Corporation Reference Manual v
August 2006 Cyclone II DSP Development Board
Typographic Conventions
Typographic
This document uses the typographic conventions shown below.
Conventions
Visual Cue Meaning
Bold Type with Initial
Capital Letters
bold type External timing parameters, directory names, project names, disk drive names,
Italic Type with Initial
Capital Letters
Italic type Internal timing parameters and variables are shown in italic type.
Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters.
“Subheading Title” References to sections within a document and titles of on-line help topics are shown
Courier type
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters.
Example: Save As dialog box.
filenames, filename extensions, and software utility names are shown in bold type.
Examples: f
Document titles are shown in italic type with initial capital letters.
Example: AN 75: High-Speed Board Design.
Examples: t
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example:
<file name>, <project name>.pof file.
Examples: Delete key, the Options menu.
in quotation marks.
Example: “Typographic Conventions.”
Signal and port names are shown in lowercase Courier type.
Examples:
Active-low signals are denoted by suffix
, \qdesigns directory, d: drive, chiptrip.gdf file.
MAX
, n + 1.
PIA
data1, tdi, input.
n, for example, resetn.
Anything that must be typed exactly as it appears is shown in Courier type (for
example:
Also, sections of an actual file, such as a Report File, references to parts of files (for
example, the AHDL keyword
example,
1., 2., 3., and
a., b., c., and so on
● • Bullets are used in a list of items when the sequence of the items is not important.
■
v The checkmark indicates a procedure that consists of one step only.
1 The hand points to information that requires special attention.
c
w
r The angled arrow indicates you should press the Enter key.
f The feet direct you to more information on a particular topic.
vi Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the procedure or
process.
The warning indicates information that should be read prior to starting or continuing
the procedure or processes
c:\qdesigns\tutorial\chiptrip.gdf.
SUBDESIGN), as well as logic function names (for
TRI) are shown in Courier.
Chapter 1. Introduction
Introduction
Features Overview
This document describes the hardware features of the Cyclone™ II DSP
development board, including detailed pin-out information, to enable
designers to create custom FPGA designs that interface with all
components on the board.
f For information on setting up and powering up the Cyclone II DSP
development board and installing the included software, refer to the
DSP Development Kit, Cyclone II Edition Getting Started User Guide.
The Cyclone II DSP development board is included in the
DSP Development Kit, Cyclone II Edition (ordering code DK-DSP-2C70N).
The Cyclone II DSP development board provides a low-cost hardware
platform for developing high performance DSP designs based on Altera
Cyclone II FPGA devices. The DSP Development Kit, Cyclone II Edition
features the EP2C70F672 FPGA.
Components
■ Analog I/O
● Two 14-bit analog-to-digital (A/D) converter channels with
125 MSPS and 70 dB signal-to-noise ratio capabilities
● Two 14-bit digital-to-analog (D/A) converter channels with
165 MSPS and 70 dB signal-to-noise ratio capabilities
● One 24-bit RGB VGA adapter with a DB-15 connector
● One Audio CODEC with input, output, and amplified output
■ Memory Subsystem
● 256 Mbyte DDR2 SDRAM DIMM
● 1 Mbyte synchronous SRAM (SSRAM)
■ Two EPCS64 64 Mbit serial configuration devices
■ Debugging Interface—Mictor connector for hardware and software
debugging
■ Expansion Interfaces
● 3.3-V/5-V tolerant Altera expansion/prototype headers
● One Texas Instruments Evaluation Module (TI-EVM) expansion
connector to connect to the Spectrum Digital DSP Starter Kit
(DSK) for the TMS320C6416, Revision E
■ Dual seven-segment LED displays
■ Eight user-defined LEDs
®
Altera Corporation Reference Manual 1–1
August 2006 Preliminary
Features Overview
■ One user programmable dual in-line package (DIP) switch
(8 positions)
■ Four user-defined push-buttons
Figure 1–1 shows a functional diagram of the Cyclone II DSP
development board.
Figure 1–1. Cyclone II DSP Development Board Functional Diagram
Channel A
Channel B
Connector
Altera Daughter Card
SMA
SMA
SMA
SMA
DB-15
Seven-Segment Display
TI-EVM Connector
256K X 36 SSRAM
100-MHz
On-Board Oscillator
Custom Oscillator
Mictor Connector
A/D
Converter
D/A
Converter
A/D
Converter
D/A
Converter
VGA
DDR2
14
14
14
Cyclone II
FPGA
14
24
75
32
41
SDRAM DIMM
JTAG Connector
ASI Connector
Audio CODEC
User-Defined
LEDs
User-Defined
Pushbuttons
User-Defined
Dipswitches
Flash Memory
Safe Mode
Flash Memory
User Mode
1–2 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Chapter 2. Cyclone II DSP
Development
Board Components
Introduction
Components & Interfaces
f Software and hardware installation and setup are described in the DSP
This chapter describes the Cyclone II DSP development board
components.
This section introduces the major components on the Cyclone II DSP
development board by first listing them in Table 2–1 on page 2–4. A
detailed description of each component comprises the remainder of this
chapter.
1 A schematic, a physical layout database, and manufacturing
files for the Cyclone II DSP development board are included in
the DSP Development Kit, Cyclone II Edition at the following
directory:
<install-path>\CycloneII_DSP_Kit-v6.0.1\BoardDesignFiles
Development Kit, Cyclone II Edition Getting Started User Guide.
Altera Corporation Reference Manual 2–1
August 2006 Preliminary
Components & Interfaces
)
Figure 2–1 shows the front view of the Cyclone II DSP development
board.
Figure 2–1. Cyclone II DSP Development Board, Front View
Power Switch (SW1)
Power LED (D1)
Single Slot DDR2
SDRAM DIMM Connector (J8)
GND Connector (J2)
DC Power Jack (J1)
On-Board Power
Regulator (U9)
Line In Audio Jack (J10)
DIMM SYNC CLK
SMA Connector (J11)
Audio CODEC Converter (U11)
Line Out Audio Jack (J14)
CLK SMA Connector (J17)
Headphone Jack (J16)
Clock Oscillator Select Jumper (J18)
D/A Converter Clock SMA Connector (J26)
Clock Buffer (U16)
Clock Select Jumper (J19)
VGA Output Connector (J21)
DAC Power Supply Jumper (J25)
VGA Triple Video D/A
Output Converter (U21)
SSRAM (U22)
SMA to D/A Output
Converter Connector (J31)
D/A Output Converter (U25)
DAC PWR Jumper (J33)
DAC Clock Select Jumper (J35)
VCCA DAC (J39)
On-Board Power Regulator (U23)
Custom Clock Oscillator Socket (J20)
On-Board Clock Oscillator (U20)
User-Defined Push-Button Switches
(SW2, SW3, SW4, SW5)
User-Defined LEDs (D2, D3, D4, D5, D6, D7, D8, D9)
(Overlay)
SSRAM SLEEP Mode or RUN Mode Jumper (J24)
Power Plane Connector (J3)
DAC Clock Buffer (U27)
Cyclone II FPGA (U12)
User-Defined DIP Switch (S1)
On-Board Power
Regulator (U2)
Unused (J36)
User-Defined Reset Push-Button (SW6)
Power Plane Connectors (J4, J5)
System Reset Push-Button (SW7)
ADC Clock Select Jumper (J37)
ADC Differential LVPECL Buffer (U29)GND DAC (J40)
Dual Seven-Segment Display (U32, U33)Unused (J34)
On-Board Power Regulator (U7)
Power Plane Connector (J6)
Bench Power Supply
Select Jumper (J7)
On-Board Power
Regulators (U8, U10)
JTAG Connector (J9)
Mictor Connector (J12)
ASI Connector (J13)
Expansion Prototype
Connector (J15)
Voltage Limiter Switches
(U13, U14, U15, U18, U19)
SAFE EPCS (U17)
(Flash Memory)
Expansion Prototype
Connectors (J22, J23)
A/D Converter Clock
SMA Connector (J27)
EPCS Select Jumper (J29)
ADC PWR Jumper (J28)
DFS Jumper (J30)
SMA to A/D Input
Converter Connector (J32)
A/D Input Converter (U26)
On-Board Power Regulator (U24
VCCA ADC (J42)
GND ADC (J41)
Status LED (D10)
(CONF DONE)
2–2 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Figure 2–2 shows the back view of the Cyclone II DSP development
board.
Figure 2–2. Cyclone II DSP Development Board, Back View
USER EPCS (U36)
(Flash Memory)
(1) For Spectrum Digital DSP Starter Kit
TI-EVM PERIPHERAL Expansion Connector U34 (1)
TI-EVM MEMORY Expansion Connector U40 (1)
Altera Corporation Reference Manual 2–3
August 2006 Cyclone II DSP Development Board
Components & Interfaces
Table 2–1 describes the major components on the Cyclone II DSP
development board and the related interfaces.
Table 2–1. Cyclone II DSP Development Board Components & Interfaces (Part 1 of 5)
Board Reference Name Description Page
Featured Device 2–9
U12 Cyclone™ II FPGA EP2C70F672-C6 2–9
User Interfaces 2–9
D2, D3, D4, D5, D6, D7,
D8, D9
S1 User-defined DIP
SW2, SW3, SW4, SW5 User-defined
U32, U33 Dual seven-segment
J10 Line-in audio jack Audio input connector for line-in (2.5 mm). 2–14
J14 Line-out audio jack Audio output connector for line-out (2.5 mm).
J16 Headphone jack Amplified audio output connector for
U11 Audio CODEC
J21 VGA output
U21 VGA triple video D/A
J31 (Channel A)
J43 (Channel B)
J26 (Channel A & B) D/A converter CLK
U25 (Channel A)
U30 (Channel B)
J32 (Channel A)
J44 (Channel B)
J27 (Channel A & B) A/D converter CLK
U26 (Channel A)
U31 (Channel B)
User-defined LEDs Eight user-defined LEDs. 2–10
One User-defined octal DIP switch. 2–11
switch
User-defined momentary-contact push-button
push-button switches
display
converter
connector
output converter
D/A converter output
SMA connector
SMA connector
D/A converter Texas Instruments DAC904E 14-bit
A/D converter input
SMA connector
SMA connector
A/D converter Texas Instruments ADS5520 12-bit 125 MSPS
switches.
Dual seven-segment display. 2–13
headphones (2.5 mm).
Texas Instruments TLV320AIC23 96 kHz stereo
audio CODEC.
VGA output connector (DB-15). 2–15
Fairchild FMS3818 triple video D/A output
converter.
SMA connector which is driven by the output of
the Channel A D/A converter (U25).
SMA connector for an external D/A converter
clock input to U25.
digital-to-analog (D/A) converter.
SMA connector which drives the Channel A A/D
converter (U26).
SMA connector for an external A/D converter
clock input to U26.
analog-to-digital (A/D) converter.
2–12
2–14
2–15
2–17
2–62
2–17
2–21
2–62
2–22
2–4 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Table 2–1. Cyclone II DSP Development Board Components & Interfaces (Part 2 of 5)
Board Reference Name Description Page
Memory Components 2–26
J8 Single slot connector
for DDR2 SDRAM
DIMM
U17, U36 EPCS64 flash
memory
U22 SSRAM Cypress Semiconductor CY7C1360B-166AC,
Micron Technology MT8HTF3264AY-40E,
256 Mbyte, 32 Mbyte x 64, 167 MHz, 1.8 V,
240-pin, non-ECC, unbuffered DDR2 SDRAM
DIMM.
Two EPCS64 64 Mbit flash memory, serial
configuration devices used to store the safe
(factory) design (U17) and a user design (U36).
The EPCS64 device configures the EP2C70
FPGA by downloading the factory design or the
user design to the EP2C70 FPGA each time the
Cyclone II DSP development board powers up
or on board reset. J29 determines which design
is used.
9 Mbit, 256 Kbit x 36-bit/512 Kbit x 18 pipelined
synchronous SRAM (SSRAM).
The TMS320C6416 processor memory maps to
the Cyclone II DSP development board’s
SSRAM and the EP2C70 FPGA through the
EMIF connector (U34 and U40).
Expansion Connectors
J15, J22, J23 Expansion Prototype
Connector
U34, U40 Expansion TI-EVM
connectors
Three connectors collectively called the
Expansion Prototype Connector. They are used
to connect to Altera daughter cards or for
debugging and prototyping purposes.
Connects to the EMIF connector on the
TMS320C6416 DSK development board.
U34 and U40 are located on the back of the
Cyclone II DSP development board.
General Connectors
J9 JTAG connector The Joint Test Action Group (JTAG) connector
J13 ASI connector The active serial interface (ASI) connector is
J12 Mictor connector The Mictor connector used for hardware and
J17 CLK SMA connector SMA connector for an external clock input to
is used to directly configure the EP2C70 FPGA.
used to program the EPCS64.
software debugging. It can be used with
external scopes or external logic analyzers.
U16 to generate FPGA clocks.
2–26
2–38
2–39
2–42
2–43
2–43
2–47
2–50
2–50
2–52
2–53
2–61
Altera Corporation Reference Manual 2–5
August 2006 Cyclone II DSP Development Board
Components & Interfaces
Table 2–1. Cyclone II DSP Development Board Components & Interfaces (Part 3 of 5)
Board Reference Name Description Page
J11 DIMM_SYNC_CLK
SMA connector
The SMA connector (
test point SMA for eye diagrams of DDR2
signals using AC-coupled SMA connections to
an oscilloscope.
DIMM_SYNC_CLK) is a
Jumpers
J18 On-board or custom
clock oscillator select
jumper
J19 Clock select jumper Jumper that determines which input to U16 (the
J24 SSRAM SLEEP
mode or RUN mode
jumper
J7 5 V enable/disable
jumper for U10
J25 D/A converter power
J28 A/D converter power
J33 D/A converter voltage
J29 EPCS select jumper Jumper that selects the configuration mode
J30 (Channel A)
J38 (Channel B)
J35 (Channel A)
J34 (Channel B)
J37 (Channel A)
J36 (Channel B)
supply jumper
supply jumper
select jumper
Data Format Select
(DFS) jumper
D/A converter clock
select jumper
A/D converter clock
select jumper
Jumper that determines if the on-board clock
100 MHz oscillator (U20) or a custom clock
oscillator (J20) becomes the input clock
oscillator to the clock buffer (U16).
selected clock oscillator or the SMA clock) will
be used to determine the clock outputs of U16.
Jumper that selects SLEEP mode or RUN mode
on the SSRAM.
J7 disables the on-board 5-volt voltage
regulator (U10) output to eliminate all regulatorbased noise.
Jumper that selects whether the D/A converter
is powered from the DC input jack or the bench
power supply connector (J39 and J40).
Jumper that selects whether the A/D converter
is powered from the DC input jack or the bench
power supply connector (J42 and J41).
Jumper that determines whether the D/A
converter is powered at 3.3 volts or 5.0 volts.
(SAFE EPCS or USER EPCS)
Data Format Select (DFS) jumper selects the
data output format from the Texas Instruments
ADS5520 A/D converter (U26 and U31). There
are four data output formats.
D/A Converter Channel A clock select jumper. It
determines the D/A converter clock from three
input clock signals, the OSC clock, the FPGA
D/A converter clock, or the SMA clock (J26).
A/D converter Channel A clock select jumper. It
determines the A/D converter clock from three
input clock signals, the OSC clock, the FPGA
A/D converter clock, or the SMA clock (J27).
2–36
2–61
2–62
2–37
2–69
2–70
2–70
2–63
2–37
2–21
2–62
2–62
2–6 Reference Manual Altera Corporation
Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Table 2–1. Cyclone II DSP Development Board Components & Interfaces (Part 4 of 5)
Board Reference Name Description Page
Status LEDs & Reset/Power Switches 2–57
D1 Power LED Indicates when power is present. 2–57
D10 Status LED Indicates successful configuration of the
Cyclone II DSP development board
(
CONFIG_DONEn is asserted).
SW1 Power switch Power switch that is used to apply power to the
on-board power regulators.
SW6 User-defined reset
push-button
SW7 System reset
push-button
Clocks 2–59
J20 Socket for connecting
custom clock
oscillator
U16 Clock buffer U16 is the clock buffer for the five clocks on the
U20 On-board clock
oscillator
U27 D/A converter clock
buffer
U29 A/D converter
differential LVPECL
buffer
U28 A/D converter
differential LVPECL
buffer
USER RESET is user-defined
momentary-contact push-button used to reset
and initialize a user design on the Cyclone II
DSP development board.
SYS RESET is a momentary-contact pushbutton used to reset the hardware and configure
the Cyclone II DSP development board with the
design stored in the EPCS64 selected by J29.
Socket on top of U20 where a half-can clock
oscillator can be installed. It is referred to as the
custom clock oscillator. It can be an input to
U16.
Cyclone II DSP development board.
The on-board clock oscillator is the ECS, Inc.
ECS-3953M-1000-BN-TR 100 MHz surface
mount oscillator. It can be an input to U16.
U27 uses the DAC_A clock selected by J35 and
inputs it to U25, and uses the DAC_B clock
selected by J34 and inputs it to U30.
U29 uses the ADC_A clock selected by J37 and
inputs it to U26.
U28 uses the ADC_B clock selected by J36 and
inputs it to U31.
2–57
2–57
2–58
2–62
2–64
2–64
2–17
2–22
2–22
Altera Corporation Reference Manual 2–7
August 2006 Cyclone II DSP Development Board
Components & Interfaces
Table 2–1. Cyclone II DSP Development Board Components & Interfaces (Part 5 of 5)
Board Reference Name Description Page
Powe r S up ply 2–65
J1 DC power jack 9-20 V DC power source.
U13, U14, U15, U18, U19 Voltage limiter
switches
U2, U7, U8, U9, U10,
U23, U24
J2, J3, J4, J5, J6, J39,
J40, J41, J42
On-board power
regulators
Power plane
connectors
For information on powering up and testing the
Cyclone II DSP development board, see
“Cyclone II DSP Development Board Power-Up”
on page 2–65. For isolating and testing the
power planes, see “Bench Power Supplies
Using Banana Jacks” on page 2–67.
10-bit, 2-port bus switch. 2–66
Seven voltage regulators on the Cyclone II DSP
development board.
Connectors for bench power supplies. 2–69
2–65
2–66
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Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Featured Device
f For details about configuring the EP2C70 FPGA, see the Getting Started
The DSP Development Kit, Cyclone II Edition features the EP2C70F672
®
FPGA (U12) in a 672-pin FineLine BGA
package. Table 2–2 lists the
“Power Switch (SW1)” on page 2–57features of this device.
Table 2–2. Cyclone II EP2C70F672 Features
Feature Value
Embedded 18x18 multipliers 150
Logic Elements (LEs) 68,416
M4K RAM blocks (4 Kbits + 512 parity bits) 250
Maximum differential channels 262
PLLs 4 PLLs
Total RAM bits 1,152,000
User I/O pins 422
You can configure the FPGA in one of two ways:
■ Use Quartus II to program a SRAM Object file (SOF) file directly into
the FPGA via the JTAG connector.
chapter in the DSP Development Kit, Cyclone II Edition Getting Started User
Guide.
■ Use Quartus II to load a design into the EPCS64 device via the ASI
connector and then cycle power to load the design from the EPCS64
device into the FPGA.
There are two EPCS64 devices, J29 determines which EPCS64 device
loads the FPGA. Refer to “EPCS64 Flash Memory Devices (U17,
U36)” on page 2–38 for more information.
User Interfaces
This section describes the user interfaces, which consist of LEDs,
switches, push-buttons, seven-segment display, line in, line out, audio
and headphone jacks, VGA, D/A converter, and A/D converter.
Altera Corporation Reference Manual 2–9
August 2006 Cyclone II DSP Development Board
User Interfaces
User-Defined LEDs (D2 Through D9)
The Cyclone II DSP development board provides eight user-defined
LEDs. D2 through D9 are connected to general purpose I/O pins on the
EP2C70 FPGA as listed in Table 2–3. When the EP2C70 FPGA drives logic
0, the corresponding LED turns on.
Table 2–3. User-Defined LED Pin-Outs
LED
Number
7D2
6D3
5D4
4D5
3D6
2D7
1D8
0D9
Board
Reference
Schematic Signal
Name
USER_LED7 AA7
USER_LED6 AA6
USER_LED5 AB4
USER_LED4 AC3
USER_LED3 E22
USER_LED2 F20
USER_LED1 B3
USER_LED0 E5
Figure 2–3 shows the user-defined LEDs.
Figure 2–3. User-Defined LED0 Through LED7
Cyclone II (U12) Pin
Number
7 D26 D35 D44 D53 D62 D71 D80
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Cyclone II DSP Development Board August 2006
D9
Cyclone II DSP Development Board Components
User Defined DIP Switch (S1)
S1 is a user-defined octal DIP switch available for general-purpose use. It
must be defined by the user before it can be used. In the open position,
the selected signal is driven to logic 1. In the closed position, the selected
signal is driven to logic 0. Table 2–4 lists the pin-outs of the user DIP
switch. Figure 2–4 shows the switch labels on the switch, the labels on the
printed circuit board (PCB), and shows the open and closed switch
positions.
Table 2–4. User-Defined Dipswitch Pin-Outs
DIP Switch
Label
10
21
32
43
54
65
76
87
Board
Reference
Schematic Signal
USER_DIPSW0 AC13
USER_DIPSW1 A19
USER_DIPSW2 C21
USER_DIPSW3 C23
USER_DIPSW4 AF4
USER_DIPSW5 AC20
USER_DIPSW6 AE18
USER_DIPSW7 AE19
Figure 2–4. User-Defined Dipswitch (S1)
Name
Open Position
Logic 1
Cyclone II (U12)
Pin Number
Closed Position
Logic 0
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August 2006 Cyclone II DSP Development Board
User Interfaces
User-Defined Pushbuttons (SW2 Through SW5)
SW2-SW5 are user-defined momentary-contact push-button switches
used to provide stimulus to a user design on the Cyclone II DSP
development board. Each push-button is connected to the EP2C70
general-purpose I/O pin as listed in Table 2–5. When the switch is
pressed and held down, the device pin is set to logic 0, when the switch
is released, the device pin is set to logic 1. Figure 2–5 shows the
push-buttons.
Table 2–5. User-Defined Push-Button Pin-Outs
Push-Button
Name
PB3 SW2
PB2 SW3
PB1 SW4
PB0 SW5
Board Reference
Figure 2–5. User-Defined Pushbuttons
Schematic Signal
Name
Cyclone II (U12)
Pin Number
USER_PB3 AE14
USER_PB2 AE22
USER_PB1 AE16
USER_PB0 AC18
SW2
PB3
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Cyclone II DSP Development Board August 2006
SW3
PB2
SW4
PB1
SW5
PB0
Cyclone II DSP Development Board Components
Seven-Segment Display (U32,U33)
U32 and U33 are dual user defined, seven-segment displays on the
Cyclone II DSP development board. Each segment is individually
controlled by a general purpose I/O pin. When the EP2C70 FPGA pin
drives logic 0, the corresponding segment turns on. Table 2–6 lists the
seven-segment display pin-outs. Figure Figure 2–6 shows the name of
each segment.
Table 2–6. Seven-Segment Display Pin-Outs
U32 U33
Segment
Display Name
A
B
C
D
E
F
G
DP
Schematic
Signal Name
DIG_MSB_A Y21
DIG_MSB_B T7
DIG_MSB_C AB23
DIG_MSB_D Y5
DIG_MSB_E E1
DIG_MSB_F U1
DIG_MSB_G W21
DIG_MSB_DP V3
Cyclone II
(U12) Pin
Name
Figure 2–6. Segment Names for the Dual Seven-Segment Displays
Segment
Display Name
A
B
C
D
E
F
G
DP
U32
A
F
B
G
Schematic
Signal Name
DIG_LSB_A K2
DIG_LSB_B U25
DIG_LSB_C AA3
DIG_LSB_D V1
DIG_LSB_E V7
DIG_LSB_F U23
DIG_LSB_G AC2
DIG_LSB_DP P7
U33
A
F
B
G
Cyclone II
(U12) Pin
Name
CE
D
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August 2006 Cyclone II DSP Development Board
DP
CE
D
DP
User Interfaces
Audio CODEC Converter (U11)
The Cyclone II DSP development board contains three stereo jack
connectors, which provide one stereo output, one stereo input, and one
amplified stereo headphone output. The stereo jacks are driven by a
stereo audio CODEC running at 8-96 kHz. Table 2–7 lists the audio
CODEC references.
Table 2–7. Audio CODEC Reference
Item Description
Board reference U11
Part number TLV320AIC23
Device description Stereo Audio CODEC, 8-96 kHz
Manufacturer Texas Instruments
Manufacturer web site www.ti.com
Table 2–8 lists the TI TLV320AIC23 audio CODEC pin-outs.
Table 2–8. TI TLV320AIC23 Audio CODEC Pin-Outs
Schematic Signal Name
AUDIO_BCLK 3 F3
AUDIO_CLK 25 AB3
AUDIO_CSN 21 AC25
AUDIO_DIN 4 J21
AUDIO_DOUT 6 B13
AUDIO_LRCIN 5 W4
AUDIO_LRCOUT 7 AB2
AUDIO_MODE 22 AA2
AUDIO_SCLK 24 R4
AUDIO_SDIN 23 AD2
Audio CODEC (U11) Pin
Number
Cyclone II (U12) Pin
Number
Audio Jacks (J10, J14, J16)
The Cyclone II DSP development board contains the following audio
connectors:
■ J10—an audio connector for line-in
■ J14—an audio connector for line-out
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Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
■ J16—an amplified audio connector output for headphones
These jacks connect to the TI TLV320AIC23 stereo audio CODEC (U11),
which controls volume and balance levels and connections. See “Audio
CODEC Converter (U11)” on page 2–14.
VGA Output Connector (J21)
J21 is a standard DB-15 VGA video output connector. This connector
interfaces to the Fairchild FMS3818 Triple Video D/A Converter (U21) on
the EP2C70 FPGA. J21 allows video images to be displayed on VGA
monitors.
VGA Triple Video D/A Output Converter (U21)
The Cyclone II DSP development board contains a high density DB-15
connector (U21), which outputs VGA and a triple video D/A output
converter with the following features:
■ 3 x 8 bit, 180 megapixels per second
■ ±2.5% gain matching
■ ±0.5 LSB linearity error
■ Internal bandgap voltage reference
■ Low glitch energy
■ One 3.3-V power supply
Table 2–9 lists the VGA triple video D/A output converter device
reference.
Table 2–9. VGA Triple Video D/A Output Converter Device Reference
Item Description
Board reference U21
Part number FMS3818
Device description Triple Video D/A Converter, 3 x 8 bit, 180 Ms/s
Voltage 3.3 V
Manufacturer Fairchild Semiconductor
Manufacturer web site www.fairchildsemi.com
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August 2006 Cyclone II DSP Development Board
User Interfaces
Table 2–10 lists the VGA triple video D/A output converter pin-outs
Table 2–10. VGA Triple Video D/A Output Converter Pin-Outs (Part 1 of 2) Note (1)
Schematic Signal Name VGA (U21) Pin Number Cyclone II (U12) Pin Number
VGA_B0 16 AC1
VGA_B1 17 W3
VGA_B2 18 B2
VGA_B3 19 W2
VGA_B4 20 H2
VGA_B5 21 W1
VGA_B6 22 U4
VGA_B7 23 U2
VGA_BLANKN 10 U6
VGA_BLUE 29
VGA_CLK 26 T4
VGA_G0 2 R3
VGA_G1 3 W6
VGA_G2 4 R7
VGA_G3 5 U5
VGA_G4 6 R6
VGA_G5 7 AA4
VGA_G6 8 T6
VGA_G7 9 V4
VGA_GREEN 32
VGA_HSYNC H21
VGA_R0 40 Y22
VGA_R1 41 T22
VGA_R2 42 AD25
VGA_R3 43 T20
VGA_R4 44 AC23
VGA_R5 45 U21
VGA_R6 46 P4
VGA_R7 47 Y25
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Cyclone II DSP Development Board Components
Table 2–10. VGA Triple Video D/A Output Converter Pin-Outs (Part 2 of 2) Note (1)
Schematic Signal Name VGA (U21) Pin Number Cyclone II (U12) Pin Number
VGA_RED 33
VGA_SYNCN 11 AE2
Note to Table 2–10:
(1) Blank cells indicate no connection.
D/A Converter SMA Connector (J31 & J43)
J31 (channel A) and J43 (channel B) are standard through-hole SMA
connectors used to interface the TI DAC904E D/A converter with SMA
cables.
D/A Converter Clock Buffer (U27 & 30)
For channel A, U27 provides the selected D/A clock to U25. For channel
B, U27 provides the selected D/A clock to U30.For more information see
“D/A Converter (U25 & U30)” on page 2–17.
D/A Converter (U25 & U30)
The D/A converter (U25 for channel A and U30 for channel B) on the
Cyclone II DSP development board provides 14-bit resolution and
produces samples at rates up to 165 MSPS. It is a high-speed TI DAC904E
D/A converter and is set up to drive a differential-to-single output
through a transformer. The output is transformer coupled and can be
found on the SMA connector (J31 for channel A, J43 for channel B). The
output of the TI DAC904E D/A converter is set to the maximum output
current of 20 mA. The signal-to-noise ratio for the system is 70 dB for
output signals from 1 MHz to the Nyquist frequency of the converter.
1 The SLP-50 anti-aliasing filter from Mini-Circuits provides a
55 MHz cutoff frequency. To use the anti-aliasing filter, connect
the filter to one end of the SMA cable. You can perform an
external loopback from the SMA D/A converters to the SMA
A/D converters using the filter and cable assembly. If the cutoff
frequency must be lower than 55 MHz, other filters may be
used. See the Connecting the Cables to the Board & PC section in the
DSP Development Kit, Cyclone II Edition Getting Started User
Guide.
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August 2006 Cyclone II DSP Development Board
User Interfaces
Table 2–11 lists the D/A converter reference for channels A and B.
Table 2–11. D/A Converter Reference (Channels A & B)
Item Description
Board reference U25 (channel A), U30 (channel B)
Part number DAC904E
Device description 14-bit 165 MSPS D/A converter
Manufacturer Texas Instruments
Manufacturer web site www.ti.com
D/A Converter Clocks
Figure 2–7 shows the components involved in selecting the clock signal to
be sent to the TI DAC0904E (U25 for channel A, U30 for channel B). J35
(channel A) or J34 (channel B) selects the D/A clock from the OSC clock,
the FPGA clock, or the SMA clock (J26). The selected D/A clock passes
from J35 through a simple clock buffer (U27), which provides the clock
signal to the TI DAC904E.
Figure 2–7. TI DAC904E D/A Converter Clocking Options
95.3
143
95.3
143
FPGA_TO_DAC_CLK
J35 (Channel A)
or J34 (Channel B)
DAC Clock
Select
SMA_TO_DAC_CLK
50
U27
DAC Clock
Buffer
33
33
U25 (Channel A)
TI DAC904E
U30 (Channel B)
TI DAC904E
Custom Clock (J20)
On-Board Clock (U20)
External Clock SMA (J17)
CLKIN_TOP
J18
DAC External Clock SMA (J26)
U16
Clock
Buffer
33
33
33
CLKIN_BOT
CLK_OSC_DACA
U12
EP2C35
Refer to “Clock Circuitry” on page 2–59 for information on clock source selection.
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Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Table 2–12 lists the J35 jumper settings used to select the D/A clock.
Table 2–12. TI DAC904E D/A Converter (U25 & U30) Clock Source Settings
Clock Source Board Reference Schematic Signal Name
OSC clock OSC
CLK_OSC_DACA (Channel A)
CLK_OSC_DACB (Channel B)
FPGA clock PLL
SMA clock (J26) SMA
FPGA_TO_DAC_CLK
SMA_TO_DAC_CLK
Figure 2–8 shows the J35 and J34 pin-outs listed in Table 2–12. Pins 1 and
2 show an example jumper setting used to select the OSC clock.
Figure 2–8. J35 & J34 Pin Settings
Pin 2
Pin 1
J35 or J34
OSC
PLL
SMA
D/A Converter Clock
Select (J35 & J34)
Setting
Pins 1 and 2
Pins 3 and 4
Pins 5 and 6
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August 2006 Cyclone II DSP Development Board
User Interfaces
Table 2–13 lists the TI DAC904E D/A converter pin-outs for channel A.
Table 2–13. TI DAC904E D/A Converter Pin-Outs Note (1)
D/A Converter (U25)
Pin Name
DAC_A_D0 14 AB1
DAC_A_D1 13 AA1
DAC_A_D2 12 AE3
DAC_A_D3 11 AD3
DAC_A_D4 10 U3
DAC_A_D5 9 T2
DAC_A_D6 8 Y4
DAC_A_D7 7 AA5
DAC_A_D8 6 V5
DAC_A_D9 5 V6
DAC_A_D10 4 P3
DAC_A_D11 3 U7
DAC_A_D12 2 R5
DAC_A_D13 1 P6
DAC_A_IOUTn 21
DAC_A_IOUTp 22
Note to Table 2–13:
(1) Blank cells indicate no connection.
D/A Converter (U25) Pin
Number
Cyclone II (U12) Pin
Number
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Cyclone II DSP Development Board August 2006
Cyclone II DSP Development Board Components
Table 2–13 lists the TI DAC904E D/A converter pin-outs for channel B.
Table 2–14. TI DAC904E D/A Converter Pin-Outs Note (1)
D/A Converter (U30)
Pin Name
DAC_B_D0 14 M4
DAC_B_D1 13 M5
DAC_B_D2 12 U20
DAC_B_D3 11 V20
DAC_B_D4 10 V21
DAC_B_D5 9 B24
DAC_B_D6 8 T23
DAC_B_D7 7 P23
DAC_B_D8 6 Y24
DAC_B_D9 5 V24
DAC_B_D10 4 W25
DAC_B_D11 3 W26
DAC_B_D12 2 V25
DAC_B_D13 1 T25
DAC_B_IOUTn 21
DAC_B_IOUTp 22
Note to Table 2–13:
(1) Blank cells indicate no connection.
D/A Converter (U25) Pin
Number
Cyclone II (U12) Pin
Number
A/D Converter Data Format Select Jumper (J30 & J38)
The Data Format Select (DFS) jumper is used to select one of four data
output formats from the TI ADS5520 A/D converter. Table 2–16 on
page 2–22 lists the data output formats and how to select a format with
J30 (channel A) or J38 (channel B).
A/D Converter SMA Connector (J32 & J44)
J32 (channel A) and J44 (channel B) are standard through-hole SMA
connectors used to interface the TI ADS5520 A/D input converter with
SMA cables.
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August 2006 Cyclone II DSP Development Board
User Interfaces
A/D Converter Clock Buffer (U29 & U28)
U29 provides the selected A/D clock to U26 for channel A. U28 provides
the selected A/D clock to U31 for channel B. For more information, see
“A/D Converter (U26 & U31)” on page 2–22.
A/D Converter (U26 & U31)
The Cyclone II DSP development board contains one TI ADS5520 12-bit
125 MSPS A/D converter. The device is designed for high speed and
high-performance applications.
The input to this A/D converter is transformer-coupled in order to create
a balanced input. To maximize performance, two transformers (T2, T3)
are used in series. The signal-to-noise ratio for the system is 70 dB for
input signals from 1 MHz to the Nyquist frequency of the converter. The
maximum differential input voltage to the converter is 2.2 V
Table 2–15 lists the A/D converter references.
Table 2–15. A/D Converter Reference
Item Description
Board reference U26 (channel A) and U31 (channel B)
Part number ADS5520
Device description 12-bit 125 MSPS A/D converter
Manufacturer Texas Instruments
Manufacturer web site www.ti.com
.
PP
The data output format from the A/D converter is selectable through J30
(channel A) or J38 (channel B). Table 2–16 lists the available data output
format options and how to set them. Figure 2–9 shows the pin settings for
J30 and J38.
Table 2–16. TI ADS5520 A/D Converter (J26) Data Output Format Select
Jumper (J30 & J38)
Setting
Pins 1 and 2 Two’s Complement Data valid on falling edge
Pins 3 and 4 Straight Binary Data valid on falling edge
Pins 5 and 6 Two’s Complement Data valid on rising edge
Pins 7 and 8 Straight Binary Data valid on rising edge
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Cyclone II DSP Development Board August 2006
Data Format Clock Output Polarity
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