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CRC Compiler
User Manual
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Altera CRC Compiler User Manual

CRC Compiler User Guide
c The CRC Compiler is scheduled for product obsolescence and discontinued
support as described in PDN1304. Therefore, Altera does not recommend use of this IP in new designs. For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.
101 Innovation Drive San Jose, CA 95134
www.altera.com
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap­plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services
.
UG-CRC01004-1.7

Contents

Chapter 1. About This Compiler
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
CRC MegaCore Function Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
CRC Compiler Walkthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Create a New Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Launch the MegaWizard Plug-In Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Parameterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Set Up Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Generate Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Functional Description
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
CRC Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
CRC Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Running the Testbench Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Create a New Project for the Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Create the Generator and Checker Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
Create a Simulation Model for the Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Compile and Simulate the Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–ii
© November 2009 Altera Corporation CRC Compiler User Guide
Preliminary
iv
CRC Compiler User Guide © November 2009 Altera Corporation
Preliminary

Release Information

Tab le 1– 1 provides information about this release of the Cyclic Redundancy Check
(CRC) compiler.
Table 1–1. CRC Compiler Release Information
Version 9.1
Release Date November 2009
Ordering Code IP-CRC
Product ID(s) 00BC
Vendor ID(s) 6AF7
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata.

1. About This Compiler

Item Description
Altera verifies that the current version of the Quartus previous version of each MegaCore
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release."

Device Family Support

MegaCore® functions provide either full or preliminary support for target Altera device families, as described below:
■ Full support means the MegaCore function meets all functional and timing
requirements for the device family and may be used in production designs.
■ Preliminary support means the MegaCore function meets all functional
requirements, but may still be undergoing timing analysis for the device family; it may be used in production designs with caution.
Tab le 1– 2 shows the level of support offered by the CRC Compiler function to each
Altera device family.
Table 1–2. Device Family Support (Part 1 of 2)
®
Arria
GX Full
Arria II GX Preliminary
®
Cyclone
Cyclone
Cyclone III Full
HardCopy
II Full
®
II Full
®
function. The MegaCore IP Library Release Notes
Device Family Support
Full
®
II software compiles the
© November 2009 Altera Corporation CRC Compiler User Guide
Preliminary
1–2 Chapter 1: About This Compiler

Features

Table 1–2. Device Family Support (Part 2 of 2)
Device Family Support
HardCopy Stratix
®
Full
Stratix Full
Stratix GX Full
Stratix II Full
Stratix II GX Full
Stratix III Full
Stratix IV Preliminary
Other device families No support
Features
The following list summarizes the features of the CRC Compiler:
■ Highly parameterized Cyclic Redundancy Check (CRC) generator and checker
■ CRC-32, CRC-16-ANSI, and CRC-16-CCITT generator polynomials
■ High-speed operation, over 250 MHz for many configurations
■ Configurable input datapath width from 1 to 256 bits (power-of-two)
■ Configurable CRC starting value
■ Built-in support for the following:
■ Inverting output data
■ Reversing input and output data
■ Partial first word
■ Multi-channel operation
■ Av al on
®
Streaming (Avalon-ST) interface without backpressure for
message/codeword bits
■ Support for all possible end-of-packet byte residues
■ Verilog and VHDL demonstration testbenches
■ Easy-to-use MegaWizard
■ IP functional simulation models for use in Altera-supported VHDL and Verilog
™
interface
HDL simulators
■ Support for OpenCore Plus evaluation
CRC Compiler User Guide © November 2009 Altera Corporation
Preliminary
Chapter 1: About This Compiler 1–3

General Description

General Description
The CRC Compiler generates high-performance circuits to generate or check Cyclic Redundancy Check (CRC) checksums for packet-based communication.
The CRC generator uses an Avalon-ST
interface to receive data and emits generated checksums on a dedicated output. The CRC checker similarly uses an Avalon-ST interface to receive a packet with a CRC checksum and uses a dedicated output to indicate if the checksum is correct. The CRC generator and checker MegaCore functions do not store any data, checksums, or status.

CRC MegaCore Function Verification

Before releasing the CRC Compiler, Altera runs comprehensive regression tests to verify the quality and correctness of the CRC Compiler.
Custom variations generated by the CRC Compiler exercise the CRC compiler’s various parameter options. The resulting simulation models are thoroughly simulated, and the results are verified against bit-accurate master simulation models.

Performance and Resource Utilization

Parameterization allows you to generate the most efficient implementation that meets your design functionality, size, and performance goals.
The section lists the performance and resource utilization for several sample implementations in different device families. The performance metrics were generated using the Quartus analyzer, with the fastest speed grade selected for the device family. Neither the generator nor checker MegaCore function uses any memory.
Tab le 1– 3 shows the typical expected performance and resource utilization for
Cyclone II, Cyclone III, and Stratix GX devices.
Table 1–3. Performance and Resource Utilization for Cyclone II, Cyclone III and Stratix GX
Device and
Speed Grade
Cyclone II
-6
Cyclone III
-6
Stratix GX
-5
Note to Table 1–3:
(1) Parameters set to their default values are not mentioned.
MegaCore
Function Parameter Settings (1)
CRC generator 8-bit datapath
1 symbol per word
CRC generator 34 450.05 3.6
CRC checker 16-bit datapath
Inputs and outputs not registered
CRC-16-CCITT
Optimize for area
2 symbols per word
CRC-16-ANSI
Optimize for speed
®
II software version 8.0 and the TimeQuest timing
Logic
Elements
34 420.17 3.36
147 277 4.4
f
max
MHz
Throughput
Gbps
© November 2009 Altera Corporation CRC Compiler User Guide
Preliminary
1–4 Chapter 1: About This Compiler

Installation and Licensing

Tab le 1– 4 shows the typical expected performance for Stratix II, Stratix II GX, and
Stratix III devices. The performance of the MegaCore function in Stratix IV devices is similar to Stratix III devices.
Table 1–4. Performance and Resource Utilization Stratix II, Stratix II GX and Stratix III Devices
Device and
Speed Grade
Stratix II
-3
MegaCore
Function Parameter Settings (1) ALUTs
CRC generator 32-bit datapath
CRC-32
4 symbols per word Optimize for speed
Stratix II
-3
CRC generator 32-bit datapath
CRC-32
4 symbols per word Optimize for speed
8 channels
Stratix II GX
-3
CRC checker 64-bit datapath
8 symbols per word CRC­16-CCITT
Optimize for speed
Stratix II GX
-3
CRC checker 64-bit datapath
8 symbols per word CRC­16-CCITT
Optimize for speed
8 channels
Stratix III
-2
CRC generator 32-bit datapath
CRC-32
4 symbols per word Optimize for speed
Note to Table 1–4:
(1) Parameters set to their default values are not mentioned.
Logic
Registers
f
max
MHz
Throughput
Gbps
510 373 274 8.7
869 1177 226.96 7.3
551 358 241 15.4
440 614 201.9 12.9
519 372 330 10.5
Installation and Licensing
The CRC Compiler is part of the MegaCore® IP Library, which is distributed with the Quartus
f For system requirements and installation instructions, refer to Quartus II Installation &
Licensing for Windows and Linux Workstations.
Figure 1–1 shows the directory structure after you install the CRC Compiler User
Guide Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\<version>; on UNIX and Solaris it is /opt/altera/<version>.
CRC Compiler User Guide © November 2009 Altera Corporation
®
II software and downloadable from the Altera® website, www.altera.com.
Preliminary
Chapter 1: About This Compiler 1–5
ip
Contains the MegaCore IP Library.
common
Contains the shared components.
crc_compiler
Contains the CRC Compiler files and documentation.
doc
Contains all the documentation for the CRC Compiler.
lib
Contains encrypted lower level design files and other support files.
<path>
Installation directory.
altera
Contains all MegaCore IP Library from Altera.
Installation and Licensing
Figure 1–1. Directory Structure

OpenCore Plus Evaluation

With Altera’s free OpenCore Plus evaluation feature, you can perform the following actions:
■ Simulate the behavior of a megafunction (Altera MegaCore function or AMPP
megafunction) within your system.
SM

OpenCore Plus Time-Out Behavior

© November 2009 Altera Corporation CRC Compiler User Guide
■ Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily.
■ Generate time-limited device programming files for designs that include
megafunctions.
■ Program a device and verify your design in hardware.
You only need to purchase a license for the megafunction when you are completely satisfied with its functionality and performance, and want to take your design to production.
After you purchase a license for CRC Compiler MegaCore function, you can request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative.
f For more information on OpenCore Plus hardware evaluation, refer to AN 320:
OpenCore Plus Evaluation of Megafunctions.
OpenCoree Plus hardware evaluation supports the following two operation modes:
■ Untethered—the design runs for a limited time.
■ Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely.
Preliminary
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