Altera CPRI v6.0 MegaCore Function User Manual

CPRI v6.0 MegaCore Function User Guide

Last updated for Altera Complete Design Suite: 14.0 and 14.0 Arria 10

Edition

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TOC-2

CPRI v6.0 MegaCore Function User Guide

About the CPRI v6.0 IP Core..............................................................................1-1

Getting Started with the CPRI v6.0 IP Core.......................................................2-1

CPRI v6.0 IP Core Supported Features.....................................................................................................1-2

CPRI v6.0 IP Core Device Family and Speed Grade Support................................................................1-3

Device Family Support....................................................................................................................1-3

CPRI v6.0 IP Core Performance: Device Speed Grade Support................................................1-4

IP Core Verification.....................................................................................................................................1-4

Resource Utilization for CPRI v6.0 IP Cores...........................................................................................1-4

Release Information.....................................................................................................................................1-6

Installation and Licensing Features...........................................................................................................1-6

OpenCore Plus Evaluation............................................................................................................. 1-6

OpenCore Plus Time-Out Behavior..............................................................................................1-7

Installation and Licensing...........................................................................................................................2-2

Specifying IP Core Parameters and Options............................................................................................2-2

Files Generated for Altera IP Cores...........................................................................................................2-3

CPRI v6.0 IP Core Parameters...................................................................................................................2-7

Integrating Your IP Core in Your Design: Required External Blocks................................................2-11

Adding the Clean-Up PLL............................................................................................................2-12

Adding the External TX PLL........................................................................................................2-13

Adding the External Reset Controller.........................................................................................2-14

Adding the Transceiver Reconfiguration Controller................................................................2-15

Simulating Altera IP Cores.......................................................................................................................2-16

Understanding the Testbench..................................................................................................................2-17

Running the Testbench.............................................................................................................................2-17

Functional Description....................................................................................... 3-1

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Interfaces Overview.....................................................................................................................................3-1

CPRI v6.0 IP Core Clocking Structure......................................................................................................3-3

CPRI v6.0 IP Core Reset Requirements....................................................................................................3-5

Start-Up Sequence Following Reset.......................................................................................................... 3-6

AUX Interface...............................................................................................................................................3-9

AUX Interface Signals...................................................................................................................3-10

AUX Interface Synchronization.................................................................................................. 3-17

Auxiliary Latency Cycles...............................................................................................................3-17

Direct Interface CPRI Frame Data Format................................................................................3-18

Direct IQ Interface.....................................................................................................................................3-21

Direct Vendor Specific Access Interface.................................................................................................3-23

Real-Time Vendor Specific Interface......................................................................................................3-25

Direct HDLC Serial Interface...................................................................................................................3-27

Direct L1 Control and Status Interface...................................................................................................3-29

CPRI v6.0 MegaCore Function User Guide

Media Independent Interface (MII) to External Ethernet Block........................................................ 3-32

CPU Interface to CPRI v6.0 IP Core Registers......................................................................................3-35

CPU Interface Signals....................................................................................................................3-36

Accessing the Hyperframe Control Words................................................................................3-37

Auto-Rate Negotiation..............................................................................................................................3-40

Extended Delay Measurement.................................................................................................................3-41

Extended Delay Measurement Interface.....................................................................................3-43

Deterministic Latency............................................................................................................................... 3-43

CPRI v6.0 IP Core Transceiver and Transceiver Management Interfaces........................................ 3-45

CPRI Link........................................................................................................................................3-45

Main Transceiver Clock and Reset Signals.................................................................................3-46

Arria V GZ and Stratix V Transceiver Reconfiguration Interface..........................................3-46

Arria 10 Transceiver Reconfiguration Interface........................................................................3-46

Interface to the External Reset Controller..................................................................................3-47

Interface to the External PLL........................................................................................................3-48

Transceiver Debug Interface........................................................................................................ 3-49

Testing Features......................................................................................................................................... 3-49

CPRI v6.0 IP Core Loopback Modes...........................................................................................3-49

CPRI v6.0 IP Core Self-Synchronization Feature......................................................................3-50

TOC-3

CPRI v6.0 IP Core Signals...................................................................................4-1

CPRI v6.0 IP Core L2 Interface..................................................................................................................4-1

CPRI v6.0 IP Core L1 Direct Access Interfaces....................................................................................... 4-2

CPRI v6.0 IP Core Management Interfaces............................................................................................. 4-4

CPRI v6.0 IP Core Transceiver and Transceiver Management Signals............................................... 4-6

CPRI v6.0 IP Core Registers................................................................................5-1

INTR Register...............................................................................................................................................5-3

L1_STATUS Register...................................................................................................................................5-3

L1_CONFIG Register..................................................................................................................................5-4

BIT_RATE_CONFIG Register...................................................................................................................5-5

PROT_VER Register................................................................................................................................... 5-6

TX_SCR Register..........................................................................................................................................5-7

RX_SCR Register..........................................................................................................................................5-7

CM_CONFIG Register................................................................................................................................5-8

CM_STATUS Register................................................................................................................................ 5-9

START_UP_SEQ Register..........................................................................................................................5-9

START_UP_TIMER Register.................................................................................................................. 5-10

FLSAR Register...........................................................................................................................................5-11

CTRL_INDEX Register.............................................................................................................................5-11

TX_CTRL Register.....................................................................................................................................5-12

RX_CTRL Register.....................................................................................................................................5-13

RX_ERR Register....................................................................................................................................... 5-13

RX_BFN Register.......................................................................................................................................5-14

LOOPBACK Register................................................................................................................................5-14

TX_DELAY Register................................................................................................................................. 5-16

RX_DELAY Register................................................................................................................................. 5-17

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TOC-4

CPRI v6.0 MegaCore Function User Guide

TX_EX_DELAY Register..........................................................................................................................5-18

RX_EX_DELAY Register..........................................................................................................................5-18

ROUND_TRIP_DELAY Register............................................................................................................5-19

XCVR_BITSLIP Register..........................................................................................................................5-19

Differences Between CPRI v6.0 IP Core and CPRI IP Core..............................A-1

Additional Information......................................................................................B-1

CPRI v6.0 MegaCore Function User Guide Revision History..............................................................B-1

How to Contact Altera................................................................................................................................B-2

Typographic Conventions..........................................................................................................................B-2

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2014.08.18

CPRI v6.0

IP Core

(RE Slave)

FPGA FPGA

CPRI v6.0

IP Core

(RE Slave)

CPRI v6.0

IP Core

(RE Master)

FPGA

CPRI v6.0

IP Core

(REC)

Clock

Module

Base Band Module

Optical Link

CPRICPRICPRI

CPRI

Routing Layer

IQ Direct IQ DirectAUX AUX

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About the CPRI v6.0 IP Core

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The Altera® CPRI v6.0 MegaCore® function implements the CPRI Specification V6.0 (2013-08-30). CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

The CPRI v6.0 IP core targets high-performance, remote, radio network applications. You can configure the CPRI v6.0 IP core as an RE or an REC.

Figure 1-1: Typical CPRI Application on Altera Devices

Example system implementation with a two-hop daisy chain. Optical links between devices support high performance.

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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1-2

CPRI v6.0 IP Core Supported Features

The CPRI v6.0 IP core offers the following features:

• Compliant with the Common Public Radio Interface (CPRI) Specification V6.0 (2013-08-30) Interface Specification available on the CPRI Industry Initiative website (www.cpri.info).

• Supports radio equipment controller (REC) and radio equipment (RE) module configurations.

• Supports the following CPRI link features:

• Configurable CPRI communication line bit rate (to 0.6144, 1.2288, 2.4576, 3.0720, 4.9152, 6.144,

9.8304, or 10.1376 Gbps) using Altera on-chip high-speed transceivers.

• CPRI line bit rate auto-rate negotiation support.

• Configurable and run-time programmable operation mode: CPRI link master or CPRI link slave.

• Optional scrambling and descrambling at 4.9152, 6.1440, 9.8304, and 10.1376 Gbps.

• Transmitter (Tx) and receiver (Rx) delay measurement and calibration.

• Optional L1 link status and alarm (Z.130.0) control and status monitoring.

• Access to all Vendor Specific data.

• Diagnostic parallel reverse loopback paths.

• Diagnostic serial and parallel forward loopback paths.

• Diagnostic stand-alone slave testing mode.

• Includes the following interfaces:

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• Register access interface to external or on-chip processor, using the Altera Avalon® Memory-

Mapped (Avalon-MM) interconnect specification.

• Optional auxiliary (AUX) interface for full access to raw CPRI frame. Provides direct access to full

radioframe, synchronizes the frame position with timing references, and enables routing applica‐ tion support from slave to master ports to implement daisy-chain topologies.

• Optional IEEE 802.3 100BASE-X compliant 100Mbps MII for Ethernet frame access.

• Optional direct I/Q access interface enables integration of all user-defined air standard I/Q

mapping schemes.

• Optional vendor specific data access interfaces provide direct access to Vendor Specific (VS),

Control AxC (Ctrl_AxC), and Real-time Vendor Specific (RTVS) subchannels.

• Optional HDLC serial interface provides direct access to slow control and management subchan‐

nels.

• Optional L1 inband interface provides direct access to Z.130.0 link status and alarm control word.

Related Information

CPRI Industry Initiative website

For a detailed specification of the CPRI protocol refer to the CPRI Specification V6.0 (2013-08-30) Interface Specification available on the CPRI Industry Initiative website.

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CPRI v6.0 IP Core Device Family and Speed Grade Support

The following sections list the device family and device speed grade support offered by the CPRI v6.0 IP core:

Device Family Support

Table 1-1: Altera IP Core Device Support Levels

Device Support Level Definition

Preliminary Altera has verified the IP core with preliminary

timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final Altera has verified the IP core with final timing

models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

1-3

Table 1-2: CPRI v6.0 IP Core Device Family Support

Shows the level of support offered by the CPRI v6.0 IP core for each Altera device family.

Device Family Support

Arria V GZ Default support level provided in Quartus II

software v14.0. Refer to the What's New in Altera IP page of the Altera website.

Stratix V (GX and GT) Default support level provided in Quartus II

software v14.0. Refer to the What's New in Altera IP page of the Altera website.

Arria 10 (GX and GT) Default support level provided in Quartus II

software v14.0 Arria 10 Edition. Refer to the What's New in Altera IP page of the Altera website.

Other device families No support

Related Information

CPRI v6.0 IP Core Performance: Device Speed Grade Support on page 1-4 What's New in Altera IP

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CPRI v6.0 IP Core Performance: Device Speed Grade Support

Table 1-3: Slowest Supported Device Speed Grades

Lower speed grade numbers correspond to faster devices. The entry -x indicates that both the industrial speed grade Ix and the commercial speed grade Cx are supported for this device family and CPRI line bit rate.

CPRI Line Bit Rate (Gbps) Arria V GZ Stratix V GX Stratix V GT

0.6144

1.2288

2.4576

-4 -4 -3

3.072

4.9152

6.1440

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9.8304 -3

10.1376

(1)

IP Core Verification

To ensure functional correctness of the CPRI v6.0 IP core, Altera performs extensive validation through both simulation and hardware testing. Before releasing a version of the CPRI v6.0 IP core, Altera runs comprehensive regression tests in the associated version of the Quartus® II software.

Related Information

• Knowledge Base Errata for CPRI v6.0 IP core Exceptions to functional correctness are documented in the CPRI v6.0 IP core errata.

Resource Utilization for CPRI v6.0 IP Cores

Resource utilization changes depending on the parameter settings you specify in the CPRI v6.0 parameter editor. For example, with every additional interface you enable, the IP core requires additional resources to implement the module that supports that interface.

-2 -2

(1)

This CPRI line bit rate is not supported for this device family.

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Resource Utilization for CPRI v6.0 IP Cores

Table 1-4: IP Core FPGA Resource Utilization

Lists the resources and expected performance for selected variations of the CPRI v6.0 IP core in an Arria 10 (10AX115R2F40I2LG), Stratix V (5SGSMD4E2H29C2), or Arria V GZ (5AGZME5K2F40C3) device. All variations are in Master Operation mode and have a Receiver FIFO depth value of 6.

• Minimum IP core variation: includes no direct interfaces and no L2 interface, supports no loopback mode and no debug features.

• Maximum IP core variation: includes all direct interfaces and the L2 Ethernet interface, supports all loopback modes and debug features, has an L2 Ethernet buffer depth parameter value of 7, and an Auxiliary latency cycle(s) value of 0.

These results were obtained using the Quartus II v14.0 and Quartus II v14.0 Arria 10 Edition software

• The numbers of ALMs and logic registers are rounded up to the nearest 100.

• The numbers of ALMs, before rounding, are the ALMs needed numbers from the Quartus II Fitter Report.

1-5

Arria 10 10.3176 Gbps

Variation

ALMs Logic Registers M20K Blocks

Minimum 600 1200 4

Maximum 2900 3700 16

Stratix V 10.3176 Gbps

Variation

ALMs Logic Registers M20K Blocks

Minimum 700 1300 4

Maximum 3300 4100 18

Arria V GZ 9.8 Gbps

Variation

ALMs Logic Registers M20K Blocks

Minimum 800 1300 2

Maximum 2900 3800 13

Related Information

Fitter Resources Reports in the Quartus II Help

Information about Quartus II resource utilization reporting, including ALMs needed.

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1-6

Release Information

Table 1-5: CPRI v6.0 IP Core Current Release Information

Item Description

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Compatible

14.0 14.0 Arria 10 Edition Quartus II Software Version

Release Date June 2014 August 2014

Ordering

IP-CPRI-V6

Codes

Product ID 0129

Vendor ID 6AF7

Installation and Licensing Features

The CPRI v6.0 IP core provides OpenCore Plus support. The following sections describe OpenCore Plus support:

OpenCore Plus Evaluation on page 1-6 OpenCore Plus Time-Out Behavior on page 1-7

Related Information

Release Information on page 1-6

OpenCore Plus Evaluation

Altera's OpenCore Plus evaluation feature is available for the CPRI v6.0 IP core. With the OpenCore Plus evaluation feature, you can perform the following actions:

• Simulate the behavior of a MegaCore function or megafunction in your system.

• Verify the functionality of your design, as well as evaluate its size and speed quickly and easily.

• Generate time-limited device programming files for designs that include MegaCore functions.

• Program a device and verify your design in hardware. You need to purchase a license for the megafunction only when you are completely satisfied with its

functionality and performance, and want to take your design to production.

Related Information

AN 320: OpenCore Plus Evaluation of Megafunctions

Information about the OpenCore Plus feature.

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OpenCore Plus Time-Out Behavior

OpenCore Plus hardware evaluation can support the following two modes of operation:

• Untethered—the design runs for a limited time.

• Tethered—requires a connection between your board and the host computer. If tethered mode is supported by all MegaCore functions in a design, the device can operate for a longer time or indefinitely.

All MegaCore functions in a device time-out simultaneously when the most restrictive evaluation time is reached. If a design contains more than one MegaCore function, a specific IP core's time-out behavior may be masked by the time-out behavior of the other IP cores.

Note: For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out value is

indefinite.

Your design stops working after the hardware evaluation time expires.

Related Information

AN 320: OpenCore Plus Evaluation of Megafunctions

Information about the OpenCore Plus feature.

OpenCore Plus Time-Out Behavior

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Getting Started with the CPRI v6.0 IP Core

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Explains how to install, parameterize, and simulate the Altera CPRI v6.0 IP core.

Installation and Licensing on page 2-2

The CPRI v6.0 IP core is an extended IP core which is not included with the Quartus II release. This section provides a general overview of the Altera extended IP core installation process to help you quickly get started with any Altera extended IP core.

Specifying IP Core Parameters and Options on page 2-2

After you install and integrate the extended IP core in the ACDS release, the CPRI v6.0 IP core supports the standard customization and generation process. This IP core does not generate a testbench or example design simultaneously with generation of the IP core. Instead, you must use the Example Design button in the CPRI v6.0 parameter editor to generate the testbench. This IP core is not supported in Qsys.

Files Generated for Altera IP Cores on page 2-3

The Quartus software generates the following IP core output file structure.

CPRI v6.0 IP Core Parameters on page 2-7

The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core and simulation testbench.

Integrating Your IP Core in Your Design: Required External Blocks on page 2-11

You must connect your CPRI v6.0 IP core to some additional required design components. Your design can compile without some of these connections and logical blocks, but it will not function correctly in hardware unless all of them are present and connected in your design.

Simulating Altera IP Cores on page 2-16

The Quartus II software supports RTL- and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

Understanding the Testbench on page 2-17

Altera provides a demonstration testbench with the CPRI v6.0 IP core.

Running the Testbench on page 2-17

To run the Altera CPRI v6.0 IP core demonstration testbench, follow these steps.

Related Information

Managing Quartus II Projects

Refer to the "Integrating IP Cores" section of this Quartus II Handbook chapter for more information about generating an Altera IP core and integrating it in your Quartus II project.

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<path>

Quartus II installation directory

ip Contains the Altera IP Library and third-party IP cores

altera_cloud Contains the Altera extended IP cores that you install

cpri_ii Contains the CPRI v6.0 IP core files

2-2

Installation and Licensing

The Altera extended IP cores are available from the Altera Self-Service Licensing Center (SSLC). Refer to Related Information below for the correct link for this IP core.

Figure 2-1: IP Core Directory Structure

Directory structure after you install the CPRI v6.0 IP core. The default installation directory <path> on Windows is C:\altera\< version number >; on Linux it is /opt/altera< version number >.

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Related Information

• Altera website

• Altera Licensing website

• Altera Self-Service Licensing Center

After you purchase the CPRI v6.0 IP core, the IP core is available for download from the SSLC page in your myAltera account. Altera requires that you create a myAltera account if you do not have one already, and log in to access the SSLC. On the SSLC page, click Run for this IP core. The SSLC provides an installation dialog box to guide your installation of the IP core.

Specifying IP Core Parameters and Options

The parameter editor GUI allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus II software. Refer to Specifying IP Core Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.

The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

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3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

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Files Generated for Altera IP Cores

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate a simulation testbench, click Generate > Generate Testbench System.

7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

Figure 2-2: IP Parameter Editor

2-3

Files Generated for Altera IP Cores

The Quartus software generates the following IP core output file structure.

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<your_testbench>_tb.csv <your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Lists files for simulation

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines individual simulation scripts

<your_ip>_tb.qsys

Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench files

2-4

Files Generated for Altera IP Cores

Figure 2-3: IP Core Generated Files

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Table 2-1: IP Core Generated Files

File Name Description

<my_ip>.qsys

<system>.sopcinfo Describes the connections and IP component parameterizations in

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.

your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

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Files Generated for Altera IP Cores

File Name Description

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that

contains local generic and port definitions that you can use in VHDL design files.

2-5

<my_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP

generation.

<my_ip>.debuginfo Contains post-generation information. Used to pass System Console

and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.

<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus software.

<my_ip>.csv Contains information about the upgrade status of the IP component. <my_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use

in Quartus Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for

IP components created for use with the Pin Planner.

<my_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module

declaration for use as a black box.

<my_ip>.sip Contains information required for NativeLink simulation of IP

components. You must add the .sip file to your Quartus project.

<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the

contents of this file into your HDL file to instantiate the IP variation.

<my_ip>.regmap If IP contains register information, .regmap file generates.

The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in the System Console.

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Files Generated for Altera IP Cores

File Name Description

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<my_ip>.svd

<my_ip>.v

<my_ip>.vhd

mentor/

aldec/

/synopsys/vcs

/synopsys/vcsmx

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

HDL files that instantiate each submodule or child IP core for synthesis or simulation.

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

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CPRI v6.0 IP Core Parameters

The CPRI v6.0 parameter editor provides the parameters you can set to configure the CPRI v6.0 IP core and simulation testbench.

Table 2-2: General CPRI v6.0 IP Core Parameters

Describes the general parameters for customizing the CPRI v6.0 IP core. These parameters appear on the General tab in the CPRI v6.0 parameter editor.

2-7

Parameter Range Default

Bit rate (Mbits/s) • 614.4

• 1228.8

• 2457.6

• 3072.0

• 4915.2

• 6144.0

• 9830.4

• 10137.6

Operation mode • Master

• Slave

Supported receiver CDR frequency

Per drop-down menu

(MHz)

Parameter Description

Setting

614.4 Selects the CPRI line bit rate. Arria V GZ devices support all line bit rates except

10.1376 Gbps. All other supported devices support all CPRI line bit rates.

Master

Specifies whether the CPRI v6.0 IP core is configured as a CPRI link master or a CPRI link slave.

The value of this parameter determines the initial and reset operation mode of the CPRI v6.0 IP core. You can modify the IP core operation mode dynamically by modifying the value of the

operation_mode field of the L1_CONFIG register.

307.2

Specifies the incoming reference clock frequency for the receiver CDR PLL, in MHz.

You must drive the input clock xcvr_cdr_refclk at the frequency you specify for this parameter.

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CPRI v6.0 IP Core Parameters

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Parameter Range Default

Receiver FIFO depth

Enable auto-rate negotiation

4, 5, 6, 7, or 8 6

• On

• Off

Setting

Off

Parameter Description

The value you specify for this parameter is log2 of the IP core Layer 1 Rx buffer depth.The IP core supports a maximum Layer 1 RX buffer depth of

256. The default depth of the buffer is 64, specified by

the parameter default value of 6. For most systems, the default buffer depth is adequate to handle dispersion, jitter, and drift that can occur on the link while the system is running. However, the parameter is available for cases in which additional depth is required.

The user guide refers to this parameter value as

RX_BUF_DEPTH.

Turn on the Enable auto-rate negotiation parameter to specify that your CPRI v6.0 IP core supports auto-rate negotiation.

This parameter is available when you specify a CPRI line bit rate (value for the Bit rate parameter) that is greater than 614.4 Mbps.

Enable auto-rate negotiation down to

614.4 Mbps

• On

• Off

Off

Turn on this parameter to specify that your autorate negotiation enabled CPRI v6.0 IP core can support auto-rate negotiation all the way down to the CPRI line bit rate of 0.6144 Gbps.

This parameter is available when you turn on Enable auto-rate negotiation.

Table 2-3: CPRI v6.0 IP Core Interface Feature Parameters

Describes the parameters for customizing the CPRI v6.0 IP core Layer 1 and Layer 2 interfaces and testing features. These parameters appear on the Interfaces tab in the CPRI v6.0 parameter editor.

Parameter Range Default

Setting

Parameter Description

L1 Features Supported CPU

interface standard

Currently, only the AvalonMM CPU interface is available in the CPRI v6.0 IP

Selects the interface specification that describes the behavior of the CPRI v6.0 IP core register access interface.

core.

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Parameter Range Default

Auxiliary latency

0 to 9 0

cycle(s)

Parameter Description

Setting

Specifies the additional write latency on the AUX TX interface and other direct TX interfaces to the CPRI v6.0 IP core. The write latency is the number of cpri_clkout cycles from when the

aux_tx_seq output signal has the value of 0 to

when user logic writes data to the AUX TX interface. For other direct interfaces, the IP core notifies user logic when it is ready for input and the user does not need to monitor the aux_tx_

seq signal.

When Auxiliary latency cycle(s) has the value of zero, the write latency on the direct TX interfaces is one cpri_clkout cycle. When Auxiliary latency cycle(s) has the value of N, the write latency is (1+N) cpri_clkout cycles.

Set this parameter to a value that provides user logic with sufficient advance notice of the position in the CPRI frame. The processing time that user logic requires after determining the current position in the CPRI frame is implemen‐ tation specific.

Enable auxiliary interface

Enable all control word access

Enable direct IQ mapping interface

• On

• Off

• On

• Off

• On

• Off

Off

This parameter is available if you turn on at least one direct interface in your CPRI v6.0 IP core variation.

Turn on this parameter to include the AUX interface in your CPRI v6.0 IP core. The AUX interface provides full access to the raw CPRI frame.

Turn on this parameter to enable access to all control words in a hyperframe using the CPRI v6.0 CTRL_INDEX, TX_CTRL, and RX_CTRL registers.

Use this option with caution. During transmis‐ sion, this feature has higher priority than the MII, the HDLC serial interface, the L1 control and status interface, and the generation of special symbols (K28.5, D16.2, /S/, /T/) , and can overwrite standard control words in the hyperframe.

Turn on this parameter to include a dedicated interface to access the raw I/Q data bytes in the CPRI frame.

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CPRI v6.0 IP Core Parameters

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Parameter Range Default

Enable direct ctrl_axc access interface

Enable direct vendor specific access

• On

• Off

• On

• Off

interface

Enable start-up sequence state

• On

• Off

machine

Enable L1 inband protocol negotiator

• On

• Off

Setting

Off

Parameter Description

Turn on this parameter to include a dedicated interface to access the Ctrl_AxC subchannels in the CPRI frame.

Turn on this parameter to include a dedicated interface to access the VS subchannels in the CPRI frame.

Turn on this parameter to include a start-up sequence state machine in the CPRI v6.0 IP core.

Turn on this parameter to include a negotiator block that performs auto-negotiation of L1 inband protocol version (communicated in CPRI frame position Z.2.0) and L2 C&M rates (communicated in CPRI frame positions Z.66.0 and Z.194.0).

This parameter is available when you turn on

Enable start-up sequence state machine.

Enable real-time vendor specific interface (R-16A)

Enable Z.130.0 access interface

L2 Features Enable direct HDLC

serial interface

Enable IEEE 802.3 100BASE-X 100Mbps MII

• On

• Off

• On

• Off

• On

• Off

• On

• Off

Off

Turn on this parameter to include a dedicated interface to access the RTVS subchannel in the CPRI frame.

This parameter is available when you specify a CPRI line bit rate of 10137.6 Mbps.

Turn on this parameter to include a dedicated L1 control and status interface to communicate the contents of the CPRI frame Z.130.0 word, which includes alarms and reset signals.

Turn on this parameter to include a dedicated interface to communicate the contents of the slow C&M subchannels.

For full HDLC communication, you must connect a user-defined HDLC module to this interface.

Turn on this parameter to include an MII port to communicate with the fast C&M (Ethernet) CPRI subchannel.

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For full Ethernet communication, you must connect a user-defined Ethernet MAC to this interface.

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2-11

Parameter Range Default

L2 Ethernet PCS Tx/

7, 8, 9, 10 7

Rx FIFO depth

Debug Features Enable debug

interface

Enable transceiver PMA forward

• On

• Off

• On

• Off

loopback path (Tx to Rx)

Setting

Off

Parameter Description

The value you specify for this parameter is log2 of the IP core Layer 2 Ethernet PCS Rx buffer depth and Tx buffer depth. The IP core supports a maximum Layer 2 Ethernet PCS buffer depth of

1024. This parameter is available when you turn on

Enable IEEE 802.3 100BASE-X 100Mbps MII.

Turn on this parameter to include dedicated transceiver status and L1 Rx status interfaces to support debug.

Turn on this parameter to enable transceiver PMA serial forward loopback. To turn on transceiver PMA serial forward loopback, you must also write the value of 2'b01 to the loop_

forward field of the LOOPBACK register at offset

0x44.

Enable forward loopback path (Tx to Rx)

• On

• Off

Off

Turn on this parameter to enable other internal parallel forward loopback paths. To turn on internal parallel forward loopback, you must also write a non-zero value to the loop_forward field of the LOOPBACK register at offset 0x44.

Enable reverse loopback path (Rx to Tx)

• On

• Off

Off

Turn on this parameter to enable internal parallel reverse loopback. To turn on reverse loopback, you must also write a non-zero value to the loop_

reversed field of the LOOPBACK register at offset

0x44, to specify the parts of the CPRI frame that are sent on the loopback path.

Related Information

LOOPBACK Register on page 5-14

Integrating Your IP Core in Your Design: Required External Blocks

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Reset Controller

PLL

Transmitter

(Native PHY)

Receiver

(Native PHY)

User-Defined

Reference Clock

xcvr_ext_pll_clk

xcvr_tx_analogreset xcvr_tx_digitalreset xcvr_tx_cal_busy

xcvr_rx_analogreset xcvr_rx_digitalreset xcvr_rx_is_lockedtodata xcvr_rx_cal_busy

xcvr_cdr_refclk

reset_tx reset_rx

pll_locked

CPRI v6.0 IP Core

xcvr_reset_tx_ready

xcvr_reset_rx_ready

2-12

Adding the Clean-Up PLL

The CPRI v6.0 IP core requires that you define, instantiate, and connect the following additional software and hardware modules for all CPRI v6.0 IP core variations:

• An external PLL IP core to configure the transceiver TX PLL. Although the hardware this IP core configures is physically part of the device transceiver, you must instantiate it in software separately from the CPRI v6.0 IP core. In Arria 10 devices, this Altera requirement supports the configuration of multiple Altera IP cores using the same transceiver block in the device.

• One or more external reset controllers to coordinate the reset sequence for the CPRI v6.0 IP core in your design.

In addition, CPRI link slave modules require an external clean-up PLL and Arria V GZ and Stratix V variations require an external transceiver reconfiguration controller.

Figure 2-4: Required External Blocks

An example showing how you could connect required components to a single CPRI v6.0 IP core.

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Related Information

Adding the External Reset Controller on page 2-14

Adding the Clean-Up PLL

If your CPRI v6.0 IP core is an RE slave, you must connect it to an external clean-up PLL to clean up any jitter that occurs in the CDR output clock before sending it to the external TX PLL.

The clean-up PLL performs the clock synchronization necessary to address the CPRI v6.0 Specification requirements R-17, R-18, and R-18A, which address jitter and frequency accuracy in the RE core clock for radio transmisstion.

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Drive the clean-up PLL with the CPRI v6.0 IP core xcvr_recovered_clk output clock, and connect the cleaned up output to the external TX PLL input reference clock port.

Related Information

CPRI v6.0 IP Core Clocking Structure on page 3-3

Adding the External TX PLL

The CPRI v6.0 IP core requires that you generate and connect an external TX PLL IP core. The transceiver PLL IP core configures the TX PLL in the transceiver in hardware, but you must generate the transceiver PLL IP core separately from the CPRI v6.0 IP core in software. If you do not generate and connect the transceiver PLL IP core, the CPRI v6.0 IP core does not compile.

You can use the IP Catalog to generate the external PLL IP core that configures a TX PLL on the device. In the IP Catalog, select an Altera IP core that configures an appropriate PLL on your target device.

In the Stratix V TX PLL parameter editor, you must set the following parameter values:

• Enable PLL reconfiguration: Turn on if you turned on Enable auto-rate negotiation in the CPRI v6.0 parameter editor. Otherwise, turn off.

• Number of TX PLL reference clocks: 1.

• PLL feedback path: Set to internal.

• PLL type: Select a type that supports the CPRI line bit rate you specified in the CPRI v6.0 parameter editor.

• PLL base data rate: Set to the CPRI line bit rate you specified in the CPRI v6.0 parameter editor.

• Selected reference clock source: Set to 0.

Adding the External TX PLL

2-13

For your Arria 10 design, you can select Arria 10 Transceiver ATX PLL, Arria 10 Transceiver CMU PLL, or Arria 10 FPLL in the IP Catalog. In the parameter editor for the TX PLL IP core you select, you

must set the following parameter values:

• PLL output frequency to one half the per-lane data rate of the IP core variation. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting drives the transceiver with the correct clock for the Interlaken lanes.

• PLL reference clock frequency to a frequency at which you can drive the TX PLL input reference clock. You must drive the external PLL reference clock input signal at the frequency you specify for this parameter.

Arria 10 devices and the Quartus II software support multiple options for configuring an Arria 10 TX PLL. Depending on the TX PLL IP core you select and the configuration options you prefer, you have a wide range of choices in parameterizing the external TX PLL for an Arria 10 variation.

You must connect the external TX PLL signals and the CPRI v6.0 IP core transceiver TX PLL interface signals according to the following rules:

• Connect the xcvr_ext_pll_clk input signal of the CPRI v6.0 IP core to the pll_clkout or

tx_serial_clk output signal of the external PLL IP core.

• If your CPRI v6.0 IP core is an RE slave, drive the input signal of the external PLL IP core with the output of the external cleanup PLL.

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Adding the External Reset Controller

User logic must provide the connection. Refer to the demonstration testbench for example working user logic including one correct method to instantiate and connect the external PLL to a single CPRI v6.0 IP core.

Related Information

Interface to the External PLL on page 3-48 Altera Transceiver PHY IP Core User Guide

Information about how to configure an external PLL for your Arria V GZ or Stratix V design.

Arria 10 Transceiver PHY User Guide

Information about how to configure an external PLL for your own Arria 10 design.

Adding the External Reset Controller

The CPRI v6.0 IP core requires that you provide reset control logic to handle the required reset sequence for the IP core transceiver on the device. Altera recommends that you generate and connect two Altera Transceiver PHY Reset Controller IP cores to perform this function, one reset controller for the TX transceiver and data path and one reset controller for the RX transceiver and data path in the CPRI v6.0 IP core. If you do not implement the device-specific correct reset sequence, the IP core does not function correctly in hardware.

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You can use the IP Catalog to generate Altera Transceiver PHY Reset Controller IP cores for the device family that your CPRI v6.0 IP core targets.

Follow the instructions in the Altera Transceiver PHY IP Core User Guide or the Arria 10 Transceiver PHY User Guide. The CPRI v6.0 IP core configures the Native PHY IP core for the target device family. You must configure the reset controllers to coordinate reset of the CPRI v6.0 IP core including the Native PHY IP core, and the external PLL IP core. In the case of Arria V GZ and Stratix V variations, the reset control‐ lers must also coordinate with the transceiver reconfiguration controller.

To configure a TX reset controller, in the Altera Transceiver PHY Reset Controller parameter editor, you must set the following parameter values:

• Set Input clock frequency to a value in the range of 100–150.

• Turn on Synchronize reset input.

• Turn on Use fast reset for simulation.

• Turn on Enable TX PLL reset control.

• Set pll_powerdown duration to the value of 10.

• Turn on Enable TX channel reset control.

• Leave all other parameters turned off or for the parameters that do not turn on or off, at their default values.

To configure an RX reset controller, in the Altera Transceiver PHY Reset Controller parameter editor, you must set the following parameter values:

• Set Input clock frequency to a value in the range of 100–150.

• Turn on Synchronize reset input.

• Turn on Use fast reset for simulation.

• Turn on Enable RX channel reset control.

• Leave all other parameters turned off or for the parameters that do not turn on or off, at their default

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values.

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Adding the Transceiver Reconfiguration Controller

2-15

You must connect the external reset controller signals and the CPRI v6.0 IP core reset controller interface signals according to the following rules. Refer to Integrating Your IP Core in Your Design: Required

External Blocks on page 2-11 for an illustration of the connections.

• Connect the tx_digitalreset, tx_analogreset, tx_ready, rx_digitalreset, rx_analogreset, and rx_ready output signals of the reset controllers to the xcvr_tx_digitalreset,

xcvr_tx_analogreset, xcvr_tx_ready, xcvr_rx_digitalreset, xcvr_rx_analogreset, and xcvr_rx_readyinput signals of the CPRI v6.0 IPcore, respectively.

• Connect the xcvr_rx_is_lockedtodata output pin of the CPRI v6.0 IP core to the rx_is_lockedto-

data input signal of the RX reset controller.

User logic must provide the connections. Refer to the demonstration testbench for example working user logic including one correct method to instantiate and connect the external reset controllers.

Related Information

• Interface to the External Reset Controller on page 3-47

• Integrating Your IP Core in Your Design: Required External Blocks on page 2-11 Figure illustrates the required connections.

• Altera Transceiver PHY IP Core User Guide Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria V GZ or Stratix V design.

• Arria 10 Transceiver PHY User Guide Information about how to configure the Altera Transceiver PHY Reset Controller for your Arria 10 design.

Adding the Transceiver Reconfiguration Controller

CPRI v6.0 IP cores that target Arria V GZ and Stratix V devices require an external reconfiguration controller to compile and to function correctly in hardware. CPRI v6.0 IP cores that target Arria 10 devices include a transceiver reconfiguration controller block and do not require an external reconfigura‐ tion controller.

You can use the IP Catalog to generate the Altera Transceiver Reconfiguration Controller IP core. When you configure the Altera Transceiver Reconfiguration Controller, you must specify the number of

reconfiguration interfaces. The number of reconfiguration interfaces required for the CPRI v6.0 IP core is two . You can configure your reconfiguration controller with additional interfaces if your design connects with multiple transceiver IP cores. You can leave other options at the default settings or modify them for your preference.

You should connect the reconfig_to_xcvr and reconfig_from_xcvr ports of the CPRI v6.0 IP core to the corresponding ports of the reconfiguration controller.

You must drive the CPRI v6.0 IP core reconfig_clk input port and the Altera Transceiver Reconfigura‐ tion Controller mgmt_clk_clk input port from the same clock source. Drive both ports at a clock frequency in the range of 100–150MHz.

Related Information

• Arria V GZ and Stratix V Transceiver Reconfiguration Interface on page 3-46

• Altera Transceiver PHY IP Core User Guide For more information about the Altera Transceiver Reconfiguration Controller.

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Post-fit timing

simulation netlist

Post-fit timing simulation (3)

Post-fit functional

simulation netlist

Post-fit functional

simulation

Analysis & Synthesis

Fitter

(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow

Gate-Level Simulation

Post-synthesis

functional

simulation

Post-synthesis functional

simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry

(HDL, Qsys, DSP Builder)

Altera Simulation

Models

EDA Netlist Writer

2-16

Simulating Altera IP Cores

You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.

Figure 2-5: Simulation in Quartus II Design Flow

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Note: Altera IP supports a variety of simulation models, including simulation-specific IP functional

simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

Related Information

Simulating Altera Designs

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Understanding the Testbench

Altera provides a demonstration testbench with the CPRI v6.0 IP core. If you click Example Design in the CPRI v6.0 parameter editor, the Quartus II software generates the

demonstration testbench. The parameter editor prompts you for the desired location of the testbench. The testbench is static and does not necessarily match your IP core variation; you can generate it without

generating an IP core. The testbench scripts generate a DUT that matches the testbench, but you must manually set the appropriate values for the DUT in the parameter editor before you create the demonstra‐ tion testbench.

The testbench performs the following sequence of actions with the static DUT:

1. Enables transmission on the CPRI link by setting the tx_enable bit (bit [0]) of the CPRI v6.0 IP core

L1_CONFIG register at offset 0x8 (and resetting all other fields of the register)>

2. Configures the DUT at the highest possible HDLC bit rate (for CPRI line bit rate 6.144 Gbps), by

setting the tx_slow_cm_rate field of the CPRI v6.0 CM_CONFIG register at offset 0x1C to the value of 3'b110.

3. Reads the CM_CONFIG regster to confirm settings.

4. After the DUT and the testbench achieve link synchronization, executes the following transactions:

Understanding the Testbench

2-17

a. Performs ten write transactions to the AUX Tx interface and confirms the testbench receives them

on the CPRI link.

b. Performs three write transactions to the VS interface and confirms the testbench receives them

from the DUT on the CPRI link.

c. Performs three write transactions to the Ctrl_AxC interface and confirms the testbench receives

them from the DUT on the CPRI link.

d. Performs 50 HDLC transactions and confirms the testbench receives them from the DUT on the

CPRI link.

e. Performs ten write transactions to the MI interface and confirms the testbench receives them from

the DUT on the CPRI link.

f. Calculates the round-trip delay through the IP core.

Running the Testbench

To run the Altera CPRI v6.0 IP core demonstration testbench, follow these steps.

1. In the Quartus II software IP Catalog, select the CPRI v6.0 IP core and click Add.

2. When prompted, you can specify any output file type (HDL). This setting is relevant only for synthesis

and does not impact simulation of the demonstration testbench.

3. In the CPRI v6.0 parameter editor, set the following parameter values:

Table 2-4: CPRI v6.0 IP Core Variation for Demonstration Testbench

The testbench scripts require that you set these values in the CPRI v6.0 parameter editor before you click Example Design. The scripts generate the DUT but they require that you provide the parameter values.

Parameter Value

Bit rate (Mbit/s) 6144.0

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Running the Testbench

Parameter Value

Operation mode Master Supported receiver CDR frequency (MHz) 307.2

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Receiver FIFO depth (value shown is log2 of actual

depth) Enable auto-rate negotiation Turn off Enable auto-rate negotiation down to 614.4Mbps Not available Supported CPU interface standard AvalonMM Auxiliary latency cycle(s) 0 Enable auxiliary interface Turn on Enable all control word access Turn off Enable direct IQ mapping interface Turn off Enable direct ctrl_axc access interface Turn on Enable direct vendor specific access interface Turn on Enable start-up sequence state machine Turn off Enable L1 inband protocol negotiator Not available Enable real-time vendor specific interface (R-16A) Not available Enable Z.130.0 access interface Turn off Enable direct HDLC serial interface Turn on Enable IEEE 802.3 100BASE-X 100Mbps MII Turn on L2 Ethernet PCS Tx/Rx FIFO depth (value shown is

Turn off

log2 of actual depth) Enable debug interface Turn off Enable transceiver PMA forward loopback path (Tx

Turn off

to Rx) Enable forward loopback path (Tx to Rx) Turn off Enable reversed loopback path (Rx to Tx) Turn off

4. In the CPRI v6.0 parameter editor, click the Example Design button and specify the desired location

of the testbench.

5. After you generate the demonstration testbench, in the Quartus II software, click View > Utility Windows > Tcl Console.

6. In the Tcl Console, change directory to your specified testbench directory's ip_sim subdirectory.

7. Type source gen_sim_verilog.tcl or source gen_sim_vhdl.tcl, depending on the language of

the model you wish to simulate. Running this script generates the DUT and testbench files.

8. If you are using a simulator that requires that you open a user interface, open your target simulator.

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Running the Testbench

2-19

Note: You must select a simulator that is supported by the Quartus II v14.0 or v14.0 Arria 10 Edition

software, as appropriate.

9. Change directory to your specified testbench directory's testbench/<simulator vendor> subdirectory.

10.Execute the simulation script in the directory.

• In the Mentor Graphics ModelSim simulator, type do run_altera_cpri_v6_tb.tcl

• In the Synopsys VCS-MX simulator, type sh run_altera_cpri_v6_vcsmx_tb.sh

• In the Cadence NCSIM simulator, type sh run_altera_cpri_v6_tb.sh

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+ 85 hidden pages

Altera CPRI v6.0 MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

CPRI v6.0 MegaCore Function User Guide

Contents

About the CPRI v6.0 IP Core

CPRI v6.0 IP Core Supported Features

CPRI v6.0 IP Core Device Family and Speed Grade Support

Device Family Support

CPRI v6.0 IP Core Performance: Device Speed Grade Support

IP Core Verification

Resource Utilization for CPRI v6.0 IP Cores

Release Information

Installation and Licensing Features

OpenCore Plus Evaluation

OpenCore Plus Time-Out Behavior

Getting Started with the CPRI v6.0 IP Core

Installation and Licensing

Specifying IP Core Parameters and Options

Files Generated for Altera IP Cores

CPRI v6.0 IP Core Parameters

Integrating Your IP Core in Your Design: Required External Blocks

Adding the Clean-Up PLL

Adding the External TX PLL

Adding the External Reset Controller

Adding the Transceiver Reconfiguration Controller

Simulating Altera IP Cores

Understanding the Testbench

Running the Testbench