Altera CIC MegaCore Function User Manual
CIC IP Core
User Guide
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2014.12.15
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TOC-2
Contents
About The CIC IP Core.......................................................................................1-1
CIC IP Core Getting Started............................................................................... 2-1
Altera DSP IP Core Features...................................................................................................................... 1-1
CIC IP Core Features...................................................................................................................................1-1
CIC IP Core Device Family Support.........................................................................................................1-2
DSP IP Core Verification............................................................................................................................1-2
CIC IP Core Release Information..............................................................................................................1-2
CIC IP Core Performance and Resource Utilization..............................................................................1-3
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
CIC IP Core OpenCore Plus Timeout Behavior......................................................................... 2-2
IP Catalog and Parameter Editor...............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-3
Files Generated for Altera IP Cores...............................................................................................2-4
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
DSP Builder Design Flow............................................................................................................................2-8
CIC IP Core Functional Description..................................................................3-1
Variable Rate Change Factors....................................................................................................................3-2
Multichannel Support................................................................................................................................. 3-2
Multiple Input Single Output (MISO)..........................................................................................3-2
Single Input Multiple Output (SIMO)..........................................................................................3-3
Output Options............................................................................................................................................3-4
Output Data Width..........................................................................................................................3-4
Output Rounding.............................................................................................................................3-5
Hogenauer Pruning......................................................................................................................... 3-6
FIR Filter Compensation Coefficients...................................................................................................... 3-6
CIC IP Core Parameters..............................................................................................................................3-7
CIC IP Core Interfaces and Signals...........................................................................................................3-9
Avalon-ST Interfaces in DSP IP Cores....................................................................................... 3-10
CIC IP Core Signals.......................................................................................................................3-11
Avalon-ST Interface Data Transfer Timing...............................................................................3-12
Packet Data Transfers....................................................................................................................3-12
Document Revision History................................................................................4-1
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2014.12.15
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101 Innovation Drive, San Jose, CA 95134
About The CIC IP Core
1
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The Altera® CIC IP core implements a cascaded integrator-comb (CIC) filter with data ports that are
compatible with the Avalon® Streaming (Avalon-ST) interface. CIC filters (also known as Hogenauer
filters) are computationally efficient for extracting baseband signals from narrow-band sources using
decimation. They also construct narrow-band signals from processed baseband signals using
interpolation.
CIC filters use only adders and registers; they require no multipliers to handle large rate changes.
Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely
used in sample rate conversion designs such as digital down converters (DDC) and digital up converters
(DUC).
Altera DSP IP Core Features
• Avalon Streaming (Avalon-ST) interfaces
• DSP Builder ready
• Testbenches to verify the IP core
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
CIC IP Core Features
• Interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurable
number of stages (1 to 12), and two differential delay options (1 or 2).
• Single clock domain with selectable number of interfaces and a maximum of 1,024 channels.
• Selectable data storage options with an option to use pipelined integrators.
• Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width).
• Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and
Hogenauer pruning support.
• Optimization for speed by specifying the number of pipeline stages used by each integrator.
• Compensation filter coefficients generation.
• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.
• DSP Builder ready.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
1-2
CIC IP Core Device Family Support
CIC IP Core Device Family Support
Altera offers the following device support levels for Altera IP cores:
• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family.
The IP core meets all functional requirements, but might still be undergoing timing analysis for the
device family. You can use it in production designs with caution.
• Final support—Altera verifies the IP core with final timing models for this device family. The IP core
meets all functional and timing requirements for the device family. You can use it in production
designs.
Table 1-1: Device Family Support
Device Family Support
Arria® II GX Final
Arria II GZ Final
ArriaV Final
Arria10 Final
Cyclone® IV GX Final
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Stratix® IV GT Final
Stratix IV GX/E Final
Stratix V Final
Other device families No support
DSP IP Core Verification
Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality
and correctness. Altera generates custom variations of the IP core to exercise the various parameter
options and thoroughly simulates the resulting simulation models with the results verified against master
simulation models.
CIC IP Core Release Information
Table 1-2: CIC IP Core Release Information
Item Description
Version 14.1
Release Date December 2014
Ordering Code IP-CIC
Product ID(s) 00BB
Vendor ID(s) 6AF7
Altera Corporation
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CIC IP Core Performance and Resource Utilization
Altera verifies that the current version of the Quartus II software compiles the previous version of each IP
core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous
version. The Altera IP Release Notes lists any exceptions.
Related Information
• Altera IP Release Notes
• Errata for CIC IP core in the Knowledge Base
CIC IP Core Performance and Resource Utilization
The following parameters apply:
• Number of stages: 8
• Rate change factor: 8
• Differential delay: 1
• Integrator data storage: Memory (whenever possible)
• Differentiator data storage: Memory (whenever possible)
• Input data width: 16
• Output data width: Full precision
• Output rounding: No rounding
1-3
The target f
MAX
is 1 GHz.
Table 1-3: CIC IP Core Performance
Typical performance using the Quartus II software with the Arria V (5AGXFB3H4F40C4), Cyclone V
(5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices
Device Filter Type ALM
Memory Registers
M10K M20K Primary Secondary
f
MAX
(MHz)
Arria V Decimator 493 2 -- 1,149 5 207.34
Arria V Decimator 5
1,162 2 -- 3,749 6 207
Channels
Arria V Decimator 5
911 37 -- 1,722 6 255
Channels 3
Interfaces
Arria V Decimator
352 1 -- 785 12 304
Hogenauer Pruning
Arria V Decimator
463 2 -- 1,055 5 198.69
Trunction
Arria V Decimator Variable
919 37 -- 1,730 7 256
Rate Change
Arria V Interpolator 326 1 -- 728 18 320
Arria V Interpolator 5
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762 1 -- 2,369 27 288
Channels
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1-4
CIC IP Core Performance and Resource Utilization
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Device Filter Type ALM
Arria V Interpolator 5
886 27 -- 1,776 17 232.61
Memory Registers
M10K M20K Primary Secondary
Channels 3
Interfaces
Arria V Interpolator
352 1 -- 785 12 304
Convergent
Rounding
Arria V Interpolator
889 27 -- 1,772 23 235
Variable Rate
Change
CycloneVDecimator 492 2 -- 1,137 17 182
CycloneVDecimator 5
1,162 2 -- 3,748 8 190.15
Channels
CycloneVDecimator 5
906 37 -- 1,719 9 204
Channels 3
Interfaces
CycloneVDecimator
352 1 -- 784 14 246
Hogenauer Pruning
f
MAX
(MHz)
CycloneVDecimator
463 2 -- 1,054 4 177
Truncation
CycloneVDecimator Variable
917 37 -- 1,730 5 193.27
Rate Change
CycloneVInterpolator 324 1 -- 709 37 264
CycloneVInterpolator 5
760 1 -- 2,383 11 235
Channels
CycloneVInterpolator 5
890 27 -- 1,747 48 168
Channels 3
Interfaces
CycloneVInterpolator
352 1 -- 784 14 246.06
Convergent
Rounding
CycloneVInterpolator
894 27 -- 1,725 70 165
Variable Rate
Change
StratixVDecimator 515 -- 1 1,152 6 377
StratixVDecimator 5
1,176 -- 1 3,750 8 413
Channels
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CIC IP Core Performance and Resource Utilization
1-5
Device Filter Type ALM
StratixVDecimator 5
1,891 -- 11 5,562 8 450.05
Memory Registers
M10K M20K Primary Secondary
f
MAX
Channels 3
Interfaces
StratixVDecimator
361 -- 0 790 13 450
Hogenauer Pruning
StratixVDecimator
483 -- 1 1,059 4 376
Truncation
StratixVDecimator Variable
1,900 -- 11 5,574 3 450
Rate Change
StratixVInterpolator 335 -- 0 737 14 450.05
StratixVInterpolator 5
771 -- 0 2,390 8 450
Channels
StratixVInterpolator 5
1,625 -- 8 4,635 70 450
Channels 3
Interfaces
StratixVInterpolator
361 -- 0 790 13 450
Convergent
Rounding
(MHz)
Arria 10 Interpolator
Variable Rate
Change
464 -- 0 128 128 451
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2014.12.15
acds
quartus - Contains the Quartus II software
ip - Contains the Altera IP Library and third-party IP cores
altera - Contains the Altera IP Library source code
<IP core name> - Contains the IP core source files
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101 Innovation Drive, San Jose, CA 95134
CIC IP Core Getting Started
2
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Installing and Licensing IP Cores
The Altera IP Library provides many useful IP core functions for your production use without purchasing
an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license
for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation
and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance,
visit the Self Service Licensing Center to obtain a license number for any Altera product.
Figure 2-1: IP Core Installation Path
Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is
<home directory>/altera/ <version number>.
Related Information
• Altera Licensing Site
• Altera Software Installation and Licensing Manual
OpenCore Plus IP Evaluation
Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and
hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take
your design to production. OpenCore Plus supports the following evaluations:
• Simulate the behavior of a licensed IP core in your system.
• Verify the functionality, size, and speed of the IP core quickly and easily.
• Generate time-limited device programming files for designs that include IP cores.
• Program a device with your IP core and verify your design in hardware.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
2-2
CIC IP Core OpenCore Plus Timeout Behavior
OpenCore Plus evaluation supports the following two operation modes:
• Untethered—run the design containing the licensed IP for a limited time.
• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a
connection between your board and the host computer.
Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times
out.
CIC IP Core OpenCore Plus Timeout Behavior
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If
there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the
time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus
II software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCore
Plus evaluation program. After you activate the feature, do not delete these files..
When the evaluation time expires, the data output signal goes low.
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Related Information
• AN 320: OpenCore Plus Evaluation of Megafunctions
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note:
The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
Use the following features to help you quickly locate and select an IP core:
• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no
project open, select the Device Family in IP Catalog.
• Type in the Search field to locate any full or partial IP core name in IP Catalog.
• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's
installation folder, and view links to documentation.
• Click Search for Partner IP, to access partner IP information on the Altera website.
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