Altera CIC MegaCore Function User Manual

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CIC IP Core

User Guide

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TOC-2

About The CIC IP Core.......................................................................................1-1

CIC IP Core Getting Started............................................................................... 2-1

Altera DSP IP Core Features...................................................................................................................... 1-1

CIC IP Core Features...................................................................................................................................1-1

CIC IP Core Device Family Support.........................................................................................................1-2

DSP IP Core Verification............................................................................................................................1-2

CIC IP Core Release Information..............................................................................................................1-2

CIC IP Core Performance and Resource Utilization..............................................................................1-3

Installing and Licensing IP Cores..............................................................................................................2-1

OpenCore Plus IP Evaluation........................................................................................................ 2-1

CIC IP Core OpenCore Plus Timeout Behavior......................................................................... 2-2

IP Catalog and Parameter Editor...............................................................................................................2-2

Specifying IP Core Parameters and Options............................................................................................2-3

Files Generated for Altera IP Cores...............................................................................................2-4

Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7

DSP Builder Design Flow............................................................................................................................2-8

CIC IP Core Functional Description..................................................................3-1

Variable Rate Change Factors....................................................................................................................3-2

Multichannel Support................................................................................................................................. 3-2

Multiple Input Single Output (MISO)..........................................................................................3-2

Single Input Multiple Output (SIMO)..........................................................................................3-3

Output Options............................................................................................................................................3-4

Output Data Width..........................................................................................................................3-4

Output Rounding.............................................................................................................................3-5

Hogenauer Pruning......................................................................................................................... 3-6

FIR Filter Compensation Coefficients...................................................................................................... 3-6

CIC IP Core Parameters..............................................................................................................................3-7

CIC IP Core Interfaces and Signals...........................................................................................................3-9

Avalon-ST Interfaces in DSP IP Cores....................................................................................... 3-10

CIC IP Core Signals.......................................................................................................................3-11

Avalon-ST Interface Data Transfer Timing...............................................................................3-12

Packet Data Transfers....................................................................................................................3-12

Document Revision History................................................................................4-1

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About The CIC IP Core

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The Altera® CIC IP core implements a cascaded integrator-comb (CIC) filter with data ports that are compatible with the Avalon® Streaming (Avalon-ST) interface. CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation. They also construct narrow-band signals from processed baseband signals using interpolation.

CIC filters use only adders and registers; they require no multipliers to handle large rate changes. Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample rate conversion designs such as digital down converters (DDC) and digital up converters (DUC).

Altera DSP IP Core Features

• Avalon Streaming (Avalon-ST) interfaces

• DSP Builder ready

• Testbenches to verify the IP core

• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators

CIC IP Core Features

• Interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurable number of stages (1 to 12), and two differential delay options (1 or 2).

• Single clock domain with selectable number of interfaces and a maximum of 1,024 channels.

• Selectable data storage options with an option to use pipelined integrators.

• Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width).

• Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and Hogenauer pruning support.

• Optimization for speed by specifying the number of pipeline stages used by each integrator.

• Compensation filter coefficients generation.

• IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.

• DSP Builder ready.

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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1-2

CIC IP Core Device Family Support

Altera offers the following device support levels for Altera IP cores:

• Preliminary support—Altera verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. You can use it in production designs with caution.

• Final support—Altera verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. You can use it in production designs.

Table 1-1: Device Family Support

Device Family Support

Arria® II GX Final Arria II GZ Final ArriaV Final Arria10 Final Cyclone® IV GX Final

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Stratix® IV GT Final Stratix IV GX/E Final Stratix V Final Other device families No support

DSP IP Core Verification

Before releasing a version of an IP core, Altera runs comprehensive regression tests to verify its quality and correctness. Altera generates custom variations of the IP core to exercise the various parameter options and thoroughly simulates the resulting simulation models with the results verified against master simulation models.

CIC IP Core Release Information

Table 1-2: CIC IP Core Release Information

Item Description

Version 14.1 Release Date December 2014 Ordering Code IP-CIC Product ID(s) 00BB Vendor ID(s) 6AF7

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CIC IP Core Performance and Resource Utilization

Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. Altera does not verify that the Quartus II software compiles IP core versions older than the previous version. The Altera IP Release Notes lists any exceptions.

Related Information

• Altera IP Release Notes

• Errata for CIC IP core in the Knowledge Base

CIC IP Core Performance and Resource Utilization

The following parameters apply:

• Number of stages: 8

• Rate change factor: 8

• Differential delay: 1

• Integrator data storage: Memory (whenever possible)

• Differentiator data storage: Memory (whenever possible)

• Input data width: 16

• Output data width: Full precision

• Output rounding: No rounding

1-3

The target f

MAX

is 1 GHz.

Table 1-3: CIC IP Core Performance

Typical performance using the Quartus II software with the Arria V (5AGXFB3H4F40C4), Cyclone V (5CGXFC7D6F31C6), and Stratix V (5SGSMD4H2F35C2) devices

Device Filter Type ALM

Memory Registers

M10K M20K Primary Secondary

MAX

(MHz)

Arria V Decimator 493 2 -- 1,149 5 207.34 Arria V Decimator 5

1,162 2 -- 3,749 6 207

Channels

Arria V Decimator 5

911 37 -- 1,722 6 255 Channels 3 Interfaces

Arria V Decimator

352 1 -- 785 12 304 Hogenauer Pruning

Arria V Decimator

463 2 -- 1,055 5 198.69 Trunction

Arria V Decimator Variable

919 37 -- 1,730 7 256 Rate Change

Arria V Interpolator 326 1 -- 728 18 320 Arria V Interpolator 5

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762 1 -- 2,369 27 288 Channels

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CIC IP Core Performance and Resource Utilization

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Device Filter Type ALM

Arria V Interpolator 5

886 27 -- 1,776 17 232.61

Memory Registers

M10K M20K Primary Secondary

Channels 3 Interfaces

Arria V Interpolator

352 1 -- 785 12 304 Convergent Rounding

Arria V Interpolator

889 27 -- 1,772 23 235 Variable Rate Change

CycloneVDecimator 492 2 -- 1,137 17 182

CycloneVDecimator 5

1,162 2 -- 3,748 8 190.15 Channels

CycloneVDecimator 5

906 37 -- 1,719 9 204 Channels 3 Interfaces

CycloneVDecimator

352 1 -- 784 14 246 Hogenauer Pruning

MAX

(MHz)

CycloneVDecimator

463 2 -- 1,054 4 177 Truncation

CycloneVDecimator Variable

917 37 -- 1,730 5 193.27 Rate Change

CycloneVInterpolator 324 1 -- 709 37 264

CycloneVInterpolator 5

760 1 -- 2,383 11 235 Channels

CycloneVInterpolator 5

890 27 -- 1,747 48 168 Channels 3 Interfaces

CycloneVInterpolator

352 1 -- 784 14 246.06 Convergent Rounding

CycloneVInterpolator

894 27 -- 1,725 70 165 Variable Rate Change

StratixVDecimator 515 -- 1 1,152 6 377

StratixVDecimator 5

1,176 -- 1 3,750 8 413 Channels

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CIC IP Core Performance and Resource Utilization

1-5

Device Filter Type ALM

StratixVDecimator 5

1,891 -- 11 5,562 8 450.05

Memory Registers

M10K M20K Primary Secondary

MAX

Channels 3 Interfaces

StratixVDecimator

361 -- 0 790 13 450 Hogenauer Pruning

StratixVDecimator

483 -- 1 1,059 4 376 Truncation

StratixVDecimator Variable

1,900 -- 11 5,574 3 450 Rate Change

StratixVInterpolator 335 -- 0 737 14 450.05

StratixVInterpolator 5

771 -- 0 2,390 8 450 Channels

StratixVInterpolator 5

1,625 -- 8 4,635 70 450 Channels 3 Interfaces

StratixVInterpolator

361 -- 0 790 13 450 Convergent Rounding

(MHz)

Arria 10 Interpolator

Variable Rate Change

464 -- 0 128 128 451

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore® IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus® II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 2-1: IP Core Installation Path

Note: The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is

<home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware.

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CIC IP Core OpenCore Plus Timeout Behavior

OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

out.

CIC IP Core OpenCore Plus Timeout Behavior

All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If there is more than one IP core in a design, the time-out behavior of the other IP cores may mask the timeout behavior of a specific IP core .

All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If there is more than one IP core in a design, a specific IP core's time-out behavior may be masked by the time-out behavior of the other IP cores. For IP cores, the untethered time-out is 1 hour; the tethered timeout value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus II software uses OpenCore Plus Files (.ocp) in your project directory to identify your use of the OpenCore Plus evaluation program. After you activate the feature, do not delete these files..

When the evaluation time expires, the data output signal goes low.

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Related Information

• AN 320: OpenCore Plus Evaluation of Megafunctions

IP Catalog and Parameter Editor

The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize, and generate files representing your custom IP variation.

Note:

The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard™ Plug-In Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.

The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (.qsys) or Quartus II IP file (.qip) representing the IP core in your project. You can also parameterize an IP variation without an open project.

Use the following features to help you quickly locate and select an IP core:

• Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog.

• Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, and view links to documentation.

• Click Search for Partner IP, to access partner IP information on the Altera website.

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Search for installed IP cores

Double-click to customize, right-click for detailed information

Show IP only for target device

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Figure 2-2: Quartus II IP Catalog

Specifying IP Core Parameters and Options

2-3

Note: The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includes

exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook.

Specifying IP Core Parameters and Options

You can quickly configure a custom IP variation in the parameter editor. Use the following steps to specify IP core options and parameters in the parameter editor. Refer to Specifying IP Core Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.

2. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys. Click OK.

3. Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.

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View IP port and parameter details

Apply preset parameters for specific applications

Specify your IP variation name and target device

2-4

Files Generated for Altera IP Cores

• Optionally select preset parameter values if provided for your IP core. Presets specify initial

parameter values for specific applications.

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for processing the IP core files in other EDA tools.

4. Click Generate HDL, the Generation dialog box appears.

5. Specify output file generation options, and then click Generate. The IP variation files generate

according to your specifications.

6. To generate a simulation testbench, click Generate > Generate Testbench System.

7. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.

8. Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.

9. After generating and instantiating your IP variation, make appropriate pin assignments to connect

ports.

Figure 2-3: IP Parameter Editor

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Files Generated for Altera IP Cores

The Quartus II software generates the following IP core output file structure:

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<your_testbench>_tb.csv <your_testbench>_tb.spd

<your_ip>.cmp - VHDL component declaration file

<your_ip>.ppf - XML I/O pin information file <your_ip>.qip - Lists IP synthesis files <your_ip>.sip - Contains assingments for IP simulation files

<your_ip>.v or .vhd

Top-level IP synthesis file

<your_ip>.v or .vhd Top-level simulation file

<simulator_setup_scripts>

<your_ip>.qsys - System or IP integration file

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

<your_ip>_generation.rpt - IP generation report <your_ip>.debuginfo - Contains post-generation information

<your_ip>.html - Connection and memory map data <your_ip>.bsf - Block symbol schematic <your_ip>.spd - Combines simulation scripts for multiple cores

<your_ip>_tb.qsys

Testbench system file

<your_ip>.sopcinfo - Software tool-chain integration file

<EDA tool setup

scripts>

<your_ip>

IP variation files

<testbench>_tb

testbench system

sim

Simulation files

synth

IP synthesis files

sim

simulation files

Simulator scripts

<testbench>_tb

<ip subcores> n

Subcore libraries

sim

Subcore

Simulation files

synth

Subcore

synthesis files

<your_ip> n

IP variation files

testbench files

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Figure 2-4: IP Core Generated Files

Files Generated for Altera IP Cores

2-5

Table 2-1: IP Core Generated Files

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File Name Description

<my_ip>.qsys

<system>.sopcinfo Describes the connections and IP component parameterizations in

The Qsys system or top-level IP variation file. <my_ip> is the name that you give your IP variation.

your Qsys system. You can parse its contents to get requirements when you develop software drivers for IP components.

Downstream tools such as the Nios II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.

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Files Generated for Altera IP Cores

File Name Description

<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that

contains local generic and port definitions that you can use in VHDL design files.

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<my_ip>.html

A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.

<my_ip>_generation.rpt IP or Qsys generation log file. A summary of the messages during IP

generation.

<my_ip>.debuginfo Contains post-generation information. Used to pass System Console

and Bus Analyzer Toolkit information about the Qsys interconnect. The Bus Analysis Toolkit uses this file to identify debug components in the Qsys interconnect.

<my_ip>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Quartus II software.

<my_ip>.csv Contains information about the upgrade status of the IP component. <my_ip>.bsf A Block Symbol File (.bsf) representation of the IP variation for use

in Quartus II Block Diagram Files (.bdf).

<my_ip>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<my_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for

IP components created for use with the Pin Planner.

<my_ip>_bb.v You can use the Verilog black-box (_bb.v) file as an empty module

declaration for use as a black box.

<my_ip>.sip Contains information required for NativeLink simulation of IP

components. You must add the .sip file to your Quartus project.

<my_ip>_inst.v or _inst.vhd HDL example instantiation template. You can copy and paste the

contents of this file into your HDL file to instantiate the IP variation.

<my_ip>.regmap If the IP contains register information, the .regmap file generates.

The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This enables register display views and user customizable statistics in System Console.

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Simulating Altera IP Cores in other EDA Tools

File Name Description

2-7

<my_ip>.svd

<my_ip>.v

<my_ip>.vhd

mentor/

aldec/

/synopsys/vcs

/synopsys/vcsmx

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Qsys system.

During synthesis, the .svd files for slave interfaces visible to System Console masters are stored in the .sof file in the debug section. System Console reads this section, which Qsys can query for register map information. For system slaves, Qsys can access the registers by name.

HDL files that instantiate each submodule or child IP core for synthesis or simulation.

Contains a ModelSim® script msim_setup.tcl to set up and run a simulation.

Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a simulation.

Contains a shell script vcs_setup.sh to set up and run a VCS

simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to

set up and run a VCS MX® simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/submodules Contains HDL files for the IP core submodule. <child IP cores>/ For each generated child IP core directory, Qsys generates /synth and /

sim sub-directories.

Simulating Altera IP Cores in other EDA Tools

The Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench. You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts. NativeLink launches your preferred simulator from within the Quartus II software.

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Post-fit timing

simulation netlist

Post-fit timing simulation (3)

Post-fit functional

simulation netlist

Post-fit functional

simulation

Analysis & Synthesis

Fitter

(place-and-route)

TimeQuest Timing Analyzer

Device Programmer

Quartus II Design Flow

Gate-Level Simulation

Post-synthesis

functional

simulation

Post-synthesis functional

simulation netlist

(Optional) Post-fit timing simulation

RTL Simulation

Design Entry

(HDL, Qsys, DSP Builder)

Altera Simulation

Models

EDA Netlist Writer

2-8

DSP Builder Design Flow

Figure 2-5: Simulation in Quartus II Design Flow

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Note: Post-fit timing simulation is supported only for Stratix IV and Cyclone IV devices in the current

version of the Quartus II software. Altera IP supports a variety of simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.

Related Information

Simulating Altera Designs

DSP Builder Design Flow

DSP Builder shortens digital signal processing (DSP) design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment.

This IP core supports DSP Builder. Use the DSP Builder flow if you want to create a DSP Builder model that includes an IP core variation; use IP Catalog if you want to create an IP core variation that you can instantiate manually in your design. For more information about the DSP Builder flow, refer to the

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Related Information

Using MegaCore Functions chapter in the DSP Builder Handbook.

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CIC IP Core Functional Description

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You can select either a decimation or interpolation CIC filter. A decimation CIC filter comprises a cascade of integrators (integrator), followed by a down sampling block (decimator) and a cascade of differentiators (called the differentiator or comb section). Similarly an interpolation CIC filter comprises a cascade of differentiators, followed by an up sampling block (interpolator) and a cascade of integrators.

In a CIC filter, both the integrator and comb sections have the same number of integrators and differen‐ tiators. Each pairing of integrator and differentiator is a stage. The number of stages (N) has a direct effect on the frequency response of a CIC filter. You determine the response of the filter by configuring:

• The number of stages N

• The rate change factor R

• The number of delays in the differentiators (differential delay) M. Generally, set the differential delay

to 1 or 2.

Figure 3-1: Three-stage CIC Decimation Filter Frequency Response

CIC decimation filter with N = 3, M = 2 and R = 32

ISO 9001:2008 Registered

clk

reset_n

clken

in_error

rate

in_valid

out_error

out_ready

in_ready

out_valid

8 28

3-2

Variable Rate Change Factors

You can optionally set minimum and maximum values for the decimator or interpolator rate change factors and enable the rate change factors to be set at run time. With these options, the CIC provides an additional rate port that you can use to specify the rate change factor.

Note: With variable rate change factors, reset the IP core when you change the rate change factor,

otherwise the CIC uses previous memory and register values. You cannot change the filter mode (interpolation or decimation) at run time.

Figure 3-2: Variable Rate Change Decimation CIC Filter Timing Diagram

The out_valid signal changes its period according to the variable rate change.

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Multichannel Support

Often many channels of data in a digital signal processing (DSP) system require filtering by CIC filters with the same configuration. You can combine them into one filter, which shares the adders that exist in each stage and reduces the overall resource utilization.

Using a combined filter uses fewer resources than using many individual CIC filters. For example, a twochannel parallel filter requires two clock cycles to calculate two outputs. The resulting hardware needs to run at twice the data rate of an individual filter, which is especially useful for higher rate changes where adders grow particularly large.

Note:

To minimize the number of logic elements, use a multiple input single output (MISO) architecture for decimation filters, and a single input multiple output (SIMO) architecture for interpolation filters.

Multiple Input Single Output (MISO)

In many practical designs, channel signals come from different input interfaces. On each input interface, the same parameters including rate change factors apply to the channel data that the CIC filter is going to process. The CIC IP core allows multiple input single output (MISO) decimation filters, which allows the flexibility to exploit time sharing of the low-rate differentiator sections.

The CIC achieves time sharing by providing multiple input interfaces and processing chains for the high rate portions. It then combines all of the processing associated with the lower rate portions into a single

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D D D

(A, C)

(B, D)

(A, B, C, D)

I I I

D D D

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Single Input Multiple Output (SIMO)

processing chain. This strategy can lead to full utilization of the resources and represents the most efficient hardware implementation.

Figure 3-3: Multiple Input Single Output Architecture For Four Channels

The symbols A, B, C, D are multiplexed into one output A, B, C, D

The sampling frequency of the input data only allows time multiplexes of two channels per bus. Therefore, you must configure the CIC filter with two input interfaces. For two interfaces, the rate change factor must also be at least two to exploit this architecture. The CIC support up to 1,024 channels by using multiple input interfaces in this way.

3-3

Note:

The CIC applies the MISO architecture when you select a decimation filter and the number of interfaces is greater than one.

Single Input Multiple Output (SIMO)

With single input multiple output (SIMO), all the channel signals presented for filtering come from a single input interface.

Like the MISO, you can share the low sampling rate differentiator section among more channels than the higher sampling frequency integrator sections. Therefore, this architecture features a single instance of the differentiator section and multiple parallel instances of the integrator sections.

After processing by the differentiator section, the CIC splits the channel signals into multiple parallel sections for processing in a high sampling frequency by the integrator sections.

CIC IP Core Functional Description

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I I I

(A,B,C,D,E,F,G,H)

(A,E)

(B,F)

(C,G)

(D,H)

D D D

I I I

3-4

Output Options

Figure 3-4: Single Input Multiple Output Architecture with Eight Channels

The symbols A, B, C, D, E, F, G, H are demultiplexed into four outputs A, E; B, F; C, G; and D, H

The required sampling frequency of the output data only allows time multiplexes of two channels per bus. Therefore, you must configure the CIC filter with four output interfaces. The rate change factor must also be at least four to exploit this architecture, but this example shows a rate change of eight.

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Note:

The CIC applies a SIMO when you select an interpolation filter and the number of interfaces is greater than one.

The total number of input channels must be a multiple of the number of interfaces. To satisfy this require‐ ment, you may need to either insert dummy channels or use more than one CIC IP core.

The CIC transfers data as packets using Avalon Avalon-ST interfaces.

Related Information

AN442: Tool Flow Design of Digital IF for Wireless Systems

An example design using multichannel MISO and SIMO architectures.

Output Options

You can select output options for the output data bit width and rounding options.

Output Data Width

If you select an output data width that is smaller than the full output resolution data width, apply the Hogenauer pruning technique to reduce the data widths across the filter stages and hence the overall resource utilization.

For a decimation filter, the gain at the output of the filter is:

G = RM

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Therefore, the data width at the output stage for if full resolution is:

= Bin + Nlog2(RM)

out

where Bin is the input data width.

CIC IP Core Functional Description

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Output Rounding

3-5

Note: A data width of B

is required for each integrator and differentiator for no data loss.

out

For an interpolation filter, the gain at each filter stage is:

Hence the required data width at the ith stage is:

Wi = [Bin + log2(Gi)]

and the data width at the output stage is:

= [Bin + Nlog2(RM) - log2(R)]

out

where Bin is the input data width. When the differential delay is one, the bit width at each integrator stage is increased by one to ensure

stability. For more information about these calculations, refer to Hogenauer, Eugene. An Economical Class of

Digital Filters For Decimation and Interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.

Output Rounding

For high rate change factors, the maximum required data width for no data loss is large for many practical cases. To reduce the output data width to the input level, apply quantization at the end of the output stage. the CIC filter offers various rounding or saturation options. You can only apply these rounding options to the output stage of the filter. The data widths at the intermediate stages are not changed.

Table 3-1: Output Rounding Options

Option Description

Trunca tion

Conver gent roundi ng

RoundupAlso known as rounding to plus infinity. Adds the MSB of the

SaturationPuts a limit value (upper limit in the case of overflow, or lower

The CIC drops the LSBs. (Equivalent to rounding to minus infinity.)

Also known as unbiased rounding. Rounds to the nearest even number. If the most significant deleted bit is one, and either the least significant of the remaining bits or at least one of the other deleted bits is one, then one is added to the remaining bits.

discarded bits for positive and negative numbers via the carry in.

limit in the case of negative overflow) at the output when the input exceeds the allowed range. The upper limit is +2n-1 and lower limit is –2n

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Decimation CIC

Filter

Compensation FIR

Filter

Compensation FIR

Filter

Interpolation CIC

Filter

Decimation

Interpolation

3-6

Hogenauer Pruning

Hogenauer pruning uses truncation in intermediate stages with the retained number of bits decreasing monotonically from stage to stage. The total error introduced is still no greater than the quantization error introduced by rounding the full precision output. This technique helps to reduce the number of logic cells used by the filter and gives better performance.

The existing algorithms for computing the Hogenauer bit width growth for large N and R values are computationally expensive.

For more information about these algorithms, refer to U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edition, Spinger, 2004.

The CIC IP core has precalculated Hogenauer pruning bit widths. The CIC does not have to calculate Hogenauer pruning bit widths if you enable Hogenauer pruning for a decimation filter.

Note: Hogenauer pruning is only available to decimation filters when the selected output data width is

smaller than the full output resolution data width.

FIR Filter Compensation Coefficients

CIC filters have a low-pass filter characteristic. Three parameters (the rate change factor R, the number of stages N, and the differential delay M) allow you to change the passband characteristics and aliasing or imaging rejection.

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Typically, decimation or interpolation filtering applications require flat passband and narrow transition region filter performance. However, the CIC filter has drooping passband gains and wide transition regions. To overcome these problems connect the decimation or interpolation CIC filter to a compensa‐ tion FIR filter, which narrows the output bandwidth and flattens the passband gain.

Figure 3-5: Using a CIC Compensation FIR Filter

You can use a frequency sampling method to determine the coefficients of a FIR filter that equalizes the undesirable passband droop of the CIC and construct an ideal frequency response.

Determine the ideal frequency response by sampling the normalized magnitude response of the CIC filter before inverting the response.

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CIC IP Core Parameters

Generally, only equalize the response in the passband, but you can sample further than the passband to fine tune the cascaded response of the filter chain.

The CIC IP core generates a MATLAB script <variation_name>_fir_comp_coeff.m in the project directory. You can run this script in MATLAB to generate FIR coefficients that provide appropriate passband equalization. The generated coefficients are saved in a text file, for use by the Altera FIR Compiler MegaCore function.

The MATLAB script requires the following parameters for the compensation FIR filter:

• L: FIR filter length, which is same as the number of taps or the number of coefficients

• FS: FIR filter sample rate in Hz before decimation/interpolation

• FC: FIR filter cutoff frequency in Hz

• B: Coefficient bit width if coefficients are written in fixed-point numbers

Figure 3-6: CIC and Compensation Filter Responses

3-7

Related Information

AN455: Understanding CIC Compensation Filters

CIC IP Core Parameters

Table 3-2: CIC IP Core Parameters

Parameter Value Description

Filter Specification Filter type Decimator,

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Selects a decimator or interpolator.

Interpolator

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CIC IP Core Parameters

Parameter Value Description

Number of stages 1 to 12 Specifies the required number of stages. Differential delay 1, 2 Specifies the differential delay in cycles.

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Enable variable rate change factor

On or Off Turn on to enable a variable rate change factor that

you can change at runtime. When this option is on, the Rate change factor parameter is not available but

you can specify minimum and maximum values. Rate change factor 2 to 32000 Specifies the rate change factor. Number of

interfaces

1 to 128 Specifies the number of MISO inputs or SIMO

outputs The product of the Number of interfaces

and the Number of channels per interface must be

no more than 1024. Number of

channels per interface

1 to 1024 Specifies the number of channels per interface. The

product of the Number of interfaces and the

Number of channels per interface must be no more

than 1024 Interface Specification Input data width 1 to 32 Specifies the input data width in bits. Output Rounding

Options

None, Truncation, Convergent rounding, Rounding up, Saturation, Hogenauer pruning

Selects the required rounding output mode. Select

None for full output resolution. The saturation limit

is the maximum value for overflow or the minimum

value for negative overflow. Hogenauer pruning is

available only when a Decimator filter type is selected

in the Architecture page. Output data width 1 to calculated

implementation Options Integrator data

storage

RAM type of integrator data storage

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maximum data width

Logic Element, Memory

AUTO, M9K, M10K, M20K, M144K, MLAB

Specifies the output data width in bits.

Selects whether to implement the integrator data

storage as logic elements or memory. The Memory

option is available for integrator data storage when

the Number of channels per interface is greater than

When you select Memory, you can select the RAM

type for integrator data storage. The Memory option

is available for integrator data storage when the

Number of channels per interface is greater than 4.

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CIC IP Core Interfaces and Signals

Parameter Value Description

3-9

Differentiator data storage

RAM type of differentiator data storage

Pipeline stages per integrator

Logic Element, Memory

Selects whether to implement the differentiator data

storage as logic elements or memory. The Memory

option is available for differentiator data storage

when the product of the Differential delay, Number

of channels per interface and Number of interfaces

is greater than 4.

AUTO, M9K, M10K, M20K, M144K, MLAB

When you select Memory, you can select the RAM

type for differentiator data storage. The options

available depend on the target device family. When

AUTO is selected, the Quartus II software automati‐

cally selects the optimum RAM type for the currently

selected device family.

— Enter the pipeline stages per integrator. This option is

available when the Number of channels per interface

is greater than or equal to 2 (or greater than or equal

to 6, when you select the Memory option for

integrator data storage).

Use this option for multichannel designs that have

large input bit width and require high f

MAX

, but not

for designs targeting Cyclone devices.

Pipeline stages per integrator

1 to 4 Specifies the number of pipeline stages used by each

integrator. Adding additional integrators can

improve f

The maximum number of pipeline stages depends on

the number of channels and whether you select

Memory or Logic Cells for integrator data storage.

For Memory, the maximum number of pipeline

stages equals the number of channels minus 5. For

Logic Cells, the maximum number of pipeline stages

equals the number of channels.

CIC IP Core Interfaces and Signals

Table 3-3: Avalon-ST Interface Parameters

All parameters not explicitly listed have undefined values.

Parameter Name Value

READY_LATENCY 0 BITS_PER_SYMBOL Data width

but increases the resource utilization.

MAX

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Avalon-ST Interfaces in DSP IP Cores

Parameter Name Value

SYMBOLS_PER_BEAT Single input, single output architectures, have one

symbol per beat at the source and the sink. MISO architectures have <number of interfaces> symbols per beat at the sink, and a single symbol per beat at the source. SIMO architectures have <number of interfaces> symbols per beat at the source, and a single symbol per beat at the sink.

SYMBOL_TYPE Signed

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ERROR_DESCRIPTION

• 00: No error

• 01: Missing startofpacket (SOP)

• 10: Missing endofpacket (EOP)

• 11: Unexpected EOP or any other error

Related Information

Avalon Interface Specifications

For more information about the Avalon-ST interface

Avalon-ST Interfaces in DSP IP Cores

Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface.

The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST interface supports packet transfers with packets interleaved across multiple channels.

Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchro‐ nizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.

Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output.

Related Information

• Avalon Interface Specifications

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CIC IP Core Signals

Table 3-4: CIC IP Core Signals

CIC IP Core Signals

3-11

Signal Directio

Description

av_st_in_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all

the Avalon-ST input data signals. For multi-interface designs Interface 0 is in the MSB; Interface N is the LSB.

clk Input Clock signal for all internal registers. clken Input Optional top-level clock enable. reset_n Input Active low reset signal. You must always reset the CIC MegaCore

function before receiving data. If not, the CIC filter may produce unexpected results because of feedback signals.

in_data Input Sample input. For multiple input cases, the input data ports are

in0_data, in1_data, and so on.

in_endofpacket Input Marks the end of the incoming sample group. For N channels, the

end of packet signal must be high when the sample belonging to the last channel, channel N-1, is presented at in_data.

in_error Input Error signal indicating Avalon-ST protocol violations on input

side:

• 00: No error

• 01: Missing start of packet

• 10: Missing end of packet

• 11: Unexpected end of packet

in_ready Output Indicates when the IP core can accept data.

in_startofpacket

in_valid Input Asserted when data at in_data is valid. When in_valid is not

av_st_out_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all

out_channel Output Specifies the channel whose result is presented at out_data. out_data Output Filter output. The data width depends on the parameter settings.

CIC IP Core Functional Description

Other types of error are also marked as 11.

Input Marks the start of the incoming sample group. The start of packet

is interpreted as a sample from channel 0.

asserted, processing is stopped until valid is re-asserted. If clken is 0, in_valid is not be asserted.

the Avalon-ST output data signals. For multi-interface designs Interface 0 is in the MSB; Interface N is the LSB.

For multiple output cases, the output data ports are named as

out0_data, out1_data, and so on.

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0 1 2 3

6 7 84

clk

ready

valid

error

data

00 00 00 00

3-12

Avalon-ST Interface Data Transfer Timing

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Signal Directio

Description

out_endofpacket Output Marks the end of the outgoing result group. If '1', a result

corresponding to channel N-1 is output, where N is the number of channels.

out_error Output Error signal indicating Avalon-ST protocol violations on source

side:

• 00: No error

• 01: Missing start of packet

• 10: Missing end of packet

• 11: Unexpected end of packet Other types of errors may also be marked as 11.

out_ready Input Asserted by the downstream module if it is able to accept data.

out_startofpacket

out_valid Output Asserted by the IP core when there is valid data to output. rate Input This signal is available when the variable rate change factor option

Output Marks the start of the outgoing result group. If '1', a result

corresponding to channel 0 is output.

is enabled. You can use it to change the decimation or interpola‐ tion rate during run time. It has the size Ceil(log2(maximum rate)) .

Avalon-ST Interface Data Transfer Timing

Figure 3-7: Avalon-ST Interface Timing with READY_LATENCY=0

The source provides data and asserts valid on cycle 1, even though the sink is not ready. The source waits until cycle 2, when the sink does assert ready, before moving onto the next data cycle. In cycle 3, the source drives data on the same cycle and because the sink is ready to receive it, the transfer occurs immediately. In cycle 4, the sink asserts ready, but the source does not drive valid data.

Packet Data Transfers

A beat is the transfer of one unit of data between a source and sink interface. This unit of data may consist of one or more symbols and makes it is possible to support modules that convey more than one piece of information about each valid cycle.

Packet data transfers are used for multichannel transfers. Two additional signals (startofpacket and

endofpacket) are defined to implement the packet transfer.

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CIC IP Core Functional Description

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0 1 2 3

00 00 00 00

1 2 3 4

6 7

clk

ready

valid

startofpacket

endofpacket

channel[1:0]

data[31:24] data[23:16]

data[15:8]

data[7:0]

error[1:0]

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Packet Data Transfers

3-13

The multiple symbols per beat scenario applies to both the sink interface on MISO CIC filters and the source interface of SIMO CIC filters. All other interfaces operate with a single symbol per beat, but the interfaces also support multiple channels using packets.

Figure 3-8: Packet Data TransferFour symbols are transferred on each beat. The data transfer occurs on cycles 1, 2, 4, and 5, when both ready and valid are asserted.

During cycle 1, the CIC IP core asserts startofpacket, and transfers the first four bytes of packet. During cycle 5, the CIC IP core asserts endofpacket indicating that this is the end of the packet. The channel signal indicates the channel index associated with the data. For example, on cycle 1, the data D0, D1, D2, and D3 associated with channel 0 are available.

CIC IP Core Functional Description

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Document Revision History

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CIC IP Core User Guide revision history.

Table 4-1:

Date Version Changes Made

2014.12.15 14.1

• Added final support for Arria 10 devices

• Reordered parameters tables to match wizard

August 2014

14.0 Arria 10 Edition

• Added support for Arria 10 devices.

• Added new av_st_in_data and av_st_out_data bus descriptions.

• Added Arria 10 generated files description.

• Removed table with generated file descriptions.

June 2014 14.0

• Removed support for Cyclone III and Stratix III devices

• Added instructions for using IP Catalog

November

13.1

• Removed support for the following devices:

2013

• Arria

• Cyclone II

• HardCopy II, HardCopy III, and HardCopy IV

• Stratix, Stratix II, Stratix GX, and Stratix II GX

• Added full support for the following devices:

November 2012

• Arria V

• Stratix V

12.1 Added support for Arria V GZ devices.

ISO 9001:2008 Registered

Altera CIC MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

About The CIC IP Core

Altera DSP IP Core Features

CIC IP Core Features

CIC IP Core Device Family Support

DSP IP Core Verification

CIC IP Core Release Information

CIC IP Core Performance and Resource Utilization

CIC IP Core Getting Started

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

CIC IP Core OpenCore Plus Timeout Behavior

IP Catalog and Parameter Editor

Specifying IP Core Parameters and Options

Files Generated for Altera IP Cores

Simulating Altera IP Cores in other EDA Tools

DSP Builder Design Flow

CIC IP Core Functional Description

Variable Rate Change Factors

Multichannel Support

Multiple Input Single Output (MISO)

Single Input Multiple Output (SIMO)

Output Options

Output Data Width

Output Rounding

Hogenauer Pruning

FIR Filter Compensation Coefficients

CIC IP Core Parameters

CIC IP Core Interfaces and Signals

Avalon-ST Interfaces in DSP IP Cores

CIC IP Core Signals

Avalon-ST Interface Data Transfer Timing

Packet Data Transfers

Document Revision History