Altera Arria V Reference Manual

Arria V Hard Processor System Technical

Reference Manual

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Last updated for Quartus Prime Design Suite: 20.1

av_5v4

2020.09.03

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Arria® V Hard Processor System Technical Reference Manual Revision

History............................................................................................................. 1-1

Introduction to the Hard Processor System....................................................... 2-1

Features of the HPS......................................................................................................................................2-3

HPS Block Diagram and System Integration........................................................................................... 2-4

HPS Block Diagram.........................................................................................................................2-4

Cortex-A9 MPCore..........................................................................................................................2-5

HPS Interfaces.................................................................................................................................. 2-5

System Interconnect.........................................................................................................................2-6

On-Chip Memory............................................................................................................................ 2-7

Flash Memory Controllers..............................................................................................................2-8

Support Peripherals..........................................................................................................................2-9

Interface Peripherals......................................................................................................................2-11

CoreSight Debug and Trace..........................................................................................................2-14

Endian Support.......................................................................................................................................... 2-14

Introduction to the Hard Processor System Address Map...................................................................2-15

HPS Address Spaces.......................................................................................................................2-15

HPS Peripheral Region Address Map..........................................................................................2-17

Clock Manager.....................................................................................................3-1

Features of the Clock Manager...................................................................................................................3-1

Clock Manager Block Diagram and System Integration........................................................................ 3-2

L4 Peripheral Clocks........................................................................................................................3-3

Functional Description of the Clock Manager.........................................................................................3-5

Clock Manager Building Blocks.....................................................................................................3-5

Hardware-Managed and Soware-Managed Clocks...................................................................3-7

Clock Groups....................................................................................................................................3-7

Resets............................................................................................................................................... 3-17

Safe Mode........................................................................................................................................3-17

Interrupts.........................................................................................................................................3-18

Clock Usage By Module................................................................................................................ 3-18

Clock Manager Address Map and Register Denitions........................................................................3-23

Reset Manager..................................................................................................... 4-1

Reset Manager Block Diagram and System Integration.........................................................................4-2

HPS External Reset Sources............................................................................................................4-3

Reset Controller................................................................................................................................4-4

Module Reset Signals.......................................................................................................................4-5

Slave Interface and Status Register.............................................................................................. 4-10

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Functional Description of the Reset Manager....................................................................................... 4-10

Reset Sequencing............................................................................................................................4-11

Reset Pins........................................................................................................................................ 4-15

Reset Eects.................................................................................................................................... 4-15

Altering Warm Reset System Response...................................................................................... 4-15

Reset Handshaking........................................................................................................................ 4-16

Reset Manager Address Map and Register Denitions.........................................................................4-16

FPGA Manager.................................................................................................... 5-1

Features of the FPGA Manager..................................................................................................................5-1

FPGA Manager Block Diagram and System Integration........................................................................5-2

Functional Description of the FPGA Manager........................................................................................5-3

FPGA Manager Building Blocks....................................................................................................5-3

FPGA Conguration....................................................................................................................... 5-4

FPGA Status......................................................................................................................................5-8

Error Message Extraction................................................................................................................5-8

Boot Handshake...............................................................................................................................5-8

General Purpose I/O........................................................................................................................5-9

Clock..................................................................................................................................................5-9

Reset...................................................................................................................................................5-9

FPGA Manager Address Map and Register Denitions.........................................................................5-9

System Manager...................................................................................................6-1

Features of the System Manager.................................................................................................................6-1

System Manager Block Diagram and System Integration......................................................................6-2

Functional Description of the System Manager.......................................................................................6-3

Boot Conguration and System Information.............................................................................. 6-3

Additional Module Control............................................................................................................6-3

Boot ROM Code...............................................................................................................................6-6

FPGA Interface Enables.................................................................................................................. 6-7

ECC and Parity Control..................................................................................................................6-8

Preloader Hando Information..................................................................................................... 6-8

Clocks................................................................................................................................................ 6-8

Resets................................................................................................................................................. 6-8

System Manager Address Map and Register Denitions........................................................................6-9

Scan Manager.......................................................................................................7-1

Features of the Scan Manager.....................................................................................................................7-1

Scan Manager Block Diagram and System Integration.......................................................................... 7-2

Arm JTAG-AP Signal Use in the Scan Manager..........................................................................7-2

Arm JTAG-AP Scan Chains............................................................................................................7-3

Functional Description of the Scan Manager...........................................................................................7-5

Conguring HPS I/O Scan Chains................................................................................................7-5

Communicating with the JTAG TAP Controller.........................................................................7-6

JTAG-AP FIFO Buer Access and Byte Command Protocol.................................................... 7-6

Clocks................................................................................................................................................ 7-7

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Resets................................................................................................................................................. 7-8

Scan Manager Address Map and Register Denitions............................................................................7-8

JTAG-AP Register Name Cross Reference Table......................................................................... 7-8

System Interconnect............................................................................................ 8-1

Features of the System Interconnect..........................................................................................................8-1

System Interconnect Block Diagram and System Integration............................................................... 8-2

Interconnect Block Diagram.......................................................................................................... 8-2

System Interconnect Architecture..................................................................................................8-2

Main Connectivity Matrix.............................................................................................................. 8-3

Functional Description of the Interconnect.............................................................................................8-4

Master to Slave Connectivity Matrix.............................................................................................8-4

System Interconnect Address Spaces.............................................................................................8-5

Master Caching and Buering Overrides...................................................................................8-13

Security............................................................................................................................................8-13

Conguring the Quality of Service Logic................................................................................... 8-14

Cyclic Dependency Avoidance Schemes.....................................................................................8-14

System Interconnect Master Properties...................................................................................... 8-15

Interconnect Slave Properties.......................................................................................................8-17

Upsizing Data Width Function....................................................................................................8-19

Downsizing Data Width Function...............................................................................................8-20

Lock Support...................................................................................................................................8-21

FIFO Buers and Clock Crossing................................................................................................8-21

System Interconnect Resets.......................................................................................................... 8-22

System Interconnect Address Map and Register Denitions...............................................................8-22

HPS-FPGA Bridges............................................................................................. 9-1

Features of the HPS-FPGA Bridges...........................................................................................................9-1

HPS-FPGA Bridges Block Diagram and System Integration.................................................................9-3

Functional Description of the HPS-FPGA Bridges.................................................................................9-4

e Global Programmers View......................................................................................................9-4

Functional Description of the FPGA-to-HPS Bridge..................................................................9-4

Functional Description of the HPS-to-FPGA Bridge..................................................................9-7

Functional Description of the Lightweight HPS-to-FPGA Bridge..........................................9-10

Clocks and Resets...........................................................................................................................9-14

Data Width Sizing..........................................................................................................................9-15

HPS-FPGA Bridges Address Map and Register Denitions................................................................9-16

Cortex-A9 Microprocessor Unit Subsystem..................................................... 10-1

Features of the Cortex-A9 MPU Subsystem...........................................................................................10-1

Cortex-A9 MPU Subsystem Block Diagram and System Integration................................................10-2

Cortex-A9 MPU Subsystem with System Interconnect............................................................10-2

Cortex-A9 MPU Subsystem Internals.........................................................................................10-3

Cortex-A9 MPCore....................................................................................................................................10-4

Functional Description..................................................................................................................10-4

Implementation Details.................................................................................................................10-5

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Cortex-A9 Processor..................................................................................................................... 10-6

Interactive Debugging Features....................................................................................................10-7

L1 Caches........................................................................................................................................ 10-7

Preload Engine............................................................................................................................... 10-7

Floating Point Unit.........................................................................................................................10-8

NEON Multimedia Processing Engine....................................................................................... 10-8

Memory Management Unit..........................................................................................................10-9

Performance Monitoring Unit....................................................................................................10-12

Arm Cortex-A9 MPCore Timers...............................................................................................10-12

Generic Interrupt Controller......................................................................................................10-13

Global Timer.................................................................................................................................10-24

Snoop Control Unit..................................................................................................................... 10-25

Accelerator Coherency Port....................................................................................................... 10-27

ACP ID Mapper.......................................................................................................................................10-31

Functional Description............................................................................................................... 10-32

Implementation Details...............................................................................................................10-32

ACP ID Mapper Address Map and Register Denitions........................................................10-38

L2 Cache....................................................................................................................................................10-38

Functional Description............................................................................................................... 10-38

CPU Prefetch............................................................................................................................................10-45

Debugging Modules.................................................................................................................................10-45

Program Trace..............................................................................................................................10-45

Event Trace....................................................................................................................................10-46

Cross-Triggering.......................................................................................................................... 10-47

Clocks........................................................................................................................................................ 10-47

Cortex-A9 MPU Subsystem Register Implementation.......................................................................10-47

Cortex-A9 MPU Subsystem Address Map...............................................................................10-48

L2 Cache Controller Address Map............................................................................................ 10-49

CoreSight Debug and Trace...............................................................................11-1

Features of CoreSight Debug and Trace..................................................................................................11-2

Arm CoreSight Documentation...............................................................................................................11-2

CoreSight Debug and Trace Block Diagram and System Integration.................................................11-3

Functional Description of CoreSight Debug and Trace........................................................................11-4

Debug Access Port......................................................................................................................... 11-4

System Trace Macrocell.................................................................................................................11-4

Trace Funnel................................................................................................................................... 11-5

CoreSight Trace Memory Controller...........................................................................................11-5

AMBA Trace Bus Replicator.........................................................................................................11-6

Trace Port Interface Unit...............................................................................................................11-6

Embedded Cross Trigger System.................................................................................................11-6

Program Trace Macrocell............................................................................................................11-11

HPS Debug APB Interface..........................................................................................................11-11

FPGA Interface.............................................................................................................................11-11

Debug Clocks................................................................................................................................11-14

Debug Resets................................................................................................................................ 11-15

CoreSight Debug and Trace Programming Model..............................................................................11-16

Coresight Component Address..................................................................................................11-17

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STM Channels..............................................................................................................................11-18

CTI Trigger Connections to Outside the Debug System........................................................11-19

Conguring Embedded Cross-Trigger Connections..............................................................11-21

CoreSight Debug and Trace Address Map and Register Denitions................................................11-22

SDRAM Controller Subsystem..........................................................................12-1

Features of the SDRAM Controller Subsystem......................................................................................12-1

SDRAM Controller Subsystem Block Diagram.....................................................................................12-2

SDRAM Controller Memory Options.....................................................................................................12-3

SDRAM Controller Subsystem Interfaces.............................................................................................. 12-4

MPU Subsystem Interface.............................................................................................................12-4

L3 Interconnect Interface..............................................................................................................12-4

CSR Interface..................................................................................................................................12-5

FPGA-to-HPS SDRAM Interface.................................................................................................12-5

Memory Controller Architecture.............................................................................................................12-6

Multi-Port Front End.....................................................................................................................12-7

Single-Port Controller................................................................................................................... 12-8

Functional Description of the SDRAM Controller Subsystem..........................................................12-10

MPFE Operation Ordering.........................................................................................................12-10

MPFE Multi-Port Arbitration....................................................................................................12-10

MPFE SDRAM Burst Scheduling..............................................................................................12-13

Single-Port Controller Operation..............................................................................................12-14

SDRAM Power Management.................................................................................................................12-24

DDR PHY................................................................................................................................................. 12-25

DDR Calibration..........................................................................................................................12-25

Clocks........................................................................................................................................................ 12-25

Resets......................................................................................................................................................... 12-26

Taking the SDRAM Controller Subsystem Out of Reset .......................................................12-26

Port Mappings..........................................................................................................................................12-26

Initialization..............................................................................................................................................12-27

FPGA-to-SDRAM Protocol Details...........................................................................................12-28

SDRAM Controller Subsystem Programming Model........................................................................ 12-32

HPS Memory Interface Architecture.........................................................................................12-32

HPS Memory Interface Conguration......................................................................................12-32

HPS Memory Interface Simulation........................................................................................... 12-33

Generating a Preloader Image for HPS with EMIF.................................................................12-34

Debugging HPS SDRAM in the Preloader...........................................................................................12-35

Enabling UART or Semihosting Printout.................................................................................12-35

Enabling Simple Memory Test...................................................................................................12-36

Enabling the Debug Report........................................................................................................12-37

Writing a Predened Data Pattern to SDRAM in the Preloader...........................................12-40

SDRAM Controller Address Map and Register Denitions.............................................................. 12-41

On-Chip Memory.............................................................................................. 13-1

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On-Chip RAM............................................................................................................................................13-1

Features of the On-Chip RAM.....................................................................................................13-1

On-Chip RAM Block Diagram and System Integration...........................................................13-1

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Functional Description of the On-Chip RAM...........................................................................13-2

Boot ROM...................................................................................................................................................13-3

Features of the Boot ROM............................................................................................................13-3

Boot ROM Block Diagram and System Integration..................................................................13-3

Functional Description of the Boot ROM..................................................................................13-3

On-Chip Memory Address Map and Register Denitions.................................................................. 13-4

NAND Flash Controller.................................................................................... 14-1

NAND Flash Controller Features............................................................................................................ 14-1

NAND Flash Controller Block Diagram and System Integration.......................................................14-2

NAND Flash Controller Signal Descriptions.........................................................................................14-2

Functional Description of the NAND Flash Controller.......................................................................14-3

Discovery and Initialization......................................................................................................... 14-3

Bootstrap Interface.........................................................................................................................14-4

Conguration by Host...................................................................................................................14-5

Local Memory Buer.....................................................................................................................14-6

Clocks.............................................................................................................................................. 14-6

Resets............................................................................................................................................... 14-7

Indexed Addressing....................................................................................................................... 14-7

Command Mapping...................................................................................................................... 14-8

Data DMA.....................................................................................................................................14-14

ECC................................................................................................................................................14-18

NAND Flash Controller Programming Model....................................................................................14-21

Basic Flash Programming...........................................................................................................14-22

Flash-Related Special Function Operations.............................................................................14-25

NAND Flash Controller Address Map and Register Denitions......................................................14-33

SD/MMC Controller..........................................................................................15-1

Features of the SD/MMC Controller.......................................................................................................15-1

SD Card Support Matrix............................................................................................................... 15-2

MMC Support Matrix....................................................................................................................15-3

SD/MMC Controller Block Diagram and System Integration............................................................ 15-3

SD/MMC Controller Signal Description................................................................................................15-4

Functional Description of the SD/MMC Controller.............................................................................15-5

SD/MMC/CE-ATA Protocol........................................................................................................ 15-5

BIU...................................................................................................................................................15-6

CIU.................................................................................................................................................15-20

Clocks............................................................................................................................................ 15-35

Resets............................................................................................................................................. 15-36

Voltage Switching.........................................................................................................................15-37

SD/MMC Controller Programming Model......................................................................................... 15-39

Soware and Hardware Restrictions†....................................................................................... 15-39

Initialization†................................................................................................................................15-41

Controller/DMA/FIFO Buer Reset Usage..............................................................................15-47

Enabling ECC...............................................................................................................................15-47

Enabling FIFO Buer ECC.........................................................................................................15-47

Non-Data Transfer Commands................................................................................................. 15-48

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Data Transfer Commands...........................................................................................................15-50

Transfer Stop and Abort Commands........................................................................................15-56

Internal DMA Controller Operations.......................................................................................15-58

Commands for SDIO Card Devices.......................................................................................... 15-60

CE-ATA Data Transfer Commands.......................................................................................... 15-62

Card Read reshold...................................................................................................................15-70

Interrupt and Error Handling.................................................................................................... 15-73

Booting Operation for eMMC and MMC................................................................................15-74

SD/MMC Controller Address Map and Register Denitions............................................................15-84

Quad SPI Flash Controller................................................................................ 16-1

Features of the Quad SPI Flash Controller.............................................................................................16-1

Quad SPI Flash Controller Block Diagram and System Integration...................................................16-2

Interface Signals......................................................................................................................................... 16-3

Functional Description of the Quad SPI Flash Controller...................................................................16-3

Overview......................................................................................................................................... 16-3

Data Slave Interface....................................................................................................................... 16-4

SPI Legacy Mode............................................................................................................................16-7

Register Slave Interface..................................................................................................................16-8

Local Memory Buer.....................................................................................................................16-8

DMA Peripheral Request Controller...........................................................................................16-9

Arbitration between Direct/Indirect Access Controller and STIG.......................................16-10

Conguring the Flash Device.....................................................................................................16-10

XIP Mode......................................................................................................................................16-12

Write Protection...........................................................................................................................16-12

Data Slave Sequential Access Detection................................................................................... 16-13

Clocks............................................................................................................................................ 16-13

Resets............................................................................................................................................. 16-13

Interrupts...................................................................................................................................... 16-14

Quad SPI Flash Controller Programming Model................................................................................16-15

Setting Up the Quad SPI Flash Controller................................................................................16-16

Indirect Read Operation with DMA Disabled.........................................................................16-16

Indirect Read Operation with DMA Enabled..........................................................................16-17

Indirect Write Operation with DMA Disabled........................................................................16-17

Indirect Write Operation with DMA Enabled.........................................................................16-18

XIP Mode Operations................................................................................................................. 16-18

Quad SPI Flash Controller Address Map and Register Denitions..................................................16-20

DMA Controller................................................................................................ 17-1

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Features of the DMA Controller..............................................................................................................17-1

DMA Controller Block Diagram and System Integration....................................................................17-3

Functional Description of the DMA Controller....................................................................................17-3

Peripheral Request Interface.........................................................................................................17-4

DMA Controller Address Map and Register Denitions.....................................................................17-7

Address Map and Register Denitions........................................................................................17-9

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Ethernet Media Access Controller.................................................................... 18-1

Features of the Ethernet MAC..................................................................................................................18-2

MAC.................................................................................................................................................18-2

DMA................................................................................................................................................18-2

Management Interface...................................................................................................................18-3

Acceleration....................................................................................................................................18-3

PHY Interface.................................................................................................................................18-3

EMAC Block Diagram and System Integration.....................................................................................18-4

EMAC Signal Description.........................................................................................................................18-5

HPS EMAC I/O Signals.................................................................................................................18-6

FPGA EMAC I/O Signals..............................................................................................................18-8

PHY Management Interface.......................................................................................................18-11

EMAC Internal Interfaces.......................................................................................................................18-12

DMA Master Interface................................................................................................................ 18-12

Timestamp Interface....................................................................................................................18-13

Functional Description of the EMAC................................................................................................... 18-14

Transmit and Receive Data FIFO Buers.................................................................................18-15

DMA Controller...........................................................................................................................18-16

Descriptor Overview................................................................................................................... 18-29

IEEE 1588-2002 Timestamps.....................................................................................................18-46

IEEE 1588-2008 Advanced Timestamps...................................................................................18-52

IEEE 802.3az Energy Ecient Ethernet....................................................................................18-55

Checksum Ooad....................................................................................................................... 18-56

Frame Filtering.............................................................................................................................18-56

Clocks and Resets.........................................................................................................................18-61

Interrupts...................................................................................................................................... 18-63

Ethernet MAC Programming Model.................................................................................................... 18-63

System Level EMAC Conguration Registers..........................................................................18-63

EMAC FPGA Interface Initialization........................................................................................18-65

EMAC HPS Interface Initialization...........................................................................................18-66

DMA Initialization.......................................................................................................................18-66

EMAC Initialization and Conguration...................................................................................18-67

Performing Normal Receive and Transmit Operation........................................................... 18-68

Stopping and Starting Transmission......................................................................................... 18-69

Programming Guidelines for Energy Ecient Ethernet........................................................ 18-69

Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output..............................18-70

Ethernet MAC Address Map and Register Denitions.......................................................................18-72

USB 2.0 OTG Controller................................................................................... 19-1

Features of the USB OTG Controller...................................................................................................... 19-2

Supported PHYS.............................................................................................................................19-3

USB OTG Controller Block Diagram and System Integration............................................................19-4

USB 2.0 ULPI PHY Signal Description...................................................................................................19-5

Functional Description of the USB OTG Controller............................................................................19-6

USB OTG Controller Block Description.................................................................................... 19-6

Local Memory Buer...................................................................................................................19-10

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Clocks............................................................................................................................................ 19-10

Resets............................................................................................................................................. 19-10

Interrupts...................................................................................................................................... 19-11

USB OTG Controller Programming Model.........................................................................................19-13

Enabling ECC...............................................................................................................................19-13

Enabling SPRAM ECCs.............................................................................................................. 19-13

Host Operation.............................................................................................................................19-14

Device Operation.........................................................................................................................19-15

USB 2.0 OTG Controller Address Map and Register Denitions.....................................................19-17

USB Data FIFO Address Map.................................................................................................... 19-17

USB Direct Access FIFO RAM Address Map..........................................................................19-19

SPI Controller....................................................................................................20-1

Features of the SPI Controller..................................................................................................................20-1

SPI Block Diagram and System Integration...........................................................................................20-2

SPI Block Diagram.........................................................................................................................20-2

SPI Controller Signal Description........................................................................................................... 20-3

Interface to HPS I/O......................................................................................................................20-3

FPGA Routing................................................................................................................................20-3

Functional Description of the SPI Controller........................................................................................20-4

Protocol Details and Standards Compliance..............................................................................20-4

SPI Controller Overview...............................................................................................................20-5

Transfer Modes...............................................................................................................................20-8

SPI Master.......................................................................................................................................20-9

SPI Slave........................................................................................................................................ 20-12

Partner Connection Interfaces...................................................................................................20-16

DMA Controller Interface.......................................................................................................... 20-21

Slave Interface...............................................................................................................................20-21

Clocks and Resets.........................................................................................................................20-22

SPI Programming Model........................................................................................................................ 20-23

Master SPI and SSP Serial Transfers..........................................................................................20-24

Master Microwire Serial Transfers.............................................................................................20-26

Slave SPI and SSP Serial Transfers............................................................................................. 20-28

Slave Microwire Serial Transfers................................................................................................20-29

Soware Control for Slave Selection......................................................................................... 20-29

DMA Controller Operation........................................................................................................20-30

SPI Controller Address Map and Register Denitions.......................................................................20-33

I2C Controller....................................................................................................21-1

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Features of the I2C Controller..................................................................................................................21-1

I2C Controller Block Diagram and System Integration........................................................................21-2

I2C Controller Signal Description........................................................................................................... 21-3

Functional Description of the I2C Controller........................................................................................21-4

Feature Usage..................................................................................................................................21-4

Behavior...........................................................................................................................................21-5

Protocol Details..............................................................................................................................21-6

Multiple Master Arbitration.......................................................................................................21-11

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Clock Frequency Conguration................................................................................................ 21-13

SDA Hold Time............................................................................................................................21-15

DMA Controller Interface.......................................................................................................... 21-15

Clocks............................................................................................................................................ 21-15

Resets............................................................................................................................................. 21-15

I2C Controller Programming Model.....................................................................................................21-16

Slave Mode Operation.................................................................................................................21-16

Master Mode Operation..............................................................................................................21-19

Disabling the I2C Controller...................................................................................................... 21-20

DMA Controller Operation........................................................................................................21-20

I2C Controller Address Map and Register Denitions.......................................................................21-24

UART Controller............................................................................................... 22-1

UART Controller Features........................................................................................................................22-1

UART Controller Block Diagram and System Integration...................................................................22-2

UART Controller Signal Description...................................................................................................... 22-3

HPS I/O Pins...................................................................................................................................22-3

FPGA Routing................................................................................................................................22-3

Functional Description of the UART Controller...................................................................................22-4

FIFO Buer Support......................................................................................................................22-4

UART(RS232) Serial Protocol......................................................................................................22-5

Automatic Flow Control............................................................................................................... 22-5

Clocks.............................................................................................................................................. 22-7

Resets............................................................................................................................................... 22-7

Interrupts.........................................................................................................................................22-7

DMA Controller Operation....................................................................................................................22-10

Transmit FIFO Underow..........................................................................................................22-11

Transmit Watermark Level......................................................................................................... 22-11

Transmit FIFO Overow............................................................................................................ 22-12

Receive FIFO Overow...............................................................................................................22-13

Receive Watermark Level............................................................................................................22-13

Receive FIFO Underow.............................................................................................................22-13

UART Controller Address Map and Register Denitions..................................................................22-14

General-Purpose I/O Interface......................................................................... 23-1

Features of the GPIO Interface.................................................................................................................23-1

GPIO Interface Block Diagram and System Integration......................................................................23-2

Functional Description of the GPIO Interface.......................................................................................23-2

Debounce Operation..................................................................................................................... 23-2

Pin Directions.................................................................................................................................23-3

Taking the GPIO Interface Out of Reset ....................................................................................23-3

GPIO Pin State During Reset....................................................................................................... 23-3

GPIO Interface Programming Model..................................................................................................... 23-4

General-Purpose I/O Interface Address Map and Register Denitions.............................................23-4

Timer .................................................................................................................24-1

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Features of the Timer.................................................................................................................................24-1

Timer Block Diagram and System Integration...................................................................................... 24-1

Functional Description of the Timer.......................................................................................................24-2

Clocks.............................................................................................................................................. 24-3

Resets............................................................................................................................................... 24-3

Interrupts.........................................................................................................................................24-3

FPGA Interface...............................................................................................................................24-3

Timer Programming Model..................................................................................................................... 24-5

Initialization....................................................................................................................................24-5

Enabling the Timer........................................................................................................................24-5

Disabling the Timer.......................................................................................................................24-5

Loading the Timer Countdown Value.........................................................................................24-5

Servicing Interrupts.......................................................................................................................24-6

Timer Address Map and Register Denitions........................................................................................24-6

Watchdog Timer................................................................................................ 25-1

Features of the Watchdog Timer..............................................................................................................25-1

Watchdog Timer Block Diagram and System Integration................................................................... 25-2

Functional Description of the Watchdog Timer....................................................................................25-2

Watchdog Timer Counter.............................................................................................................25-2

Watchdog Timer Pause Mode......................................................................................................25-3

Watchdog Timer Clocks................................................................................................................25-3

Watchdog Timer Resets.................................................................................................................25-3

FPGA Interface...............................................................................................................................25-4

Watchdog Timer Programming Model...................................................................................................25-4

Setting the Timeout Period Values.............................................................................................. 25-4

Selecting the Output Response Mode......................................................................................... 25-4

Enabling and Initially Starting a Watchdog Timer....................................................................25-5

Reloading a Watchdog Counter...................................................................................................25-5

Pausing a Watchdog Timer...........................................................................................................25-5

Disabling and Stopping a Watchdog Timer................................................................................25-5

Watchdog Timer State Machine...................................................................................................25-5

Watchdog Timer Address Map and Register Denitions.....................................................................25-7

Introduction to the HPS Component............................................................... 26-1

Instantiating the HPS Component................................................................... 27-1

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MPU Subsystem.........................................................................................................................................26-2

Arm CoreSight Debug Components.......................................................................................................26-2

Interconnect................................................................................................................................................26-2

HPS-to-FPGA Interfaces...........................................................................................................................26-2

Memory Controllers..................................................................................................................................26-3

Support Peripherals....................................................................................................................................26-3

Interface Peripherals..................................................................................................................................26-3

On-Chip Memories....................................................................................................................................26-4

FPGA Interfaces.........................................................................................................................................27-1

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General Interfaces..........................................................................................................................27-2

FPGA-to-HPS SDRAM Interface.................................................................................................27-3

DMA Peripheral Request.............................................................................................................. 27-5

Interrupts.........................................................................................................................................27-5

AXI Bridges.....................................................................................................................................27-7

Conguring HPS Clocks and Resets....................................................................................................... 27-8

User Clocks.....................................................................................................................................27-8

Reset Interfaces...............................................................................................................................27-9

PLL Reference Clocks..................................................................................................................27-10

Peripheral FPGA Clocks.............................................................................................................27-11

Conguring Peripheral Pin Multiplexing.............................................................................................27-11

Conguring Peripherals..............................................................................................................27-12

Connecting Unassigned Pins to GPIO......................................................................................27-12

Using Unassigned IO as LoanIO................................................................................................27-13

Resolving Pin Multiplexing Conicts........................................................................................27-13

Peripheral Signals Routed to FPGA ..........................................................................................27-14

Conguring the External Memory Interface........................................................................................27-14

Selecting PLL Output Frequency and Phase............................................................................ 27-15

Using the Address Span Extender Component....................................................................................27-15

Generating and Compiling the HPS Component............................................................................... 27-16

HPS Component Interfaces...............................................................................28-1

Memory-Mapped Interfaces.....................................................................................................................28-1

FPGA-to-HPS Bridge....................................................................................................................28-1

HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges...........................................................28-2

FPGA-to-HPS SDRAM Interface.................................................................................................28-3

Clocks.......................................................................................................................................................... 28-4

Alternative Clock Inputs to HPS PLLs........................................................................................28-4

User Clocks.....................................................................................................................................28-4

AXI Bridge FPGA Interface Clocks.............................................................................................28-5

SDRAM Clocks.............................................................................................................................. 28-5

Peripheral FPGA Clocks............................................................................................................... 28-5

Resets........................................................................................................................................................... 28-6

HPS-to-FPGA Reset Interfaces....................................................................................................28-6

HPS External Reset Request......................................................................................................... 28-6

Peripheral Reset Interfaces............................................................................................................28-7

Debug and Trace Interfaces...................................................................................................................... 28-7

Trace Port Interface Unit...............................................................................................................28-7

FPGA System Trace Macrocell Events Interface........................................................................28-7

FPGA Cross Trigger Interface...................................................................................................... 28-7

Debug APB Interface.....................................................................................................................28-7

Peripheral Signal Interfaces...................................................................................................................... 28-7

DMA Controller Interface............................................................................................................ 28-7

Other Interfaces..........................................................................................................................................28-8

MPU Standby and Event Interfaces.............................................................................................28-8

General Purpose Signals............................................................................................................... 28-9

FPGA-to-HPS Interrupts..............................................................................................................28-9

Boot from FPGA Interface............................................................................................................28-9

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TOC-14

Input-only General Purpose Interface........................................................................................ 28-9

Simulating the HPS Component.......................................................................29-1

Simulation Flows........................................................................................................................................29-2

Setting Up the HPS Component for Simulation........................................................................29-3

Generating the HPS Simulation Model in Platform Designer (Standard).............................29-5

Running the Simulations...............................................................................................................29-5

Clock and Reset Interfaces........................................................................................................................29-9

Clock Interface............................................................................................................................... 29-9

Reset Interface..............................................................................................................................29-10

FPGA-to-HPS AXI Slave Interface........................................................................................................29-11

HPS-to-FPGA AXI Master Interface.....................................................................................................29-12

Lightweight HPS-to-FPGA AXI Master Interface...............................................................................29-12

FPGA-to-HPS SDRAM Interface.......................................................................................................... 29-13

HPS Memory Interface Simulation........................................................................................... 29-13

HPS-to-FPGA MPU Event Interface.....................................................................................................29-14

Interrupts Interface..................................................................................................................................29-14

HPS-to-FPGA Debug APB Interface.................................................................................................... 29-16

FPGA-to-HPS System Trace Macrocell Hardware Event Interface...................................................29-16

HPS-to-FPGA Cross-Trigger Interface.................................................................................................29-17

HPS-to-FPGA Trace Port Interface.......................................................................................................29-17

FPGA-to-HPS DMA Handshake Interface...........................................................................................29-18

Boot from FPGA Interface......................................................................................................................29-19

General Purpose Input Interface............................................................................................................29-20

Booting and Conguration................................................................................ A-1

Boot Overview.............................................................................................................................................A-1

FPGA Conguration Overview.................................................................................................................A-1

Booting and Conguration Options.........................................................................................................A-2

Boot Denitions.......................................................................................................................................... A-5

Reset.................................................................................................................................................. A-5

Boot ROM........................................................................................................................................ A-5

Boot Select........................................................................................................................................ A-6

Flash Memory Devices for Booting............................................................................................ A-13

Clock Select.................................................................................................................................... A-25

I/O Conguration......................................................................................................................... A-25

L4 Watchdog 0 Timer................................................................................................................... A-26

Preloader.........................................................................................................................................A-26

U-Boot Loader...............................................................................................................................A-26

Boot ROM Flow.........................................................................................................................................A-26

Typical Preloader Boot Flow....................................................................................................................A-28

HPS State on Entry to the Preloader...........................................................................................A-31

Shared Memory............................................................................................................................. A-31

Loading the Preloader Image.......................................................................................................A-32

FPGA Conguration.................................................................................................................................A-33

Full Conguration.........................................................................................................................A-33

Partial Reconguration.................................................................................................................A-34

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Reference Manual Revision History

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Chapter Date of Last Update

Introduction to the Hard Processor System

Clock Manager November 2, 2015 Reset Manager November 2, 2015 FPGA Manager June 14, 2019 System Manager July 17, 2018 Scan Manager May 3, 2016 System Interconnect May 4, 2015 HPS-FPGA Bridges September 3, 2020

Cortex®-A9 Microprocessor Unit Subsystem

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September 3, 2020

CoreSight* Debug and Trace July 31, 2014

SDRAM Controller Subsystem

February 28, 2020

Controller On-Chip Memory January 26, 2018 NAND Flash Controller January 26, 2018 SD/MMC Controller January 26, 2018 Quad SPI Flash Controller September 3, 2020 DMA Controller January 26, 2018 Ethernet Media Access Controller June 14, 2019 USB 2.0 OTG Controller January 26, 2018 SPI Controller January 26, 2018

I2C Controller May 4, 2015 UART Controller November 2, 2015

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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General-Purpose I/O Interface September 3, 2020 Timer June 30, 2014 Watchdog Timer November 2, 2015 Introduction to the HPS Component December 30, 2013 Instantiating the HPS Component November 2, 2015 HPS Component Interfaces May 4, 2015 Simulating the HPS Component May 3, 2016 Booting and Conguration September 3, 2020

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2016.10.28

2016.05.03

• Added 8-bit support for eMMC for SD/MMC

• Renamed MPU Subsystem to Cortex-A9 MPCore

Maintenance release.

Changes

2015.11.02 Updated the link to the Memory Maps.

2015.05.04 Corrected the base address for NANDDATA in the "Peripheral Region Address Map" table.

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30 Maintenance release

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.3 Minor updates.

1.2 Updated address spaces section.

1.1 Added peripheral region address map.

1.0 Initial release.

Introduction to the Hard Processor System on page 2-1

Document

Version

2020.01.13 Correct typical sdmmc_clk frequencies in Flash Controller Clocks

2015.11.02 Minor formatting updates.

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2015.05.04 Minor formatting updates.

2014.12.15

FREF, FVCO, and FOUT Equations section updated. More information added about vco register, M and N equations.

Reference Clock information added to Clock Groups section.

2014.06.30

E0SC1 changed to HPS_CLK1 E0SC2 changed to HPS_CLK2 Added Address Map and Register Descriptions

2014.02.28

2013.12.30

Updated content in the "Peripheral Clock Group" section

Minor formatting updates.

1.2 Minor updates.

1.1 • Reorganized and expanded functional description section.

• Added address map and register denitions section.

1.0 Initial release.

Clock Manager on page 3-1

Document

Version

2015.11.02 Updated "Reset Pins" section

2015.05.04 Updated:

• MISC Group, Generated Module Resets table

• "Reset Pins" section

2014.12.15

• Signal power information added to "HPS External Reset Sources" section

• Updated block diagram with h2f_dbg_rst_n signal

2014.06.30

• Updated "Functional Description of Reset Manager"

• Added address map and register descriptions

2014.02.28

Updated sections:

• Reset Sequencing

• Warm Reset Assertion Sequence

Changes

2013.12.30

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1.2 • Added cold and warm reset timing diagrams.

1.1 Added reset controller, functional description, and address map and register denitions sections.

1.0 Initial release.

Reset Manager on page 4-1

Document

Version

Changes

2019.06.14 Corrected the msel descriptions for encodings 0x0 through 0x2 and 0x4 to 0x6 in the stat register.

2015.11.02 Provided more information for the conguration schemes for the dedicated pins.

2015.05.04 Added information about FPPx32.

2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Minor updates.

1.3 Minor updates.

1.2 Updated the FPGA conguration section.

1.1 • Updated the conguration schemes table.

• Updated the FPGA conguration section.

• Added address map and register denitions section.

1.0 Initial release.

FPGA Manager

Document

Version

on page 5-1

Changes

2018.11.03 Modied mode register biteld descriptions for clarity.

2018.07.17 Made the following changes to the Pin Mux Control Group register block:

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• Added new registers in the Pin Mux Control Group for routing QSPI, SD/MMC, UART,

I2C, and SPI signals to the FPGA.

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2014.06.30

• Added address map and register descriptions

Changes

• Updated ECC Parity Control

2014.02.28 Maintenance release

2013.12.30 Maintenance release.

1.2 Minor updates.

1.1 Added functional description, address map and register denitions sections.

1.0 Initial release.

System Manager on page 6-1

Document

Version

Changes

2016.05.03 Added a list of the HPS I/O pins that do not support boundary scan tests in the Arm* JTAG- AP Scan Chains section.

2015.11.02 Maintenance release

2015.05.04 Maintenance release

2014.12.15 Maintenance release

2014.06.30

• Add address map and register denitions

• Remove erroneous reference to CAN controller

2014.02.28 Update to "Scan Manager Block Diagram and System Integration" section

2013.12.30 Minor formatting issues

1.2 Added JTAG-AP descriptions.

1.1 Added block diagram and system integration, functional description, and address map and register denitions sections.

1.0 Initial release.

Scan Manager on page 7-1

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2015.05.04

• Reference AXI ID encoding in MPU chapter

• Add information about the SDRAM address space

2014.12.15

• Minor correction to table in "Available Address Maps"

• Add detail to "L3 Address Space"

2014.06.30

• Corrected master interconnect security properties for:

• Ethernet MAC

• ETR

• Added address map and register descriptions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 Minor updates.

1.1 • Added interconnect connectivity matrix.

• Rearranged functional description sections.

• Simplied address remapping section.

• Added address map and register denitions section.

Changes

1.0 Initial release.

System Interconnect on page 8-1

Document

Version

Changes

2020.09.03 Updated Taking HPS-FPGA Bridges Out of Reset with clarication on the state of the HPS GPIO during cold reset.

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1 Described GPV

1.0 Initial release

HPS-FPGA Bridges on page 9-1

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2020.09.03 Added Interconnect Master (L2M0) to the "HPS Peripheral Master Input IDs" table in HPS Peripheral Master Input IDs.

2020.01.13 Added new section Avoiding ACP Dependency Lockup

2019.06.14 Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,

2016.10.28

• Added note to "AXI Master Conguration for ACP Access" section

• Added "Conguring AxCACHE[3:0] Sideband Signals" and "Conguring AxUser[4:0]

Sideband Signals" subsections to the "AXI Master Conguration for ACP Access" section

• Added note in the "Implementation Details" subsection of the "ACP ID Mapper" section.

2016.05.03 Maintenance release

2015.11.02

• Reordered "L2 Cache" subsections

• Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection"

• Added "L2 Cache Parity" subsection in "L2 Cache" section

2015.05.04 Claried EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section.

2014.12.15

• Added bus transaction scenarios in the "Accelerator Coherency Port" section

• Added the "AxUSER and AxCACHE Attributes" subsection to the "Accelerator Coherency

Port" section

• Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port"

section

• Added the "Conguration for ACP Use" subsection to the "Accelerator Coherency Port"

section

• Claried how to use xed mapping mode in the ACP ID Mapper

• Updated HPS Peripheral Master Input IDs table

• Added a note to the "Control of the AXI User Sideband Signals" subsection in the "ACP ID

Mapper" section.

• Added parity error handling information to the "L1 Caches" section and the "Cache

Controller Conguration" topic of the "L2 Cache" section.

2014.06.30

• Added Reset Section to Cortex-A9 Processor

• Updated HPS Peripheral Master Input IDs table

• Added ACP ID Mapper Address Map and Register Denitions

• Added information in ECC Support section regarding ECC errors

• Minor clarications regarding MPU description and module revision numbers

2014.02.28 Maintenance release

2013.12.30

Correct SDRAM region address in Arm Cortex-A9 MPCoreAddress Map

1.2 Minor updates.

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1.1 • Add description of the ACP ID mapper

• Consolidate redundant information

1.0 Initial release.

Cortex-A9 Microprocessor Unit Subsystem on page 10-1

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Version

Changes

2014.07.31 Updated the address map and register denitions.

2014.06.30 Added address map and register denitions.

2014.02.28 Maintenance release.

2013.12.30 Maintenance release.

1.2 Minor updates.

1.1 Added functional description, programming model, and address map and register denition sections.

1.0 Initial release.

CoreSight Debug and Trace on page 11-1

Document

Version

Changes

2020.02.28 In the Memory Protection section - Corrected the "Protection" eld denition in the "Fields for Rules in Memory Protection Table".

2018.07.17 Modied text to clarify that there is support for up to 4 Gb external memory device per chip select.

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Version

2015.11.02

2015.05.04

2014.12.15

Changes

• Added information regarding calculation of ECC error byte address location from

erraddr register in "User Notication of ECC Errors" section

• Added information regarding bus response to memory protection transaction failure in

"Memory Protection" section

• Claried "Protection" row in "Fields for Rules in Memory Protection" table in the "Memory

Protection" section

• Claried protruledata.security column in "Rules in Memory Protection Table for Example

Conguration" table in the "Example of Conguration for TrustZone" section

• Added note about double-bit error functionality in "ECC Write Backs" subsection of

"ECC" section

• Added the "DDR Calibration" subsection under "DDR PHY" section

• Added the recommended sequence for writing or reading a rule in the "Memory

Protection" section.

• Added SDRAM Protection Access Flow Diagram to "Memory Protection" subsection in

the "Single-Port Controller Operation" section.

• Changed the "SDRAM Multi-Port Scheduling" section to "SDRAM Multi-Port Arbitration"

and added detailed information on how to use and program the priority and weighted arbitration scheme.

2014.6.30

• Added Port Mappings section.

• Added SDRAM Controller Memory Options section.

• Enhanced Example of Conguration for TrustZone section.

• Added SDRAM Controller address map and registers.

2013.12.30

• Added Generating a Preloader Image for HPS with EMIF section.

• Added Debugging HPS SDRAM in the Preloader section.

• Enhanced Simulation section.

1.1 Added address map and register denitions section.

1.0 Initial release.

SDRAM Controller Subsystem on page 12-1

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Changes

2018.01.26 Updated "On-Chip RAM Initialization" section with steps to enable ECC.

2016.10.28 Maintenance release

2016.05.03 Maintenance release

2015.11.02 Maintenance release

2015.05.04 Maintenance release

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2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1 Added address map section

1.0 Initial release

On-Chip Memory on page 13-1

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Version

Changes

2018.01.26 Updated "ECC Enabling" section with steps to enable ECC.

2016.10.28 Added content about the local memory buer

2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

2016.05.03 Maintenance release

2015.11.02

• Moved "Interface Signals" section aer "NAND Flash Controller Block Diagram and

System Integration" section and renamed it to "NAND Flash Controller Signal Descrip‐ tion"

• Updated the Interrupt and DMA Enabling section to recommend reading back a register

to ensure clearing an interrupt status

• Specied the valid values for Burst Length in the Command-Data Pair 4 table

• Updated the description of dma_cmd_comp and added a RESERVED bit for intr_status0/1/

2/3 and intr_en0/1/2/3

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.07.31 Updated address map and register denitions.

2014.06.30 • Added address map and register denitions.

• Removed Command DMA section.

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 • Supports one 8-bit device

• Show additional supported block sizes

• Bad block marker handling

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1.1 Added programming model section.

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NAND Flash Controller on page 14-1

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Changes

2018.01.26 Added "Enabling ECC" section.

2017.12.27 Added 8-bit support for eMMC in the "Features of SD/MMC Controller" section. (FB320076)

2016.10.28

• Removed SPI support in tables in the Features section

• Added 8-bit support for eMMC for SD/MMC

2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

2016.05.03 Maintenance release.

2015.11.02

• Moved "Interface Signals" section below "SD/MMC Controller Block Diagram and System

Integration" section and renamed to "SD/MMC Signal Description." Claried signals in this section.

• Added information that Card Detect is only supported on interfaces routed via the FPGA

fabric.

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1

• Added programming model section.

• Reorganized programming information.

• Added information about ECCs.

• Added pin listing.

• Updated clocks section.

1.0 Initial release.

SD/MMC Controller on page 15-1

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2020.09.03 Updated the denition for the QSPI register: indaddrtrig in the Quad SPI Flash Controller Address Map and Register Denitions section

2019.07.09

2019.06.14

Added a new section, Write Request, with WREN and RDSR information

Maintenance release

2018.01.26 Updated "Local Memory Buer" section with steps to enable ECC.

2016.10.28 Maintenance release

2016.05.27

• Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk;

and the external QSPI output clock, from sclk_out to qspi_clk.

• Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

• Re-worded information about disabling the watermark feature in the "Indirect Read

Operation" and "Indirect Write Operation" sections.

2016.05.03

• Added clarication for the SRAM indirect read and write size allocations.

• Updated the SRAM block on the "Quad SPI Flash Controller Block Diagram and System

Integration" gure.

2015.11.02

• Moved "Interface Signals" section below "Quad SPI Flash Controller Block Diagram and

System Integration"

• Better dened l4_mp_clk clock.

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30

Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 Minor updates.

1.1 Added block diagram and system integration, functional description, programming model, and address map and register denitions sections.

1.0 Initial release.

Quad SPI Flash Controller on page 16-1

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Changes

2018.01.26 Updated "Initializing and Clearing of Memory before Enabling ECC" section with steps to enable ECC.

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2016.10.28 Maintenance release

2016.05.03 Maintenance release

2015.11.02

• Updated link point to the HPS Address Map and Register Denitions

• Added information about the instruction fetch cache properties

• Added a description about the relationship between the GIC interrupt map and INTCLR

2015.05.04

• Added Synopsys* handshake rules.

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30 Added address maps and register denitions

2014.02.28

ECC updates

1.2 Maintenance release

1.1 Minor updates

1.0 Initial release

DMA Controller on page 17-1

Document

Version

Changes

2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks aer bringing the Ethernet PHY out of reset.

2019.06.14 Claied the PCF bit description for encoding value 0x2 in the MAC_Frame_Filter register.

• Claried "Busy Bit" (gb bit of GMII_Address register) in Flow_Control register descrip‐

tion.

• Claried that ttc bit resides in the Operation_Mode Register (Register 6).

• Claried that the pcsancis and the pcslchgis bits of theInterrupt_Status register can

be ignored because they apply to TBI, RTBI, or SGMII interface only.

2016.10.28

• Note added into PHY Interface section

• Bit 16 updated Transmit Descriptor table

2016.05.03 Maintenance release.

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2014.12.15

Changes

• Added the following subsections in the "Layer 3 and Layer 4 Filters" section:

• Layer 3 and Layer 4 Filters Register Set

• Layer 3 Filtering

• Layer 4 Filtering

• Corrected IEEE 1588 timestamp resolution in the "EMAC Block Diagram and System

Integration" section and the "IEEE 1588-2002 Timestamps" section

• Added reset pulse width for rst_clk_tx_n_o and rst_clk_rx_n_o in the "FPGA EMAC

I/O signals" section

• Added subsections "Ordinary Clock," "Boundary Clock," "End-to-End Transparent Clock"

and "Peer-to-Peer Transparent Clock" in the "Clock Type" section

• Updated EMAC Block Diagram and System Integration section with new diagram and

information.

• Added Signal Descriptions section.

• Added EMAC Internal Interfaces section.

• Added TX FIFO and RX FIFO subsection to the Transmit and Receive Data FIFO Buers

section.

• Updated Descriptor Overview section to clarify support for only enhanced (alternate)

descriptors.

• Added Destination and Source Address Filtering Summary in Frame Filtering Section.

• Added Clock Structure sub-section to Clocks and Resets section

• Added System Level EMAC Conguration Registers section in Ethernet Programming Model

• Added EMAC Interface Initialization for FPGA GMII/MII Mode section in Ethernet

Programming Model

• Added EMAC Interface Initialization for RGMII/RMII Mode section in Ethernet Program‐

ming Model

• Corrected DMA Initialization and EMAC Initialization and Conguration titles to appear

on correct initialization information

• Removed duplicate programming information for DMA

• Added Taking the Ethernet MAC Out of Reset section.

2014.06.30

2014.02.28 ECC updates.

1.4 Maintenance release.

1.3

1.2 Updated the HPS boot and FPGA conguration sections.

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Updated EMAC to RGMII Interface table with EMAC Port names Updated EMAC to FPGA PHY Interface table with Signal names Updated EMAC to FPGA IEEE1588 Timestamp Interface with Signal names Added Address Map and Register Descriptions

• Expanded shared memory block table.

• Added CSEL tables.

• Additional minor updates.

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Changes

2018.01.26 Added steps for enabling ECC.

2016.10.28 Maintenance release.

2016.05.03 Maintenance release.

2015.11.02 Renamed "ULPI PHY Interface" section to "USB 2.0 ULPI PHY Signal Description" and moved it aer the "USB OTG Controller Block Diagram and System Integration" section.

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added Taking the USB OTG Out of Reset section.

2014.07.31 Updated address map and register denitions.

2014.06.30 Added USB OTG Controller address map and register denitions.

2014.02.28 Maintenance release.

2013.12.30 Maintenance release.

1.2 • Described interrupt generation.

• Described soware initialization in host and device modes.

• Described soware operation in host and device modes.

• Simplied features list.

• Simplied hardware description.

1.1 Added information about ECCs.

1.0 Initial release.

USB 2.0 OTG Controller on page 19-1

Document

Version

Changes

2017.01.26 Corrected the support information for continuous data transfers in SPI Serial Format.

2016.10.28 Maintenance release.

2016.05.03 Maintenance release.

Arria V Hard Processor System Technical Reference Manual Revision History

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Arria® V Hard Processor System Technical Reference Manual Revision History

av_5v4

2020.09.03

Document

Version

2015.11.02

• Renamed "Interface Pins" section to "Interface to HPS I/O" and moved it under the "SPI

Controller Signal Description" section

• Moved "FPGA Routing" section under "SPI Controller Signal Description" section

• Added Multi-Master mode to "Features of the SPI Controller" section

• Updated "RXD Sample Delay" section

• Updated "SPI Slave" section

• Updated "Glue Logic for Master Port ss_in_n" section

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added Taking the SPI Out of Reset section.

2014.06.30

• "Glue Logic for Master Port ss_in_n" section added

• Interface Pins topic added

• FPGA Routing topic added

• Added address aap and register descriptions

2014.02.28 Maintenance release.

2013.12.30

Minor formatting updates.

Changes

1.2 Minor updates.

1.1 Added programming model, address map and register denitions, clocks, and reset sections.

1.0 Initial release.

SPI Controller on page 20-1

Document Version Changes

2015.05.04

• Added Impact of SCL Rise Time and Fall Time On Generated SCL gure to "Clock Synchronization" section

• Updated "Minimum High and Low Counts" section

2014.12.15

• Maintenance release.

• Added Taking the I2C Out of Reset section.

2014.06.30

HPS I2C Signals for FPGA Routing table updated I2C interface in FPGA Fabric diagram added Added Address Map and Register Descriptions

Altera Corporation

2014.02.28 Maintenance release.

Arria V Hard Processor System Technical Reference Manual Revision History

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Altera Arria V Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents