Altera Arria V Reference Manual

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Arria V Hard Processor System Technical

Reference Manual

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Last updated for Quartus Prime Design Suite: 20.1

av_5v4

2020.09.03

101 Innovation Drive San Jose, CA 95134

www.altera.com

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Arria® V Hard Processor System Technical Reference Manual Revision

History............................................................................................................. 1-1

Introduction to the Hard Processor System....................................................... 2-1

Features of the HPS......................................................................................................................................2-3

HPS Block Diagram and System Integration........................................................................................... 2-4

HPS Block Diagram.........................................................................................................................2-4

Cortex-A9 MPCore..........................................................................................................................2-5

HPS Interfaces.................................................................................................................................. 2-5

System Interconnect.........................................................................................................................2-6

On-Chip Memory............................................................................................................................ 2-7

Flash Memory Controllers..............................................................................................................2-8

Support Peripherals..........................................................................................................................2-9

Interface Peripherals......................................................................................................................2-11

CoreSight Debug and Trace..........................................................................................................2-14

Endian Support.......................................................................................................................................... 2-14

Introduction to the Hard Processor System Address Map...................................................................2-15

HPS Address Spaces.......................................................................................................................2-15

HPS Peripheral Region Address Map..........................................................................................2-17

Clock Manager.....................................................................................................3-1

Features of the Clock Manager...................................................................................................................3-1

Clock Manager Block Diagram and System Integration........................................................................ 3-2

L4 Peripheral Clocks........................................................................................................................3-3

Functional Description of the Clock Manager.........................................................................................3-5

Clock Manager Building Blocks.....................................................................................................3-5

Hardware-Managed and Soware-Managed Clocks...................................................................3-7

Clock Groups....................................................................................................................................3-7

Resets............................................................................................................................................... 3-17

Safe Mode........................................................................................................................................3-17

Interrupts.........................................................................................................................................3-18

Clock Usage By Module................................................................................................................ 3-18

Clock Manager Address Map and Register Denitions........................................................................3-23

Reset Manager..................................................................................................... 4-1

Reset Manager Block Diagram and System Integration.........................................................................4-2

HPS External Reset Sources............................................................................................................4-3

Reset Controller................................................................................................................................4-4

Module Reset Signals.......................................................................................................................4-5

Slave Interface and Status Register.............................................................................................. 4-10

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Functional Description of the Reset Manager....................................................................................... 4-10

Reset Sequencing............................................................................................................................4-11

Reset Pins........................................................................................................................................ 4-15

Reset Eects.................................................................................................................................... 4-15

Altering Warm Reset System Response...................................................................................... 4-15

Reset Handshaking........................................................................................................................ 4-16

Reset Manager Address Map and Register Denitions.........................................................................4-16

FPGA Manager.................................................................................................... 5-1

Features of the FPGA Manager..................................................................................................................5-1

FPGA Manager Block Diagram and System Integration........................................................................5-2

Functional Description of the FPGA Manager........................................................................................5-3

FPGA Manager Building Blocks....................................................................................................5-3

FPGA Conguration....................................................................................................................... 5-4

FPGA Status......................................................................................................................................5-8

Error Message Extraction................................................................................................................5-8

Boot Handshake...............................................................................................................................5-8

General Purpose I/O........................................................................................................................5-9

Clock..................................................................................................................................................5-9

Reset...................................................................................................................................................5-9

FPGA Manager Address Map and Register Denitions.........................................................................5-9

System Manager...................................................................................................6-1

Features of the System Manager.................................................................................................................6-1

System Manager Block Diagram and System Integration......................................................................6-2

Functional Description of the System Manager.......................................................................................6-3

Boot Conguration and System Information.............................................................................. 6-3

Additional Module Control............................................................................................................6-3

Boot ROM Code...............................................................................................................................6-6

FPGA Interface Enables.................................................................................................................. 6-7

ECC and Parity Control..................................................................................................................6-8

Preloader Hando Information..................................................................................................... 6-8

Clocks................................................................................................................................................ 6-8

Resets................................................................................................................................................. 6-8

System Manager Address Map and Register Denitions........................................................................6-9

Scan Manager.......................................................................................................7-1

Features of the Scan Manager.....................................................................................................................7-1

Scan Manager Block Diagram and System Integration.......................................................................... 7-2

Arm JTAG-AP Signal Use in the Scan Manager..........................................................................7-2

Arm JTAG-AP Scan Chains............................................................................................................7-3

Functional Description of the Scan Manager...........................................................................................7-5

Conguring HPS I/O Scan Chains................................................................................................7-5

Communicating with the JTAG TAP Controller.........................................................................7-6

JTAG-AP FIFO Buer Access and Byte Command Protocol.................................................... 7-6

Clocks................................................................................................................................................ 7-7

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Resets................................................................................................................................................. 7-8

Scan Manager Address Map and Register Denitions............................................................................7-8

JTAG-AP Register Name Cross Reference Table......................................................................... 7-8

System Interconnect............................................................................................ 8-1

Features of the System Interconnect..........................................................................................................8-1

System Interconnect Block Diagram and System Integration............................................................... 8-2

Interconnect Block Diagram.......................................................................................................... 8-2

System Interconnect Architecture..................................................................................................8-2

Main Connectivity Matrix.............................................................................................................. 8-3

Functional Description of the Interconnect.............................................................................................8-4

Master to Slave Connectivity Matrix.............................................................................................8-4

System Interconnect Address Spaces.............................................................................................8-5

Master Caching and Buering Overrides...................................................................................8-13

Security............................................................................................................................................8-13

Conguring the Quality of Service Logic................................................................................... 8-14

Cyclic Dependency Avoidance Schemes.....................................................................................8-14

System Interconnect Master Properties...................................................................................... 8-15

Interconnect Slave Properties.......................................................................................................8-17

Upsizing Data Width Function....................................................................................................8-19

Downsizing Data Width Function...............................................................................................8-20

Lock Support...................................................................................................................................8-21

FIFO Buers and Clock Crossing................................................................................................8-21

System Interconnect Resets.......................................................................................................... 8-22

System Interconnect Address Map and Register Denitions...............................................................8-22

HPS-FPGA Bridges............................................................................................. 9-1

Features of the HPS-FPGA Bridges...........................................................................................................9-1

HPS-FPGA Bridges Block Diagram and System Integration.................................................................9-3

Functional Description of the HPS-FPGA Bridges.................................................................................9-4

e Global Programmers View......................................................................................................9-4

Functional Description of the FPGA-to-HPS Bridge..................................................................9-4

Functional Description of the HPS-to-FPGA Bridge..................................................................9-7

Functional Description of the Lightweight HPS-to-FPGA Bridge..........................................9-10

Clocks and Resets...........................................................................................................................9-14

Data Width Sizing..........................................................................................................................9-15

HPS-FPGA Bridges Address Map and Register Denitions................................................................9-16

Cortex-A9 Microprocessor Unit Subsystem..................................................... 10-1

Features of the Cortex-A9 MPU Subsystem...........................................................................................10-1

Cortex-A9 MPU Subsystem Block Diagram and System Integration................................................10-2

Cortex-A9 MPU Subsystem with System Interconnect............................................................10-2

Cortex-A9 MPU Subsystem Internals.........................................................................................10-3

Cortex-A9 MPCore....................................................................................................................................10-4

Functional Description..................................................................................................................10-4

Implementation Details.................................................................................................................10-5

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Cortex-A9 Processor..................................................................................................................... 10-6

Interactive Debugging Features....................................................................................................10-7

L1 Caches........................................................................................................................................ 10-7

Preload Engine............................................................................................................................... 10-7

Floating Point Unit.........................................................................................................................10-8

NEON Multimedia Processing Engine....................................................................................... 10-8

Memory Management Unit..........................................................................................................10-9

Performance Monitoring Unit....................................................................................................10-12

Arm Cortex-A9 MPCore Timers...............................................................................................10-12

Generic Interrupt Controller......................................................................................................10-13

Global Timer.................................................................................................................................10-24

Snoop Control Unit..................................................................................................................... 10-25

Accelerator Coherency Port....................................................................................................... 10-27

ACP ID Mapper.......................................................................................................................................10-31

Functional Description............................................................................................................... 10-32

Implementation Details...............................................................................................................10-32

ACP ID Mapper Address Map and Register Denitions........................................................10-38

L2 Cache....................................................................................................................................................10-38

Functional Description............................................................................................................... 10-38

CPU Prefetch............................................................................................................................................10-45

Debugging Modules.................................................................................................................................10-45

Program Trace..............................................................................................................................10-45

Event Trace....................................................................................................................................10-46

Cross-Triggering.......................................................................................................................... 10-47

Clocks........................................................................................................................................................ 10-47

Cortex-A9 MPU Subsystem Register Implementation.......................................................................10-47

Cortex-A9 MPU Subsystem Address Map...............................................................................10-48

L2 Cache Controller Address Map............................................................................................ 10-49

CoreSight Debug and Trace...............................................................................11-1

Features of CoreSight Debug and Trace..................................................................................................11-2

Arm CoreSight Documentation...............................................................................................................11-2

CoreSight Debug and Trace Block Diagram and System Integration.................................................11-3

Functional Description of CoreSight Debug and Trace........................................................................11-4

Debug Access Port......................................................................................................................... 11-4

System Trace Macrocell.................................................................................................................11-4

Trace Funnel................................................................................................................................... 11-5

CoreSight Trace Memory Controller...........................................................................................11-5

AMBA Trace Bus Replicator.........................................................................................................11-6

Trace Port Interface Unit...............................................................................................................11-6

Embedded Cross Trigger System.................................................................................................11-6

Program Trace Macrocell............................................................................................................11-11

HPS Debug APB Interface..........................................................................................................11-11

FPGA Interface.............................................................................................................................11-11

Debug Clocks................................................................................................................................11-14

Debug Resets................................................................................................................................ 11-15

CoreSight Debug and Trace Programming Model..............................................................................11-16

Coresight Component Address..................................................................................................11-17

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STM Channels..............................................................................................................................11-18

CTI Trigger Connections to Outside the Debug System........................................................11-19

Conguring Embedded Cross-Trigger Connections..............................................................11-21

CoreSight Debug and Trace Address Map and Register Denitions................................................11-22

SDRAM Controller Subsystem..........................................................................12-1

Features of the SDRAM Controller Subsystem......................................................................................12-1

SDRAM Controller Subsystem Block Diagram.....................................................................................12-2

SDRAM Controller Memory Options.....................................................................................................12-3

SDRAM Controller Subsystem Interfaces.............................................................................................. 12-4

MPU Subsystem Interface.............................................................................................................12-4

L3 Interconnect Interface..............................................................................................................12-4

CSR Interface..................................................................................................................................12-5

FPGA-to-HPS SDRAM Interface.................................................................................................12-5

Memory Controller Architecture.............................................................................................................12-6

Multi-Port Front End.....................................................................................................................12-7

Single-Port Controller................................................................................................................... 12-8

Functional Description of the SDRAM Controller Subsystem..........................................................12-10

MPFE Operation Ordering.........................................................................................................12-10

MPFE Multi-Port Arbitration....................................................................................................12-10

MPFE SDRAM Burst Scheduling..............................................................................................12-13

Single-Port Controller Operation..............................................................................................12-14

SDRAM Power Management.................................................................................................................12-24

DDR PHY................................................................................................................................................. 12-25

DDR Calibration..........................................................................................................................12-25

Clocks........................................................................................................................................................ 12-25

Resets......................................................................................................................................................... 12-26

Taking the SDRAM Controller Subsystem Out of Reset .......................................................12-26

Port Mappings..........................................................................................................................................12-26

Initialization..............................................................................................................................................12-27

FPGA-to-SDRAM Protocol Details...........................................................................................12-28

SDRAM Controller Subsystem Programming Model........................................................................ 12-32

HPS Memory Interface Architecture.........................................................................................12-32

HPS Memory Interface Conguration......................................................................................12-32

HPS Memory Interface Simulation........................................................................................... 12-33

Generating a Preloader Image for HPS with EMIF.................................................................12-34

Debugging HPS SDRAM in the Preloader...........................................................................................12-35

Enabling UART or Semihosting Printout.................................................................................12-35

Enabling Simple Memory Test...................................................................................................12-36

Enabling the Debug Report........................................................................................................12-37

Writing a Predened Data Pattern to SDRAM in the Preloader...........................................12-40

SDRAM Controller Address Map and Register Denitions.............................................................. 12-41

On-Chip Memory.............................................................................................. 13-1

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On-Chip RAM............................................................................................................................................13-1

Features of the On-Chip RAM.....................................................................................................13-1

On-Chip RAM Block Diagram and System Integration...........................................................13-1

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Functional Description of the On-Chip RAM...........................................................................13-2

Boot ROM...................................................................................................................................................13-3

Features of the Boot ROM............................................................................................................13-3

Boot ROM Block Diagram and System Integration..................................................................13-3

Functional Description of the Boot ROM..................................................................................13-3

On-Chip Memory Address Map and Register Denitions.................................................................. 13-4

NAND Flash Controller.................................................................................... 14-1

NAND Flash Controller Features............................................................................................................ 14-1

NAND Flash Controller Block Diagram and System Integration.......................................................14-2

NAND Flash Controller Signal Descriptions.........................................................................................14-2

Functional Description of the NAND Flash Controller.......................................................................14-3

Discovery and Initialization......................................................................................................... 14-3

Bootstrap Interface.........................................................................................................................14-4

Conguration by Host...................................................................................................................14-5

Local Memory Buer.....................................................................................................................14-6

Clocks.............................................................................................................................................. 14-6

Resets............................................................................................................................................... 14-7

Indexed Addressing....................................................................................................................... 14-7

Command Mapping...................................................................................................................... 14-8

Data DMA.....................................................................................................................................14-14

ECC................................................................................................................................................14-18

NAND Flash Controller Programming Model....................................................................................14-21

Basic Flash Programming...........................................................................................................14-22

Flash-Related Special Function Operations.............................................................................14-25

NAND Flash Controller Address Map and Register Denitions......................................................14-33

SD/MMC Controller..........................................................................................15-1

Features of the SD/MMC Controller.......................................................................................................15-1

SD Card Support Matrix............................................................................................................... 15-2

MMC Support Matrix....................................................................................................................15-3

SD/MMC Controller Block Diagram and System Integration............................................................ 15-3

SD/MMC Controller Signal Description................................................................................................15-4

Functional Description of the SD/MMC Controller.............................................................................15-5

SD/MMC/CE-ATA Protocol........................................................................................................ 15-5

BIU...................................................................................................................................................15-6

CIU.................................................................................................................................................15-20

Clocks............................................................................................................................................ 15-35

Resets............................................................................................................................................. 15-36

Voltage Switching.........................................................................................................................15-37

SD/MMC Controller Programming Model......................................................................................... 15-39

Soware and Hardware Restrictions†....................................................................................... 15-39

Initialization†................................................................................................................................15-41

Controller/DMA/FIFO Buer Reset Usage..............................................................................15-47

Enabling ECC...............................................................................................................................15-47

Enabling FIFO Buer ECC.........................................................................................................15-47

Non-Data Transfer Commands................................................................................................. 15-48

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Data Transfer Commands...........................................................................................................15-50

Transfer Stop and Abort Commands........................................................................................15-56

Internal DMA Controller Operations.......................................................................................15-58

Commands for SDIO Card Devices.......................................................................................... 15-60

CE-ATA Data Transfer Commands.......................................................................................... 15-62

Card Read reshold...................................................................................................................15-70

Interrupt and Error Handling.................................................................................................... 15-73

Booting Operation for eMMC and MMC................................................................................15-74

SD/MMC Controller Address Map and Register Denitions............................................................15-84

Quad SPI Flash Controller................................................................................ 16-1

Features of the Quad SPI Flash Controller.............................................................................................16-1

Quad SPI Flash Controller Block Diagram and System Integration...................................................16-2

Interface Signals......................................................................................................................................... 16-3

Functional Description of the Quad SPI Flash Controller...................................................................16-3

Overview......................................................................................................................................... 16-3

Data Slave Interface....................................................................................................................... 16-4

SPI Legacy Mode............................................................................................................................16-7

Register Slave Interface..................................................................................................................16-8

Local Memory Buer.....................................................................................................................16-8

DMA Peripheral Request Controller...........................................................................................16-9

Arbitration between Direct/Indirect Access Controller and STIG.......................................16-10

Conguring the Flash Device.....................................................................................................16-10

XIP Mode......................................................................................................................................16-12

Write Protection...........................................................................................................................16-12

Data Slave Sequential Access Detection................................................................................... 16-13

Clocks............................................................................................................................................ 16-13

Resets............................................................................................................................................. 16-13

Interrupts...................................................................................................................................... 16-14

Quad SPI Flash Controller Programming Model................................................................................16-15

Setting Up the Quad SPI Flash Controller................................................................................16-16

Indirect Read Operation with DMA Disabled.........................................................................16-16

Indirect Read Operation with DMA Enabled..........................................................................16-17

Indirect Write Operation with DMA Disabled........................................................................16-17

Indirect Write Operation with DMA Enabled.........................................................................16-18

XIP Mode Operations................................................................................................................. 16-18

Quad SPI Flash Controller Address Map and Register Denitions..................................................16-20

DMA Controller................................................................................................ 17-1

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Features of the DMA Controller..............................................................................................................17-1

DMA Controller Block Diagram and System Integration....................................................................17-3

Functional Description of the DMA Controller....................................................................................17-3

Peripheral Request Interface.........................................................................................................17-4

DMA Controller Address Map and Register Denitions.....................................................................17-7

Address Map and Register Denitions........................................................................................17-9

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Ethernet Media Access Controller.................................................................... 18-1

Features of the Ethernet MAC..................................................................................................................18-2

MAC.................................................................................................................................................18-2

DMA................................................................................................................................................18-2

Management Interface...................................................................................................................18-3

Acceleration....................................................................................................................................18-3

PHY Interface.................................................................................................................................18-3

EMAC Block Diagram and System Integration.....................................................................................18-4

EMAC Signal Description.........................................................................................................................18-5

HPS EMAC I/O Signals.................................................................................................................18-6

FPGA EMAC I/O Signals..............................................................................................................18-8

PHY Management Interface.......................................................................................................18-11

EMAC Internal Interfaces.......................................................................................................................18-12

DMA Master Interface................................................................................................................ 18-12

Timestamp Interface....................................................................................................................18-13

Functional Description of the EMAC................................................................................................... 18-14

Transmit and Receive Data FIFO Buers.................................................................................18-15

DMA Controller...........................................................................................................................18-16

Descriptor Overview................................................................................................................... 18-29

IEEE 1588-2002 Timestamps.....................................................................................................18-46

IEEE 1588-2008 Advanced Timestamps...................................................................................18-52

IEEE 802.3az Energy Ecient Ethernet....................................................................................18-55

Checksum Ooad....................................................................................................................... 18-56

Frame Filtering.............................................................................................................................18-56

Clocks and Resets.........................................................................................................................18-61

Interrupts...................................................................................................................................... 18-63

Ethernet MAC Programming Model.................................................................................................... 18-63

System Level EMAC Conguration Registers..........................................................................18-63

EMAC FPGA Interface Initialization........................................................................................18-65

EMAC HPS Interface Initialization...........................................................................................18-66

DMA Initialization.......................................................................................................................18-66

EMAC Initialization and Conguration...................................................................................18-67

Performing Normal Receive and Transmit Operation........................................................... 18-68

Stopping and Starting Transmission......................................................................................... 18-69

Programming Guidelines for Energy Ecient Ethernet........................................................ 18-69

Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output..............................18-70

Ethernet MAC Address Map and Register Denitions.......................................................................18-72

USB 2.0 OTG Controller................................................................................... 19-1

Features of the USB OTG Controller...................................................................................................... 19-2

Supported PHYS.............................................................................................................................19-3

USB OTG Controller Block Diagram and System Integration............................................................19-4

USB 2.0 ULPI PHY Signal Description...................................................................................................19-5

Functional Description of the USB OTG Controller............................................................................19-6

USB OTG Controller Block Description.................................................................................... 19-6

Local Memory Buer...................................................................................................................19-10

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Clocks............................................................................................................................................ 19-10

Resets............................................................................................................................................. 19-10

Interrupts...................................................................................................................................... 19-11

USB OTG Controller Programming Model.........................................................................................19-13

Enabling ECC...............................................................................................................................19-13

Enabling SPRAM ECCs.............................................................................................................. 19-13

Host Operation.............................................................................................................................19-14

Device Operation.........................................................................................................................19-15

USB 2.0 OTG Controller Address Map and Register Denitions.....................................................19-17

USB Data FIFO Address Map.................................................................................................... 19-17

USB Direct Access FIFO RAM Address Map..........................................................................19-19

SPI Controller....................................................................................................20-1

Features of the SPI Controller..................................................................................................................20-1

SPI Block Diagram and System Integration...........................................................................................20-2

SPI Block Diagram.........................................................................................................................20-2

SPI Controller Signal Description........................................................................................................... 20-3

Interface to HPS I/O......................................................................................................................20-3

FPGA Routing................................................................................................................................20-3

Functional Description of the SPI Controller........................................................................................20-4

Protocol Details and Standards Compliance..............................................................................20-4

SPI Controller Overview...............................................................................................................20-5

Transfer Modes...............................................................................................................................20-8

SPI Master.......................................................................................................................................20-9

SPI Slave........................................................................................................................................ 20-12

Partner Connection Interfaces...................................................................................................20-16

DMA Controller Interface.......................................................................................................... 20-21

Slave Interface...............................................................................................................................20-21

Clocks and Resets.........................................................................................................................20-22

SPI Programming Model........................................................................................................................ 20-23

Master SPI and SSP Serial Transfers..........................................................................................20-24

Master Microwire Serial Transfers.............................................................................................20-26

Slave SPI and SSP Serial Transfers............................................................................................. 20-28

Slave Microwire Serial Transfers................................................................................................20-29

Soware Control for Slave Selection......................................................................................... 20-29

DMA Controller Operation........................................................................................................20-30

SPI Controller Address Map and Register Denitions.......................................................................20-33

I2C Controller....................................................................................................21-1

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Features of the I2C Controller..................................................................................................................21-1

I2C Controller Block Diagram and System Integration........................................................................21-2

I2C Controller Signal Description........................................................................................................... 21-3

Functional Description of the I2C Controller........................................................................................21-4

Feature Usage..................................................................................................................................21-4

Behavior...........................................................................................................................................21-5

Protocol Details..............................................................................................................................21-6

Multiple Master Arbitration.......................................................................................................21-11

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Clock Frequency Conguration................................................................................................ 21-13

SDA Hold Time............................................................................................................................21-15

DMA Controller Interface.......................................................................................................... 21-15

Clocks............................................................................................................................................ 21-15

Resets............................................................................................................................................. 21-15

I2C Controller Programming Model.....................................................................................................21-16

Slave Mode Operation.................................................................................................................21-16

Master Mode Operation..............................................................................................................21-19

Disabling the I2C Controller...................................................................................................... 21-20

DMA Controller Operation........................................................................................................21-20

I2C Controller Address Map and Register Denitions.......................................................................21-24

UART Controller............................................................................................... 22-1

UART Controller Features........................................................................................................................22-1

UART Controller Block Diagram and System Integration...................................................................22-2

UART Controller Signal Description...................................................................................................... 22-3

HPS I/O Pins...................................................................................................................................22-3

FPGA Routing................................................................................................................................22-3

Functional Description of the UART Controller...................................................................................22-4

FIFO Buer Support......................................................................................................................22-4

UART(RS232) Serial Protocol......................................................................................................22-5

Automatic Flow Control............................................................................................................... 22-5

Clocks.............................................................................................................................................. 22-7

Resets............................................................................................................................................... 22-7

Interrupts.........................................................................................................................................22-7

DMA Controller Operation....................................................................................................................22-10

Transmit FIFO Underow..........................................................................................................22-11

Transmit Watermark Level......................................................................................................... 22-11

Transmit FIFO Overow............................................................................................................ 22-12

Receive FIFO Overow...............................................................................................................22-13

Receive Watermark Level............................................................................................................22-13

Receive FIFO Underow.............................................................................................................22-13

UART Controller Address Map and Register Denitions..................................................................22-14

General-Purpose I/O Interface......................................................................... 23-1

Features of the GPIO Interface.................................................................................................................23-1

GPIO Interface Block Diagram and System Integration......................................................................23-2

Functional Description of the GPIO Interface.......................................................................................23-2

Debounce Operation..................................................................................................................... 23-2

Pin Directions.................................................................................................................................23-3

Taking the GPIO Interface Out of Reset ....................................................................................23-3

GPIO Pin State During Reset....................................................................................................... 23-3

GPIO Interface Programming Model..................................................................................................... 23-4

General-Purpose I/O Interface Address Map and Register Denitions.............................................23-4

Timer .................................................................................................................24-1

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Features of the Timer.................................................................................................................................24-1

Timer Block Diagram and System Integration...................................................................................... 24-1

Functional Description of the Timer.......................................................................................................24-2

Clocks.............................................................................................................................................. 24-3

Resets............................................................................................................................................... 24-3

Interrupts.........................................................................................................................................24-3

FPGA Interface...............................................................................................................................24-3

Timer Programming Model..................................................................................................................... 24-5

Initialization....................................................................................................................................24-5

Enabling the Timer........................................................................................................................24-5

Disabling the Timer.......................................................................................................................24-5

Loading the Timer Countdown Value.........................................................................................24-5

Servicing Interrupts.......................................................................................................................24-6

Timer Address Map and Register Denitions........................................................................................24-6

Watchdog Timer................................................................................................ 25-1

Features of the Watchdog Timer..............................................................................................................25-1

Watchdog Timer Block Diagram and System Integration................................................................... 25-2

Functional Description of the Watchdog Timer....................................................................................25-2

Watchdog Timer Counter.............................................................................................................25-2

Watchdog Timer Pause Mode......................................................................................................25-3

Watchdog Timer Clocks................................................................................................................25-3

Watchdog Timer Resets.................................................................................................................25-3

FPGA Interface...............................................................................................................................25-4

Watchdog Timer Programming Model...................................................................................................25-4

Setting the Timeout Period Values.............................................................................................. 25-4

Selecting the Output Response Mode......................................................................................... 25-4

Enabling and Initially Starting a Watchdog Timer....................................................................25-5

Reloading a Watchdog Counter...................................................................................................25-5

Pausing a Watchdog Timer...........................................................................................................25-5

Disabling and Stopping a Watchdog Timer................................................................................25-5

Watchdog Timer State Machine...................................................................................................25-5

Watchdog Timer Address Map and Register Denitions.....................................................................25-7

Introduction to the HPS Component............................................................... 26-1

Instantiating the HPS Component................................................................... 27-1

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MPU Subsystem.........................................................................................................................................26-2

Arm CoreSight Debug Components.......................................................................................................26-2

Interconnect................................................................................................................................................26-2

HPS-to-FPGA Interfaces...........................................................................................................................26-2

Memory Controllers..................................................................................................................................26-3

Support Peripherals....................................................................................................................................26-3

Interface Peripherals..................................................................................................................................26-3

On-Chip Memories....................................................................................................................................26-4

FPGA Interfaces.........................................................................................................................................27-1

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General Interfaces..........................................................................................................................27-2

FPGA-to-HPS SDRAM Interface.................................................................................................27-3

DMA Peripheral Request.............................................................................................................. 27-5

Interrupts.........................................................................................................................................27-5

AXI Bridges.....................................................................................................................................27-7

Conguring HPS Clocks and Resets....................................................................................................... 27-8

User Clocks.....................................................................................................................................27-8

Reset Interfaces...............................................................................................................................27-9

PLL Reference Clocks..................................................................................................................27-10

Peripheral FPGA Clocks.............................................................................................................27-11

Conguring Peripheral Pin Multiplexing.............................................................................................27-11

Conguring Peripherals..............................................................................................................27-12

Connecting Unassigned Pins to GPIO......................................................................................27-12

Using Unassigned IO as LoanIO................................................................................................27-13

Resolving Pin Multiplexing Conicts........................................................................................27-13

Peripheral Signals Routed to FPGA ..........................................................................................27-14

Conguring the External Memory Interface........................................................................................27-14

Selecting PLL Output Frequency and Phase............................................................................ 27-15

Using the Address Span Extender Component....................................................................................27-15

Generating and Compiling the HPS Component............................................................................... 27-16

HPS Component Interfaces...............................................................................28-1

Memory-Mapped Interfaces.....................................................................................................................28-1

FPGA-to-HPS Bridge....................................................................................................................28-1

HPS-to-FPGA and Lightweight HPS-to-FPGA Bridges...........................................................28-2

FPGA-to-HPS SDRAM Interface.................................................................................................28-3

Clocks.......................................................................................................................................................... 28-4

Alternative Clock Inputs to HPS PLLs........................................................................................28-4

User Clocks.....................................................................................................................................28-4

AXI Bridge FPGA Interface Clocks.............................................................................................28-5

SDRAM Clocks.............................................................................................................................. 28-5

Peripheral FPGA Clocks............................................................................................................... 28-5

Resets........................................................................................................................................................... 28-6

HPS-to-FPGA Reset Interfaces....................................................................................................28-6

HPS External Reset Request......................................................................................................... 28-6

Peripheral Reset Interfaces............................................................................................................28-7

Debug and Trace Interfaces...................................................................................................................... 28-7

Trace Port Interface Unit...............................................................................................................28-7

FPGA System Trace Macrocell Events Interface........................................................................28-7

FPGA Cross Trigger Interface...................................................................................................... 28-7

Debug APB Interface.....................................................................................................................28-7

Peripheral Signal Interfaces...................................................................................................................... 28-7

DMA Controller Interface............................................................................................................ 28-7

Other Interfaces..........................................................................................................................................28-8

MPU Standby and Event Interfaces.............................................................................................28-8

General Purpose Signals............................................................................................................... 28-9

FPGA-to-HPS Interrupts..............................................................................................................28-9

Boot from FPGA Interface............................................................................................................28-9

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Page 14

TOC-14

Input-only General Purpose Interface........................................................................................ 28-9

Simulating the HPS Component.......................................................................29-1

Simulation Flows........................................................................................................................................29-2

Setting Up the HPS Component for Simulation........................................................................29-3

Generating the HPS Simulation Model in Platform Designer (Standard).............................29-5

Running the Simulations...............................................................................................................29-5

Clock and Reset Interfaces........................................................................................................................29-9

Clock Interface............................................................................................................................... 29-9

Reset Interface..............................................................................................................................29-10

FPGA-to-HPS AXI Slave Interface........................................................................................................29-11

HPS-to-FPGA AXI Master Interface.....................................................................................................29-12

Lightweight HPS-to-FPGA AXI Master Interface...............................................................................29-12

FPGA-to-HPS SDRAM Interface.......................................................................................................... 29-13

HPS Memory Interface Simulation........................................................................................... 29-13

HPS-to-FPGA MPU Event Interface.....................................................................................................29-14

Interrupts Interface..................................................................................................................................29-14

HPS-to-FPGA Debug APB Interface.................................................................................................... 29-16

FPGA-to-HPS System Trace Macrocell Hardware Event Interface...................................................29-16

HPS-to-FPGA Cross-Trigger Interface.................................................................................................29-17

HPS-to-FPGA Trace Port Interface.......................................................................................................29-17

FPGA-to-HPS DMA Handshake Interface...........................................................................................29-18

Boot from FPGA Interface......................................................................................................................29-19

General Purpose Input Interface............................................................................................................29-20

Booting and Conguration................................................................................ A-1

Boot Overview.............................................................................................................................................A-1

FPGA Conguration Overview.................................................................................................................A-1

Booting and Conguration Options.........................................................................................................A-2

Boot Denitions.......................................................................................................................................... A-5

Reset.................................................................................................................................................. A-5

Boot ROM........................................................................................................................................ A-5

Boot Select........................................................................................................................................ A-6

Flash Memory Devices for Booting............................................................................................ A-13

Clock Select.................................................................................................................................... A-25

I/O Conguration......................................................................................................................... A-25

L4 Watchdog 0 Timer................................................................................................................... A-26

Preloader.........................................................................................................................................A-26

U-Boot Loader...............................................................................................................................A-26

Boot ROM Flow.........................................................................................................................................A-26

Typical Preloader Boot Flow....................................................................................................................A-28

HPS State on Entry to the Preloader...........................................................................................A-31

Shared Memory............................................................................................................................. A-31

Loading the Preloader Image.......................................................................................................A-32

FPGA Conguration.................................................................................................................................A-33

Full Conguration.........................................................................................................................A-33

Partial Reconguration.................................................................................................................A-34

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Reference Manual Revision History

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Chapter Date of Last Update

Introduction to the Hard Processor System

Clock Manager November 2, 2015 Reset Manager November 2, 2015 FPGA Manager June 14, 2019 System Manager July 17, 2018 Scan Manager May 3, 2016 System Interconnect May 4, 2015 HPS-FPGA Bridges September 3, 2020

Cortex®-A9 Microprocessor Unit Subsystem

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October 28, 2016

September 3, 2020

CoreSight* Debug and Trace July 31, 2014

SDRAM Controller Subsystem

February 28, 2020

Controller On-Chip Memory January 26, 2018 NAND Flash Controller January 26, 2018 SD/MMC Controller January 26, 2018 Quad SPI Flash Controller September 3, 2020 DMA Controller January 26, 2018 Ethernet Media Access Controller June 14, 2019 USB 2.0 OTG Controller January 26, 2018 SPI Controller January 26, 2018

I2C Controller May 4, 2015 UART Controller November 2, 2015

Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others.

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Chapter Date of Last Update

General-Purpose I/O Interface September 3, 2020 Timer June 30, 2014 Watchdog Timer November 2, 2015 Introduction to the HPS Component December 30, 2013 Instantiating the HPS Component November 2, 2015 HPS Component Interfaces May 4, 2015 Simulating the HPS Component May 3, 2016 Booting and Conguration September 3, 2020

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Version

2016.10.28

2016.05.03

• Added 8-bit support for eMMC for SD/MMC

• Renamed MPU Subsystem to Cortex-A9 MPCore

Maintenance release.

Changes

2015.11.02 Updated the link to the Memory Maps.

2015.05.04 Corrected the base address for NANDDATA in the "Peripheral Region Address Map" table.

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30 Maintenance release

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.3 Minor updates.

1.2 Updated address spaces section.

1.1 Added peripheral region address map.

1.0 Initial release.

Introduction to the Hard Processor System on page 2-1

Document

Version

2020.01.13 Correct typical sdmmc_clk frequencies in Flash Controller Clocks

2015.11.02 Minor formatting updates.

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Changes

2015.05.04 Minor formatting updates.

2014.12.15

FREF, FVCO, and FOUT Equations section updated. More information added about vco register, M and N equations.

Reference Clock information added to Clock Groups section.

2014.06.30

E0SC1 changed to HPS_CLK1 E0SC2 changed to HPS_CLK2 Added Address Map and Register Descriptions

2014.02.28

2013.12.30

Updated content in the "Peripheral Clock Group" section

Minor formatting updates.

1.2 Minor updates.

1.1 • Reorganized and expanded functional description section.

• Added address map and register denitions section.

1.0 Initial release.

Clock Manager on page 3-1

Document

Version

2015.11.02 Updated "Reset Pins" section

2015.05.04 Updated:

• MISC Group, Generated Module Resets table

• "Reset Pins" section

2014.12.15

• Signal power information added to "HPS External Reset Sources" section

• Updated block diagram with h2f_dbg_rst_n signal

2014.06.30

• Updated "Functional Description of Reset Manager"

• Added address map and register descriptions

2014.02.28

Updated sections:

• Reset Sequencing

• Warm Reset Assertion Sequence

Changes

2013.12.30

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1.2 • Added cold and warm reset timing diagrams.

1.1 Added reset controller, functional description, and address map and register denitions sections.

1.0 Initial release.

Reset Manager on page 4-1

Document

Version

Changes

2019.06.14 Corrected the msel descriptions for encodings 0x0 through 0x2 and 0x4 to 0x6 in the stat register.

2015.11.02 Provided more information for the conguration schemes for the dedicated pins.

2015.05.04 Added information about FPPx32.

2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Minor updates.

1.3 Minor updates.

1.2 Updated the FPGA conguration section.

1.1 • Updated the conguration schemes table.

• Updated the FPGA conguration section.

• Added address map and register denitions section.

1.0 Initial release.

FPGA Manager

Document

Version

on page 5-1

Changes

2018.11.03 Modied mode register biteld descriptions for clarity.

2018.07.17 Made the following changes to the Pin Mux Control Group register block:

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• Added new registers in the Pin Mux Control Group for routing QSPI, SD/MMC, UART,

I2C, and SPI signals to the FPGA.

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2014.06.30

• Added address map and register descriptions

Changes

• Updated ECC Parity Control

2014.02.28 Maintenance release

2013.12.30 Maintenance release.

1.2 Minor updates.

1.1 Added functional description, address map and register denitions sections.

1.0 Initial release.

System Manager on page 6-1

Document

Version

Changes

2016.05.03 Added a list of the HPS I/O pins that do not support boundary scan tests in the Arm* JTAG- AP Scan Chains section.

2015.11.02 Maintenance release

2015.05.04 Maintenance release

2014.12.15 Maintenance release

2014.06.30

• Add address map and register denitions

• Remove erroneous reference to CAN controller

2014.02.28 Update to "Scan Manager Block Diagram and System Integration" section

2013.12.30 Minor formatting issues

1.2 Added JTAG-AP descriptions.

1.1 Added block diagram and system integration, functional description, and address map and register denitions sections.

1.0 Initial release.

Scan Manager on page 7-1

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2015.05.04

• Reference AXI ID encoding in MPU chapter

• Add information about the SDRAM address space

2014.12.15

• Minor correction to table in "Available Address Maps"

• Add detail to "L3 Address Space"

2014.06.30

• Corrected master interconnect security properties for:

• Ethernet MAC

• ETR

• Added address map and register descriptions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 Minor updates.

1.1 • Added interconnect connectivity matrix.

• Rearranged functional description sections.

• Simplied address remapping section.

• Added address map and register denitions section.

Changes

1.0 Initial release.

System Interconnect on page 8-1

Document

Version

Changes

2020.09.03 Updated Taking HPS-FPGA Bridges Out of Reset with clarication on the state of the HPS GPIO during cold reset.

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1 Described GPV

1.0 Initial release

HPS-FPGA Bridges on page 9-1

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Changes

2020.09.03 Added Interconnect Master (L2M0) to the "HPS Peripheral Master Input IDs" table in HPS Peripheral Master Input IDs.

2020.01.13 Added new section Avoiding ACP Dependency Lockup

2019.06.14 Added details about arbitration behavior in the SCU when the ACP is not being used in the Implementation Details of the Snoop Control Unit section,

2016.10.28

• Added note to "AXI Master Conguration for ACP Access" section

• Added "Conguring AxCACHE[3:0] Sideband Signals" and "Conguring AxUser[4:0]

Sideband Signals" subsections to the "AXI Master Conguration for ACP Access" section

• Added note in the "Implementation Details" subsection of the "ACP ID Mapper" section.

2016.05.03 Maintenance release

2015.11.02

• Reordered "L2 Cache" subsections

• Renamed "ECC Support" L2 subsection to be "Single Event Upset Protection"

• Added "L2 Cache Parity" subsection in "L2 Cache" section

2015.05.04 Claried EMAC0 and EMAC1 ACP Mapper IDs in the "HPS Peripheral Master Input IDs" table in the "HPS Peripheral Master Input IDs" section.

2014.12.15

• Added bus transaction scenarios in the "Accelerator Coherency Port" section

• Added the "AxUSER and AxCACHE Attributes" subsection to the "Accelerator Coherency

Port" section

• Added the "Shared Requests on ACP" subsection to the "Accelerator Coherency Port"

section

• Added the "Conguration for ACP Use" subsection to the "Accelerator Coherency Port"

section

• Claried how to use xed mapping mode in the ACP ID Mapper

• Updated HPS Peripheral Master Input IDs table

• Added a note to the "Control of the AXI User Sideband Signals" subsection in the "ACP ID

Mapper" section.

• Added parity error handling information to the "L1 Caches" section and the "Cache

Controller Conguration" topic of the "L2 Cache" section.

2014.06.30

• Added Reset Section to Cortex-A9 Processor

• Updated HPS Peripheral Master Input IDs table

• Added ACP ID Mapper Address Map and Register Denitions

• Added information in ECC Support section regarding ECC errors

• Minor clarications regarding MPU description and module revision numbers

2014.02.28 Maintenance release

2013.12.30

Correct SDRAM region address in Arm Cortex-A9 MPCoreAddress Map

1.2 Minor updates.

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1.1 • Add description of the ACP ID mapper

• Consolidate redundant information

1.0 Initial release.

Cortex-A9 Microprocessor Unit Subsystem on page 10-1

Document

Version

Changes

2014.07.31 Updated the address map and register denitions.

2014.06.30 Added address map and register denitions.

2014.02.28 Maintenance release.

2013.12.30 Maintenance release.

1.2 Minor updates.

1.1 Added functional description, programming model, and address map and register denition sections.

1.0 Initial release.

CoreSight Debug and Trace on page 11-1

Document

Version

Changes

2020.02.28 In the Memory Protection section - Corrected the "Protection" eld denition in the "Fields for Rules in Memory Protection Table".

2018.07.17 Modied text to clarify that there is support for up to 4 Gb external memory device per chip select.

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2015.11.02

2015.05.04

2014.12.15

Changes

• Added information regarding calculation of ECC error byte address location from

erraddr register in "User Notication of ECC Errors" section

• Added information regarding bus response to memory protection transaction failure in

"Memory Protection" section

• Claried "Protection" row in "Fields for Rules in Memory Protection" table in the "Memory

Protection" section

• Claried protruledata.security column in "Rules in Memory Protection Table for Example

Conguration" table in the "Example of Conguration for TrustZone" section

• Added note about double-bit error functionality in "ECC Write Backs" subsection of

"ECC" section

• Added the "DDR Calibration" subsection under "DDR PHY" section

• Added the recommended sequence for writing or reading a rule in the "Memory

Protection" section.

• Added SDRAM Protection Access Flow Diagram to "Memory Protection" subsection in

the "Single-Port Controller Operation" section.

• Changed the "SDRAM Multi-Port Scheduling" section to "SDRAM Multi-Port Arbitration"

and added detailed information on how to use and program the priority and weighted arbitration scheme.

2014.6.30

• Added Port Mappings section.

• Added SDRAM Controller Memory Options section.

• Enhanced Example of Conguration for TrustZone section.

• Added SDRAM Controller address map and registers.

2013.12.30

• Added Generating a Preloader Image for HPS with EMIF section.

• Added Debugging HPS SDRAM in the Preloader section.

• Enhanced Simulation section.

1.1 Added address map and register denitions section.

1.0 Initial release.

SDRAM Controller Subsystem on page 12-1

Document

Version

Changes

2018.01.26 Updated "On-Chip RAM Initialization" section with steps to enable ECC.

2016.10.28 Maintenance release

2016.05.03 Maintenance release

2015.11.02 Maintenance release

2015.05.04 Maintenance release

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2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1 Added address map section

1.0 Initial release

On-Chip Memory on page 13-1

Document

Version

Changes

2018.01.26 Updated "ECC Enabling" section with steps to enable ECC.

2016.10.28 Added content about the local memory buer

2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

2016.05.03 Maintenance release

2015.11.02

• Moved "Interface Signals" section aer "NAND Flash Controller Block Diagram and

System Integration" section and renamed it to "NAND Flash Controller Signal Descrip‐ tion"

• Updated the Interrupt and DMA Enabling section to recommend reading back a register

to ensure clearing an interrupt status

• Specied the valid values for Burst Length in the Command-Data Pair 4 table

• Updated the description of dma_cmd_comp and added a RESERVED bit for intr_status0/1/

2/3 and intr_en0/1/2/3

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.07.31 Updated address map and register denitions.

2014.06.30 • Added address map and register denitions.

• Removed Command DMA section.

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 • Supports one 8-bit device

• Show additional supported block sizes

• Bad block marker handling

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1.1 Added programming model section.

1.0 Initial release

NAND Flash Controller on page 14-1

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Changes

2018.01.26 Added "Enabling ECC" section.

2017.12.27 Added 8-bit support for eMMC in the "Features of SD/MMC Controller" section. (FB320076)

2016.10.28

• Removed SPI support in tables in the Features section

• Added 8-bit support for eMMC for SD/MMC

2016.05.27 Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

2016.05.03 Maintenance release.

2015.11.02

• Moved "Interface Signals" section below "SD/MMC Controller Block Diagram and System

Integration" section and renamed to "SD/MMC Signal Description." Claried signals in this section.

• Added information that Card Detect is only supported on interfaces routed via the FPGA

fabric.

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.06.30 Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.1

• Added programming model section.

• Reorganized programming information.

• Added information about ECCs.

• Added pin listing.

• Updated clocks section.

1.0 Initial release.

SD/MMC Controller on page 15-1

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2020.09.03 Updated the denition for the QSPI register: indaddrtrig in the Quad SPI Flash Controller Address Map and Register Denitions section

2019.07.09

2019.06.14

Added a new section, Write Request, with WREN and RDSR information

Maintenance release

2018.01.26 Updated "Local Memory Buer" section with steps to enable ECC.

2016.10.28 Maintenance release

2016.05.27

• Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk;

and the external QSPI output clock, from sclk_out to qspi_clk.

• Added a link to the Supported Flash Devices for Cyclone V and Arria V SoC webpage.

• Re-worded information about disabling the watermark feature in the "Indirect Read

Operation" and "Indirect Write Operation" sections.

2016.05.03

• Added clarication for the SRAM indirect read and write size allocations.

• Updated the SRAM block on the "Quad SPI Flash Controller Block Diagram and System

Integration" gure.

2015.11.02

• Moved "Interface Signals" section below "Quad SPI Flash Controller Block Diagram and

System Integration"

• Better dened l4_mp_clk clock.

2015.05.04 Added information about clearing out the ECC before the feature is enabled

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30

Added address maps and register denitions

2014.02.28 Maintenance release

2013.12.30 Maintenance release

1.2 Minor updates.

1.1 Added block diagram and system integration, functional description, programming model, and address map and register denitions sections.

1.0 Initial release.

Quad SPI Flash Controller on page 16-1

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Changes

2018.01.26 Updated "Initializing and Clearing of Memory before Enabling ECC" section with steps to enable ECC.

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Changes

2016.10.28 Maintenance release

2016.05.03 Maintenance release

2015.11.02

• Updated link point to the HPS Address Map and Register Denitions

• Added information about the instruction fetch cache properties

• Added a description about the relationship between the GIC interrupt map and INTCLR

2015.05.04

• Added Synopsys* handshake rules.

2014.12.15 Maintenance release

2014.07.31 Updated address maps and register descriptions

2014.06.30 Added address maps and register denitions

2014.02.28

ECC updates

1.2 Maintenance release

1.1 Minor updates

1.0 Initial release

DMA Controller on page 17-1

Document

Version

Changes

2020.08.18 Updated EMAC HPS Interface Initialization to clarify how to verify RX PHY clocks aer bringing the Ethernet PHY out of reset.

2019.06.14 Claied the PCF bit description for encoding value 0x2 in the MAC_Frame_Filter register.

• Claried "Busy Bit" (gb bit of GMII_Address register) in Flow_Control register descrip‐

tion.

• Claried that ttc bit resides in the Operation_Mode Register (Register 6).

• Claried that the pcsancis and the pcslchgis bits of theInterrupt_Status register can

be ignored because they apply to TBI, RTBI, or SGMII interface only.

2016.10.28

• Note added into PHY Interface section

• Bit 16 updated Transmit Descriptor table

2016.05.03 Maintenance release.

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2015.11.02

2015.05.04

2014.12.15

Changes

• Added the following subsections in the "Layer 3 and Layer 4 Filters" section:

• Layer 3 and Layer 4 Filters Register Set

• Layer 3 Filtering

• Layer 4 Filtering

• Corrected IEEE 1588 timestamp resolution in the "EMAC Block Diagram and System

Integration" section and the "IEEE 1588-2002 Timestamps" section

• Added reset pulse width for rst_clk_tx_n_o and rst_clk_rx_n_o in the "FPGA EMAC

I/O signals" section

• Added subsections "Ordinary Clock," "Boundary Clock," "End-to-End Transparent Clock"

and "Peer-to-Peer Transparent Clock" in the "Clock Type" section

• Updated EMAC Block Diagram and System Integration section with new diagram and

information.

• Added Signal Descriptions section.

• Added EMAC Internal Interfaces section.

• Added TX FIFO and RX FIFO subsection to the Transmit and Receive Data FIFO Buers

section.

• Updated Descriptor Overview section to clarify support for only enhanced (alternate)

descriptors.

• Added Destination and Source Address Filtering Summary in Frame Filtering Section.

• Added Clock Structure sub-section to Clocks and Resets section

• Added System Level EMAC Conguration Registers section in Ethernet Programming Model

• Added EMAC Interface Initialization for FPGA GMII/MII Mode section in Ethernet

Programming Model

• Added EMAC Interface Initialization for RGMII/RMII Mode section in Ethernet Program‐

ming Model

• Corrected DMA Initialization and EMAC Initialization and Conguration titles to appear

on correct initialization information

• Removed duplicate programming information for DMA

• Added Taking the Ethernet MAC Out of Reset section.

2014.06.30

2014.02.28 ECC updates.

1.4 Maintenance release.

1.3

1.2 Updated the HPS boot and FPGA conguration sections.

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Updated EMAC to RGMII Interface table with EMAC Port names Updated EMAC to FPGA PHY Interface table with Signal names Updated EMAC to FPGA IEEE1588 Timestamp Interface with Signal names Added Address Map and Register Descriptions

• Expanded shared memory block table.

• Added CSEL tables.

• Additional minor updates.

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Arria® V Hard Processor System Technical Reference Manual Revision History

Ethernet Media Access Controller on page 18-1

1-15

Document

Version

Changes

2018.01.26 Added steps for enabling ECC.

2016.10.28 Maintenance release.

2016.05.03 Maintenance release.

2015.11.02 Renamed "ULPI PHY Interface" section to "USB 2.0 ULPI PHY Signal Description" and moved it aer the "USB OTG Controller Block Diagram and System Integration" section.

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added Taking the USB OTG Out of Reset section.

2014.07.31 Updated address map and register denitions.

2014.06.30 Added USB OTG Controller address map and register denitions.

2014.02.28 Maintenance release.

2013.12.30 Maintenance release.

1.2 • Described interrupt generation.

• Described soware initialization in host and device modes.

• Described soware operation in host and device modes.

• Simplied features list.

• Simplied hardware description.

1.1 Added information about ECCs.

1.0 Initial release.

USB 2.0 OTG Controller on page 19-1

Document

Version

Changes

2017.01.26 Corrected the support information for continuous data transfers in SPI Serial Format.

2016.10.28 Maintenance release.

2016.05.03 Maintenance release.

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Document

Version

2015.11.02

• Renamed "Interface Pins" section to "Interface to HPS I/O" and moved it under the "SPI

Controller Signal Description" section

• Moved "FPGA Routing" section under "SPI Controller Signal Description" section

• Added Multi-Master mode to "Features of the SPI Controller" section

• Updated "RXD Sample Delay" section

• Updated "SPI Slave" section

• Updated "Glue Logic for Master Port ss_in_n" section

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added Taking the SPI Out of Reset section.

2014.06.30

• "Glue Logic for Master Port ss_in_n" section added

• Interface Pins topic added

• FPGA Routing topic added

• Added address aap and register descriptions

2014.02.28 Maintenance release.

2013.12.30

Minor formatting updates.

Changes

1.2 Minor updates.

1.1 Added programming model, address map and register denitions, clocks, and reset sections.

1.0 Initial release.

SPI Controller on page 20-1

Document Version Changes

2015.05.04

• Added Impact of SCL Rise Time and Fall Time On Generated SCL gure to "Clock Synchronization" section

• Updated "Minimum High and Low Counts" section

2014.12.15

• Maintenance release.

• Added Taking the I2C Out of Reset section.

2014.06.30

HPS I2C Signals for FPGA Routing table updated I2C interface in FPGA Fabric diagram added Added Address Map and Register Descriptions

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2014.02.28 Maintenance release.

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Document Version Changes

1-17

2013.12.30

Added HPS I2c Signals for FPGA routing to "Interface Pins" section.

1.2 Minor updates.

1.1 Added programming model, address map and register denitions, clocks, reset, and interface pins sections.

1.0 Initial release.

I2C Controller on page 21-1

Document

Version

Changes

2015.11.02 Renamed Interface Pins section to HPS I/O Pins and moved this section and FPGA Routing under UART Controller Signal Description

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added Taking the UART Out of Reset section.

2014.06.30

• UART(RS232) Serial Protocol topic added

• Interrupts section updated

• Updated Interrupt type table

• Added address map and register descriptions

2014.02.28 Maintenance release

2013.12.30

Minor formatting updates.

1.2 Minor updates.

1.1 Added programming model, address map and register denitions, and reset sections.

1.0 Initial release.

UART Controller on page 22-1

Document

Version

Changes

2020.09.03 Added information about the state of HPS GPIO during cold reset in the Taking the GPIO Interface Out of Reset section.

2019.06.14 Added GPIO State During Reset section.

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Arria® V Hard Processor System Technical Reference Manual Revision History

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Document

Version

2014.12.15

• Maintenance release.

• Added Taking the GPIO Out of Reset section.

2014.06.30

2014.02.28

Added Address Map and Register Descriptions

Updated content in sections:

• Features of the GPIO Interface

• GPIO Interface Block Diagram and System Integration

• Debounce Operation

2013.12.30

Minor formatting updates Updated GPIO interface block diagram and GPIO interface pin table

1.2 Minor updates.

1.1 Added programming model section.

1.0 Initial release.

Changes

General-Purpose I/O Interface on page 23-1

Document

Version

2014.06.30

• "FPGA Interface" section added

Changes

• Added address map and register descriptions

2014.02.28 Maintenance release.

2013.12.30

Minor formatting updates.

1.2 Minor updates.

1.1 Added programming model and address map and register denitions sections.

1.0 Initial release.

Timer on page 24-1

Document

Version

Changes

2015.11.02 Added note to "Watchdog Timer Counter" section.

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Arria® V Hard Processor System Technical Reference Manual Revision History

1-19

Document

Version

Changes

2015.05.04 Maintenance release.

2014.12.15

• Maintenance release.

• Added "Taking the Watchdog Timer Out of Reset" section.

2014.06.30

• "FPGA Interface" section added

• Added address map and register descriptions

2014.02.28 Maintenance release.

2013.12.30

Minor formatting updates.

1.2 Minor updates.

1.1 Added programming model and address map and register denitions sections.

1.0 Initial release.

Watchdog Timer

on page 25-1

Document

Version

2013.12.30

Maintenance release

1.0 Maintenance release.

0.1 Preliminary dra.

Introduction to the HPS Component on page 26-1

Document

Version

2015.11.02 Updated Sections:

• Conguring Peripherals

• Peripheral Signals Routed to FPGA

2015.05.04 Maintenance release.

2014.12.15 Maintenance release.

2014.06.30

• Updated the "Instantiating the HPS Component" section.

• Added the "Using Unassigned I/O as Loan I/O" section.

• Removed reference to CAN interrupts from the "Interrupts" section.

Changes

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Arria® V Hard Processor System Technical Reference Manual Revision History

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Document

Version

2014.02.28

• Add interfaces to tables

• Add parameters to General Parameters table

1.2 Maintenance release.

1.1 • Added debug interfaces

• Added boot options

• Corrected slave address width

• Corrected SDRAM interface widths

• Added TPIU peripheral

• Added .sdc le generation

• Added .tcl script for memory assignments

1.0 Initial release.

0.1 Preliminary dra.

Changes

Instantiating the HPS Component

Document

Version

2015.05.04

• Added note to FGPA-to-HPS SDRAM Interface section

• Added note to User Clocks section

2014.12.15

2014.06.30

User Clock 2 has been removed

Added address map and register descriptions

on page 27-1

Changes

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1-21

Document

Version

2014.02.28

Added sections:

• Peripheral FPGA Clocks

• Peripheral Reset Interfaces

• Boot from FPGA Interface

• Input-only General Purpose Interfaces Removed section:

• General Purpose Interfaces Updated sections:

• Trace Port Interface Unit

• Peripheral Signal Interfaces

• FPGA-to-HPS Interrupts

2013.12.30

Minor formatting issues

1.1 • Added debug interfaces.

• Updated HPS-to-FPGA reset interface names.

• Updated HPS external reset source interface names.

• Removed DMA peripheral interface clocks.

• Referred to Address Span Extender.

Changes

1.0 Initial release.

0.1 Preliminary dra.

HPS Component Interfaces

Document

Version

on page 28-1

Changes

2016.05.03 Removed references to FPGA to HPS SDRAM simulation.

2015.11.02 Maintenance release

2015.05.04 Maintenance release

2014.12.15 Maintenance release

2014.11.14

• Updated the "Simulation Flows" section.

• Updated the "Generating HPS Simulation Model in Platform Designer (Standard)"

section.

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Arria® V Hard Processor System Technical Reference Manual Revision History

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Document

Version

2014.02.28

Added new sections:

Changes

• Boot from FPGA Interface

• General Purpose Input (GPI) Interface Updated content in sections:

• Specifying HPS Simulation Model in Platform Designer (Standard)

• Running HPS RTL Simulation

2013.12.30 Maintenance release

1.1 • Added debug APB*, STM hardware event, FPGA cross trigger, FPGA trace port interfaces.

• Added support for post-t simulation.

• Updated some API function names.

• Removed DMA peripheral clock.

1.0 Initial release.

0.1 Preliminary dra.

Simulating the HPS Component

Document

Version

on page 29-1

Changes

2020.09.03 Added information about where the HPS IO Conguration is contained in the Typical Preloader Boot Flow section.

2018.07.17

• Removed I/O State subsection in I/O Conguration section. is content only applies to

Intel® Arria® 10 HPS.

• Added state of dedicated I/O at power up in the I/O Conguration section.

2016.05.27 Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk; and the external QSPI output clock, from sclk_out to qspi_clk.

2016.05.03

• Updated SD/MMC device clock values in the CSEL Settings for SD/MMC Controller

section.

• Included read capture delay information in the Quad SPI Flash Delay Conguration

section.

• Added bus mode to the "SD/MMC Controller Default Settings" table in the Default

Settings of the SD/MMC Controller section.

• Changed the name of the internal QSPI reference clock from qspi_clk to qspi_ref_clk;

and the external QSPI output clock, from sclk_out to qspi_clk.

2015.11.02 Maintenance Release

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1-23

Document

Version

2015.05.04

2014.12.15

2014.06.30

Changes

• Added "Boot Source I/O Mapping" section

• Removed "*2" multiplier in CSEL3 column of the table in "CSEL Pin Settings for the SD/

MMC Controller" section.

• Corrected frequency values for Device frequency and controller clock in the "NAND

Controller CSEL Pin Settings" table in the "CSEL Settings for the NAND Controller" section

• Removed reference to Mode Reset Command in the "Quad SPI Flash Devices"

• Claried "Shared Memory Locations" in "Shared Memory" section

• Added the following sections:

• "Boot Overview"

• "FPGA Conguration Overview"

• "Booting and Conguration Options"

• "Boot Denitions" section with subsections on "Reset", "Boot ROM", "Boot Source I/O Pins", "Flash Memory Devices", "Clock Select", "I/O Conguration", "L4 Watchdog 0 Timer", "Preloader", and "U-Boot Loader".

• Removed "Shared Memory" section

Maintenance release

2014.02.28 Correction to "Leading the Preloader" section

2013.12.30

• Updated gures in the Booting and Conguration Introduction section.

• Updated the Rest and Boot ROM sections.

• Updated the Shared Memory Block table.

• Updated register names in the Full Conguration section.

1.3 • Expanded shared memory block table.

• Added CLKSEL tables.

• Additional minor updates.

1.2 Updated the HPS boot and FPGA conguration sections.

1.1 • Updated the HPS boot section.

• Added information about the ash devices used for HPS boot.

• Added information about the FPGA conguration mode.

1.0 Initial release.

Booting and Conguration on page 30-1

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Altera SoC Device

HPS Portion

Flash

Controllers

SDRAM Controller

Subsystem

Cortex-A9 MPU Subsystem

On-Chip

Memories

Support

Peripherals

PLLs

Interface

Peripherals

Debug

HPS-FPGA Interfaces

Control

Block

User

I/O

HSSI

Transceivers

FPGA Fabric

(LUTs, RAMs, Multipliers & Routing)

PLLs

Hard

PCIe

Hard Memory

Controllers

FPGA Portion

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Introduction to the Hard Processor System

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e Arria V system-on-a-chip (SoC) is composed of two distinct portions- a dual-core Arm Cortex-A9 hard processor system (HPS) and an FPGA. e HPS architecture integrates a wide set of peripherals that reduce board size and increase performance within a system.

e SoC features the FPGA I/O, which is I/O pins dedicated to the FPGA fabric.

Figure 2-1: Intel SoC Device Block Diagram

Blocks connected to device pins have symbols (square with an X) adjacent to them in the gure.

e HPS consists of the following types of modules:

• Microprocessor unit (MPU) subsystem with a dual Arm Cortex-A9 MPCore processor

• Flash memory controllers

• SDRAM controller subsystem

• System interconnect

• On-chip memories

• Support peripherals

• Interface peripherals

• Debug components

• Phase-locked loops (PLLs)

ISO 9001:2015 Registered

Page 39

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Introduction to the Hard Processor System

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e HPS incorporates third-party intellectual property (IP) from several vendors. e dual-processor HPS supports symmetric (SMP) and asymmetric (AMP) multiprocessing. e FPGA portion of the device contains:

• FPGA fabric

• Control block (CB)

• PLLs

• High-speed serial interface (HSSI) transceivers, depending on the device variant

• Hard PCI Express® (PCI-e) controllers

• Hard memory controllers e HPS and FPGA communicate with each other through bus interfaces that bridge the two distinct

portions. On a power-on reset, the HPS can boot from multiple sources, including the FPGA fabric and external ash. e FPGA can be congured through the HPS or an externally supported device.

e HPS and FPGA portions of the device each have their own pins. Pins are not freely shared between the HPS and the FPGA fabric. e HPS I/O pins are congured by boot soware executed by the MPU in the HPS. Soware executing on the HPS accesses control registers in the system manager to assign HPS I/O pins to the available HPS modules. e FPGA I/O pins are congured by an FPGA conguration image through the HPS or any external source supported by the device.

e MPU subsystem can boot from ash devices connected to the HPS pins. When the FPGA portion is congured by an external source, the MPU subsystem can boot from ash memory devices available to the

FPGA portion of the device. e HPS and FPGA portions of the device have separate external power supplies and independently

power on. You can power on the HPS without powering on the FPGA portion of the device. However, to power on the FPGA portion, the HPS must already be on or powered at the same time as the FPGA portion. You can also turn o the FPGA portion of the device while leaving the HPS power on.

Table 2-1: Valid SoC Power Modes

HPS FPGA Valid?

O O Yes O On No

On O Yes On On Yes

Related Information

• Booting and Conguration on page 30-1

• Arria V Device Datasheet

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Features of the HPS

e main modules of the HPS are:

• MPU subsystem featuring a dual-core Arm Cortex-A9 MPCore processor

• General-purpose direct memory access (DMA) controller

• Two Ethernet media access controllers (EMACs)

• Two USB 2.0 on-the-go (OTG) controllers

• NAND ash controller

• Quad SPI ash controller

• Secure digital/multimedia card (SD/MMC) controller

• Two serial peripheral interface (SPI) master controllers

• Two SPI slave controllers

• Four inter-integrated circuit (I2C) controllers

• 64 KB on-chip RAM

• 64 KB on-chip boot ROM

• Two UARTs

• Four timers

• Two watchdog timers

• ree general-purpose I/O (GPIO) interfaces

• Arm CoreSight debug components:

(1)

Features of the HPS

2-3

• Debug access port (DAP)

• Trace port interface unit (TPIU)

• System trace macrocell (STM)

• Program trace macrocell (PTM)

• Embedded trace router (ETR)

• Embedded cross trigger (ECT)

• System manager

• Clock manager

• Reset manager

• Scan manager

• FPGA manager

• SDRAM controller subsystem

(1)

Two of the four I2Cs, provide support for general purpose.

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DAP

ETR

SD/MMC

EMAC

(2)

USB OTG

(2)

NAND

Flash

Timer

(4)

Watchdog

Timer

(2)

UART

(2)

GPIO

(3)

SPI (4)

Clock

Manager

Reset

Manager

I C (4)

Scan

Manager

System

Manager

L4, 32-Bit Bus

32-Bit

L3 Interconnect

(NIC-301)

L3 Master Peripheral

Switch

32-Bit

64-Bit

32-Bit

64-Bit

32-Bit

64-Bit

L3 Slave Peripheral Switch

ACP

CPU0 CPU1

SCU

Arm Cortex-A9

MPCore

MPU Subsystem

ACP ID

Mapper

STM

Boot ROM

On-Chip RAM

DMA

Quad

SPI

Flash

FPGA

Manager

FPGA-to-HPS

Bridge

HPS-to-FPGA

Bridge

Lightweight

HPS-to-FPGA Bridge

L4, 32-Bit Bus

32-Bit AXI

32-Bit 64-Bit AXI 64-Bit AXI

L3 Main

Switch

FPGA Portion

Control

Block

Masters Slaves

Slaves

32-, 64-, 128-Bit AXI 32-, 64-, 128-Bit AXI 32-Bit AXI

1 - 6

Masters

FPGA to HPS HPS to FPGA Lightweight HPS to FPGA

32-Bit

Cache

SDRAM Controller Subsystem

Altera PHY Interface

DDR PHY

SDRAM Controller

Single-Port Memory Controller

HPS I/O Pins

External Memory

2-4

HPS Block Diagram and System Integration

HPS Block Diagram

Figure 2-2: HPS Block Diagram

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Cortex-A9 MPCore

e MPU subsystem provides the following functionality:

• Arm Cortex-A9 MPCore

• Two Arm Cortex-A9 processors

• NEON™ single instruction, multiple data (SIMD) coprocessor and vector oating-point v3 (VFPv3)

• Snoop control unit (SCU) to ensure coherency

• Accelerator coherency port (ACP) that accepts coherency memory access requests

• Interrupt controller

• One general-purpose timer and one watchdog timer per processor

• Debug and trace features

• 32 KB instruction and 32 KB data level 1 (L1) caches per processor

• Memory management unit (MMU) per processor

• Arm L2-310 level 2 (L2) cache

• Shared 512 KB L2 cache

• ACP ID mapper

• Maps the 12-bit ID from the level 3 (L3) interconnect to the 3-bit ID supported by the ACP

per processor

Cortex-A9 MPCore

2-5

A programmable address lter in the L2 cache controls which portions of the 32-bit physical address space can be accessed by each master.

Related Information

HPS Block Diagram on page 2-4

HPS Interfaces

e Arria V device family provides multiple communication channels to the HPS.

HPS–FPGA Memory-Mapped Interfaces

e HPS–FPGA memory-mapped interfaces provide the major communication channels between the HPS and the FPGA fabric. e HPS–FPGA memory-mapped interfaces include:

• FPGA–to–HPS bridge—a high–performance bus with a congurable data width of 32, 64, or 128 bits, allowing the FPGA fabric to master transactions to the slaves in the HPS. is interface allows the FPGA fabric to have full visibility into the HPS address space. is interface also provides access to the coherent memory location

• HPS–to–FPGA bridge—a high–performance interface with a congurable data width of 32, 64, or 128 bits, allowing the HPS to master transactions to slaves in the FPGA fabric

• Lightweight HPS–to–FPGA bridge—an interface with a 32–bit xed data width, allowing the HPS to master transactions to slaves in the FPGA fabric. is lower–bandwidth interface is useful for accessing the control and status registers of so peripherals

Related Information

HPS-FPGA Bridges on page 9-1

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Other HPS Interfaces

• TPIU trace—sends trace data created in the HPS to the FPGA fabric

• FPGA System Trace Macrocell (STM) —an interface that allows the FPGA fabric to send hardware events to be stored in the HPS trace data

• FPGA cross–trigger—an interface that allows the CoreSight trigger system to send triggers to IP cores in the FPGA, and vise versa

• DMA peripheral interface—multiple peripheral–request channels

• FPGA manager interface—signals that communicate with the FPGA fabric for boot and conguration

• Interrupts—allow so IP cores to supply interrupts directly to the MPU interrupt controller

• MPU standby and events—signals that notify the FPGA fabric that the MPU is in standby mode and signals that wake up Cortex-A9 processors from a wait for event (WFE) state

• HPS debug interface – an interface that allows the HPS debug control domain (debug APB) to extend into FPGA

Other HPS–FPGA communications channels:

• FPGA clocks and resets

• HPS–to–FPGA JTAG—allows the HPS to master the FPGA JTAG chain

System Interconnect

e system interconnect consists of the main L3 interconnect and level 4 (L4) buses. e L3 interconnect is an Arm NIC-301 module composed of the following switches:

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• L3 main switch

• Connects the master, slaves, and other subswitches

• Provides 64-bit switching capabilities

• L3 master peripheral switch

• Connects master ports of peripherals with integrated DMA controllers to the L3 main switch

• L3 slave peripheral switch

• Connects slave ports of peripherals to the L3 main switch

Related Information

System Interconnect on page 8-1

SDRAM Controller Subsystem

HPS and FPGA fabric masters have access to the SDRAM controller subsystem. e SDRAM controller subsystem implements the following high-level features:

• Support for double data rate 2 (DDR2), DDR3, and low-power double data rate 2 (LPDDR2) devices

• Error correction code (ECC) support, including calculation, single-bit error correction and write-back, and error counters

• Fully-programmable timing parameter support for all JEDEC-specied timing parameters

• All ports support memory protection and mutual accesses

• FPGA fabric interface with up to six ports that can be combined for a data width up to 256-bits wide using Avalon-MM and AXI interfaces.

e SDRAM controller subsystem is composed of the SDRAM controller, DDR PHY, control and status registers and their associated interfaces.

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SDRAM Controller

Related Information

SDRAM Controller Subsystem on page 12-1

SDRAM Controller

e SDRAM controller contains a multiport front end (MPFE) that accepts requests from HPS masters and from so logic in the FPGA fabric through the FPGA-to-HPS SDRAM interface.

e SDRAM controller oers the following features:

• Up to 4 GB address range

• 8-, 16-, and 32-bit data widths

• Optional ECC support

• Low-voltage 1.35V DDR3L and 1.2V DDR3U support

• Full memory device power management support

• Two chip selects (DDR2 and DDR3)

e SDRAM controller provides the following features to maximize memory performance:

• Command reordering (look-ahead bank management)

• Data reordering (out of order transactions)

• Priority arbitration and decit round-robin arbitration for ports with the same priority

• High-priority bypass for latency sensitive trac

2-7

Related Information

SDRAM Controller Subsystem on page 12-1

DDR PHY

e DDR PHY interfaces the single port memory controller to the HPS memory I/O.

Related Information

SDRAM Controller Subsystem on page 12-1

On-Chip Memory

On-Chip RAM

e on-chip RAM oers the following features:

• 64 KB size

• 64-bit slave interface

• High performance for all burst lengths

Related Information

On-Chip Memory on page 13-1

Boot ROM

e boot ROM oers the following features:

• 64 KB size

• Contains the code required to support HPS boot from cold or warm reset

• Used exclusively for booting the HPS

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Flash Memory Controllers

Related Information

• On-Chip Memory on page 13-1

• Booting and Conguration on page 30-1

Flash Memory Controllers

NAND Flash Controller

e NAND ash controller is based on the Cadence® Design IP® NAND Flash Memory Controller and oers the following functionality and features:

• Supports one x8 NAND ash device

• Supports Open NAND Flash Interface (ONFI) 1.0

• Supports NAND ash memories from Hynix, Samsung, Toshiba, Micron, and ST Micro

• Supports programmable 512 byte (4-, 8-, or 16-bit correction) or 1024 byte (24-bit correction) ECC sector size

• Supports pipeline read-ahead and write commands for enhanced read/write throughput

• Supports devices with 32, 64, 128, 256, 384, or 512 pages per block

• Supports multiplane devices

• Supports page sizes of 512 bytes, 2 kilobytes (KB), 4 KB, or 8 KB

• Supports single-level cell (SLC) and multi-level cell (MLC) devices with programmable correction capabilities

• Provides internal DMA

• Provides programmable access timing

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Related Information

NAND Flash Controller on page 14-1

Quad SPI Flash Controller

e quad SPI ash controller is based on the Cadence Quad SPI Flash Controller and oers the following features:

• Supports SPIx1, SPIx2, or SPIx4 (Quad SPI) serial NOR ash devices

• Supports direct access and indirect access modes

• Supports single, dual, and quad I/O instructions

• Support up to four chip selects

• Programmable write-protected regions

• Programmable delays between transactions

• Programmable device sizes

• Support eXecute-In-Place (XIP) mode

• Programmable baud rate generator to generate device clocks

Related Information

Quad SPI Flash Controller on page 16-1

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SD/MMC Controller

e Secure Digital (SD), Multimedia Card (MMC), (SD/MMC) and CE-ATA host controller is based on the Synopsys DesignWare* Mobile Storage Host controller and oers the following features:

• Integrated descriptor-based DMA

• Supports CE-ATA digital protocol commands

• Supports single card

• Single data rate (SDR) mode only

• Programmable card width: 1-, 4-, and 8-bit

• Programmable card types: SD, SDIO, or MMC

• Up to 64 KB programmable block size

• Supports the following standards and card types:

• Supports various types of multimedia cards, MMC version 4.41

• Supports embedded MMC (eMMC) version 4.41

• SD, including eSD—version 3.0

(2)

• SDIO, including embedded SDIO (eSDIO)—version 3.0

• CE-ATA—version 1.1

• MMC: 1-bit data bus

• Reduced-size MMC (RSMMC): 1-bit and 4-bit data bus

• MMCMobile: 1-bit data bus

• MMCPlus: 1-bit, 4-bit, and 8-bit data bus

• Default speed and high speed

(5)

(3)

(4)

SD/MMC Controller

2-9

• 1-bit, 4-bit and 8-bit data bus

Note:

For an inclusive list of the programmable card types and versions supported, refer to the SD/MMC Controller chapter.

Related Information

SD/MMC Controller on page 15-1

Support Peripherals

Clock Manager

e clock manager oers the following features:

• Manages clocks for HPS

• Supports dynamic clock tuning

Related Information

Clock Manager on page 3-1

(2)

Does not support SDR50, SDR104, and DDR50 modes.

(3)

Does not support SDR50, SDR104, and DDR50 modes.

(4)

Does not support DDR mode.

(5)

Does not support DDR mode.

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Reset Manager

e reset manager manages both hardware and soware reset sources in the HPS. Reset status is also provided. Reset types include cold, warm, and debug. Reset behavior depends on the type.

Related Information

Reset Manager on page 4-1

System Manager

e system manager controls system functions and modules that need external control signals. e system manager oers the following features:

• ECC monitoring and control

• Low-level control of peripheral features not accessible through the control and status registers (CSRs)

• Freeze controller that places I/O elements into a safe state for conguration

Related Information

System Manager on page 6-1

Scan Manager

e scan manager is used to congure and manage HPS I/O pins and to communicate with the FPGA JTAG.

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Related Information

Scan Manager on page 7-1

Timers

e four timers are based on the Synopsys DesignWare APB Timer peripheral and oer the following features:

• 32-bit timer resolution

• Free-running timer mode

• Supports a time-out period of up to 43 seconds when the timer clock frequency is 100 MHz

• Interrupt generation

Related Information

Timer on page 24-1

Watchdog Timers

e two watchdog timers are based on the Synopsys DesignWare APB Watchdog Timer peripheral and oer the following features:

• 32-bit timer resolution

• Interrupt request

• Reset request

• Programmable time-out period up to approximately 86 seconds (assuming a 50 MHz input clock frequency)

Related Information

Watchdog Timer on page 25-1

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DMA Controller

FPGA Manager

DMA Controller

2-11

e DMA controller provides high-bandwidth data transfers for modules without integrated DMA controllers. e DMA controller is based on the Arm Corelink* DMA Controller (DMA-330) and oers the following features:

• Micro-coded to support exible transfer types

• Memory-to-memory

• Memory-to-peripheral

• Peripheral-to-memory

• Scatter-gather

• Supports up to eight channels

• Supports ow control with 31 peripheral handshake interfaces

• Soware can schedule up to 16 outstanding read and 16 outstanding write instructions

• Supports nine interrupt lines: one for DMA thread abort and eight for external events

Related Information

DMA Controller on page 17-1

e FPGA manager oers the following features:

• Manages conguration of the FPGA portion of the device

• 32-bit fast passive parallel conguration interface to the FPGA CSS block

• Partial reconguration

• Compressed FPGA conguration images

• Advanced Encryption Standard (AES) encrypted FPGA conguration images

• Monitors conguration-related signals in FPGA

• Provides 32 general-purpose inputs and 32 general-purpose outputs to the FPGA fabric

Related Information

FPGA Manager on page 5-1

Interface Peripherals

EMACs

e two EMACs are based on the Synopsys DesignWare 3504-0 Universal 10/100/1000 Ethernet MAC and oer the following features:

• Supports 10, 100, and 1000 Mbps standard

• Supports RGMII external PHY interface

• Media independent interface (MII)

• Gigabit media independent interface (GMII)

• Reduced gigabit media independent interface (RGMII)

• Serial gigabit media independent interface (SGMII) with additional external conversion logic

• Provides full GMII interface when using FPGA interface

• Integrated DMA controller

• Supports IEEE 1588-2002 and IEEE 1588-2008 standards for precision networked clock synchroniza‐ tion

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USB Controllers

• IEEE 802.3-az, version D2.0 of Energy Ecient Ethernet

• Supports IEEE 802.1Q VLAN tag detection for reception frames

• Supports a variety of address ltering modes

• Management of PHY through Management data input/output (MDIO) interface or optionally, I2C interface

Related Information

Ethernet Media Access Controller on page 18-1

USB Controllers

e HPS provides two USB 2.0 Hi-Speed On-the-Go (OTG) controllers from Synopsys DesignWare. e USB controller signals cannot be routed to the FPGA like those of other peripherals; instead they are routed to the dedicated I/O.

Each of the USB controllers oers the following features:

• Complies with the following specications:

• USB OTG Revision 1.3

• USB OTG Revision 2.0

• Embedded Host Supplement to the USB Revision 2.0 Specication

• Supports soware-congurable modes of operation between OTG 1.3 and OTG 2.0

• Supports all USB 2.0 speeds:

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• High speed (HS, 480-Mbps)

• Full speed (FS, 12-Mbps)

• Low speed (LS, 1.5-Mbps)

In host mode, all speeds are supported; however, in device mode, only high speed and full

Note:

speed are supported.

• Local buering with Error Correction Code (ECC) support

e USB 2.0 OTG controller does not support the following interface standards:

Note:

• Enhanced Host Controller Interface (EHCI)

• Open Host Controller Interface (OHCI)

• Universal Host Controller Interface (UHCI)

• Supports USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) PHYs (SDR mode only)

• Supports up to 16 bidirectional endpoints, including control endpoint 0

Only seven periodic device IN endpoints are supported.

Note:

• Supports up to 16 host channels

In host mode, when the number of device endpoints is greater than the number of host

Note:

channels, soware can reprogram the channels to support up to 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints.

• Supports generic root hub

• Supports automatic ping capability

Related Information

• USB 2.0 OTG Controller on page 19-1

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I2C Controllers

UARTs

I2C Controllers

2-13

• Universal Serial Bus (USB) website Additional information is available in the On e Go and Embedded Host Supplement to the USB Revision 2.0 Specication, which you can download from the USB Implementers Forum website.

e four I2C controllers are based on Synopsys DesignWare APB I2C controller which oer the following features:

• Two controllers support I2C management interfaces for use by the EMAC controllers

• Support both 100 KBps and 400 KBps modes

• Support both 7-bit and 10-bit addressing modes

• Support master and slave operating mode

• Direct access for host processor

• DMA controller may be used for large transfers

Related Information

I2C Controller on page 21-1

e HPS provides two UART controllers to provide asynchronous serial communications. e two UART modules are based on Synopsys DesignWare APB Universal Asynchronous Receiver/ Transmitter peripheral and oer the following features:

• 16550-compatible UART

• Support automatic ow control as specied in 16750 standard

• Programmable baud rate up to 6.25 MBaud (with 100MHz reference clock)

• Direct access for host processor

• DMA controller may be used for large transfers

• 128-byte transmit and receive FIFO buers

Related Information

UART Controller on page 22-1

SPI Master Controllers

e two SPI master controllers are based on Synopsys DesignWare Synchronous Serial Interface (SSI) controller and oer the following features:

• Choice of Motorola* SPI, Texas Instruments* Synchronous Serial Protocol or National Semiconductor Microwire protocol

• Programmable data frame size from 4 bits to 16 bits

• Supports full- and half-duplex modes

• Supports up to four chip selects

• Direct access for host processor

• DMA controller may be used for large transfers

• Programmable master serial bit rate

• Support for rxd sample delay

• Transmit and receive FIFO buers are 256 words deep

Related Information

SPI Controller on page 20-1

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2-14

SPI Slave Controllers

e two SPI slave controllers are based on Synopsys DesignWare Synchronous Serial Interface (SSI) controller and oer the following features:

• Programmable data frame size from 4 bits to 16 bits

• Supports full- and half-duplex moces

• Direct access for host processor

• DMA controller may be used for large transfers

• Transmit and receive FIFO buers are 256 words deep

Related Information

SPI Controller on page 20-1

GPIO Interfaces

e HPS provides three GPIO interfaces that are based on Synopsys DesignWare APB General Purpose Programming I/O peripheral and oer the following features:

• Supports digital de-bounce

• Congurable interrupt mode

• Supports up to 71 I/O pins and 14 input-only pins, based on device variant

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Related Information

General-Purpose I/O Interface on page 23-1

CoreSight Debug and Trace

e CoreSight debug and trace system oers the following features:

• Real-time program ow instruction trace through a separate PTM for each processor

• Host debugger JTAG interface

• Connections for cross-trigger and STM-to-FPGA interfaces, which enable so IP cores to generate of triggers and system trace messages

• Custom message injection through STM into trace stream for delivery to host debugger

• Capability to route trace data to any slave accessible to the ETR master, which is connected to the level 3 (L3) interconnect

Related Information

CoreSight Debug and Trace on page 11-1

Endian Support

e HPS is natively a little–endian system. All HPS slaves are little endian. e processor masters are soware congurable to interpret data as little endian, big endian, or byte–

invariant (BE8). All other masters, including the USB 2.0 interface, are little endian. Registers in the MPU and L2 cache are little endian regardless of the endian mode of the CPUs.

Note:

e FPGA–to–HPS, HPS–to–FPGA, FPGA–to–SDRAM, and lightweight HPS–to–FPGA interfaces are little endian.

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Intel strongly recommends that you only use little endian.

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0 GB

1 GB

2 GB

3 GB

4 GB

ACP

Window

SDRAM Region

SDRAM

Window

FPGA

Slaves

Region

Lightweight

FPGA

Slaves

MPU

FPGA-to-SDRAM

FPGA

Slaves

Region

Peripheral Region

SDRAM

Window

RAM / SDRAM

Boot Region

(ROM/RAM/SDRAM)

Peripheral Region

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If a processor is set to BE8 mode, soware must convert endianness for accesses to peripherals and DMA linked lists in memory. e processor provides instructions to swap byte lanes for various sizes of data.

e Arm Cortex-A9 MPU supports a single instruction to change the endianness of the processor and provides the REV and REV16 instructions to swap the endianness of bytes or half–words respectively. e MMU page tables are soware congurable to be organized as little–endian or BE8.

e Arm DMA controller is soware congurable to perform byte lane swapping during a transfer.

Introduction to the Hard Processor System Address Map

e address map species the addresses of slaves, such as memory and peripherals, as viewed by the MPU and other masters. e HPS has multiple address spaces, dened in the following section.

Related Information

System Interconnect on page 8-1

HPS Address Spaces

e following table shows the HPS address spaces and their sizes. Address spaces are divided into one or more nonoverlapping regions. For example, the MPU address space

has the peripheral, FPGA slaves, SDRAM window, and boot regions.

2-15

Figure 2-3: HPS Address Space Relationships

e following gure shows the relationships between the HPS address spaces. e gure is not to scale.

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2-16

SDRAM Address Space

e window regions provide access to other address spaces. e thin black arrows indicate which address space is accessed by a window region (arrows point to accessed address space). For example, accesses to the ACP window in the L3 address space map to a 1 GB region of the MPU address space.

e SDRAM window in the MPU address space can grow and shrink at the top and bottom (short, blue vertical arrows) at the expense of the FPGA slaves and boot regions. For specic details, refer to “MPU Address Space”.

e ACP window can be mapped to any 1 GB region in the MPU address space (blue vertical bidirectional arrow), on gigabyte-aligned boundaries.

e following table shows the base address and size of each region that is common to the L3 and MPU address spaces.

Table 2-2: Common Address Space Regions

Region Name Base Address Size

FPGA slaves 0xC0000000 960 MB

Peripheral 0xFC000000 64 MB

Lightweight FPGA slaves 0xFF200000 2 MB

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SDRAM Address Space

e SDRAM address space is up to 4 GB. e entire address space can be accessed through the FPGA-to-HPS SDRAM interface from the FPGA fabric. e total amount of SDRAM addressable from the other address spaces can be congured at runtime.

Related Information

System Interconnect on page 8-1

For more information about how to congure SDRAM address space.

MPU Address Space

e MPU address space is 4 GB and applies to addresses generated inside the MPU. e MPU address space contains the following regions:

• e SDRAM window region provides access to a large, congurable portion of the 4 GB SDRAM address space.

e address ltering start and end registers in the L2 cache controller dene the SDRAM window boundaries. e boundaries are megabyte-aligned. Addresses within the boundaries route to the SDRAM master. Addresses outside the boundaries route to the system interconnect master.

Related Information

• HPS Address Spaces on page 2-15 For more information, refer to the "HPS Address Space Relationships" table.

• System Interconnect on page 8-1 For more information regarding SDRAM address mapping, refer to the System Interconnect chapter.

• Cortex-A9 Microprocessor Unit Subsystem on page 10-1

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• HPS Address Spaces on page 2-15

L3 Address Space

e L3 address space is 4 GB and applies to all L3 masters except the MPU. e L3 address space has more conguration options than the other address spaces.

Related Information

System Interconnect on page 8-1

For more information about conguring the L3 address space, refer to the System Interconnect chapter.

HPS Peripheral Region Address Map

Each peripheral slave interface has a dedicated address range in the peripheral region. e table below lists the base address and address range size for each slave.

Table 2-3: Peripheral Region Address Map

Slave Identier Description Base Address Size

STM Space Trace Macrocell 0xFC000000 48 MB

L3 Address Space

2-17

DAP Debug Access Port 0xFF000000 2 MB

LWFPGASLAVES FPGA slaves accessed with

0xFF200000 2 MB lightweight HPS-to-FPGA bridge

LWHPS2FPGAREGS Lightweight HPS-to-FPGA

0xFF400000 1 MB bridge global programm‐ er's view (GPV) registers

HPS2FPGAREGS HPS-to-FPGA bridge GPV

0xFF500000 1 MB registers

FPGA2HPSREGS FPGA-to-HPS bridge GPV

0xFF600000 1 MB registers

EMAC0 Ethernet MAC 0 0xFF700000 8 KB

EMAC1 Ethernet MAC 1 0xFF702000 8 KB

SDMMC SD/MMC 0xFF704000 4 KB

QSPIREGS Quad SPI ash controller

0xFF705000 4 KB registers

FPGAMGRREGS FPGA manager registers 0xFF706000 4 KB

ACPIDMAP ACP ID mapper registers 0xFF707000 4 KB

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HPS Peripheral Region Address Map

Slave Identier Description Base Address Size

GPIO0 GPIO 0 0xFF708000 4 KB

GPIO1 GPIO 1 0xFF709000 4 KB

GPIO2 GPIO 2 0xFF70A000 4 KB

L3REGS L3 interconnect GPV 0xFF800000 1 MB

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NANDDATA NAND ash controller

0xFF900000 64 KB data

QSPIDATA Quad SPI ash data 0xFFA00000 1 MB

USB0 USB 2.0 OTG 0 controller

0xFFB00000 256 KB registers

USB1 USB 2.0 OTG 1 controller

0xFFB40000 256 KB registers

NANDREGS NAND ash controller

0xFFB80000 64 KB registers

FPGAMGRDATA FPGA manager congura‐

0xFFB90000 4 KB tion data

UART0 UART 0 0xFFC02000 4 KB

UART1 UART 1 0xFFC03000 4 KB

I2C0 I2C controller 0 0xFFC04000 4 KB

I2C1 I2C controller 1 0xFFC05000 4 KB

I2C2 I2C controller 2 0xFFC06000 4 KB

I2C3 I2C controller 3 0xFFC07000 4 KB

SPTIMER0 SP Timer 0 0xFFC08000 4 KB

SPTIMER1 SP Timer 1 0xFFC09000 4 KB

SDRREGS SDRAM controller

OSC1TIMER0 OSC1 Timer 0 0xFFD00000 4 KB

OSC1TIMER1 OSC1 Timer 1 0xFFD01000 4 KB

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0xFFC20000 128 KB subsystem registers

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HPS Peripheral Region Address Map

Slave Identier Description Base Address Size

L4WD0 Watchdog Timer 0 0xFFD02000 4 KB

L4WD1 Watchdog Timer 1 0xFFD03000 4 KB

CLKMGR Clock manager 0xFFD04000 4 KB

RSTMGR Reset manager 0xFFD05000 4 KB

SYSMGR System manager 0xFFD08000 16 KB

DMANONSECURE DMA nonsecure registers 0xFFE00000 4 KB

DMASECURE DMA secure registers 0xFFE01000 4 KB

SPIS0 SPI slave 0 0xFFE02000 4 KB

SPIS1 SPI slave 1 0xFFE03000 4 KB

2-19

SPIM0 SPI master 0 0xFFF00000 4 KB

SPIM1 SPI master 1 0xFFF01000 4 KB

SCANMGR Scan manager registers 0xFFF02000 4 KB

ROM Boot ROM 0xFFFD0000 64 KB

MPU MPU registers 0xFFFEC000 8 KB

MPUL2 MPU L2 cache controller

0xFFFEF000 4 KB registers

OCRAM On-chip RAM 0xFFFF0000 64 KB

Related Information

Arria V Address Map and Register Denitions

Web-based address map and register denitions

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101 Innovation Drive, San Jose, CA 95134

Clock Manager

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e hard processor system (HPS) clock generation is centralized in the clock manager. e clock manager is responsible for providing soware-programmable clock control to congure all clocks generated in the HPS. Clocks are organized in clock groups. A clock group is a set of clock signals that originate from the same clock source. A phase-locked loop (PLL) clock group is a clock group where the clock source is a common PLL voltage-controlled oscillator (VCO).

Features of the Clock Manager

e Clock Manager oers the following features:

• Generates and manages clocks in the HPS

• Contains the following PLL clock groups:

• PLL 0 (Main)—contains clocks for the Arm Cortex-A9 microprocessor unit (MPU) subsystem, level 3 (L3) interconnect, level 4 (L4) peripheral bus, and debug

• PLL 1 (Peripheral)—contains clocks for PLL-driven peripherals

• SDRAM—contains clocks for the SDRAM subsystem

• Allows scaling of the MPU subsystem clocks without disabling peripheral and SDRAM clock groups

• Generates clock gate controls for enabling and disabling most clocks

• Initializes and sequences clocks for the following events:

• Cold reset

• Safe mode request from reset manager on warm reset

• Allows soware to program clock characteristics, such as the following items discussed later in this chapter:

• Input clock source for SDRAM and peripheral PLLs

• Multiplier range, divider range, and six post-scale counters for each PLL

• Output phases for SDRAM PLL outputs

• VCO enable for each PLL

• Bypass modes for each PLL

• Gate o individual clocks in all PLL clock groups

• Clear loss of lock status for each PLL

• Safe mode for hardware-managed clocks

• General-purpose I/O (GPIO) debounce clock divide

ISO 9001:2015 Registered

Page 58

3-2

Clock Manager Block Diagram and System Integration

• Allows soware to observe the status of all writable registers

• Supports interrupting the MPU subsystem on PLL-lock and loss-of-lock

• Supports clock gating at the signal level e clock manager is not responsible for the following functional behaviors:

• Selection or management of the clocks for the FPGA-to-HPS and HPS-to-FPGA interfaces. e FPGA logic designer is responsible for selecting and managing these clocks.

• Soware must not program the clock manager with illegal values. If it does, the behavior of the clock manager is undened and could stop the operation of the HPS. e only guaranteed means for recovery from an illegal clock setting is a cold reset.

• When re-programming clock settings, there are no automatic glitch-free clock transitions. Soware must follow a specic sequence to ensure glitch-free clock transitions. Refer to Hardware-Managed and Soware-Managed Clocks section of this chapter.

Related Information

Hardware-Managed and Soware-Managed Clocks on page 3-7

Clock Manager Block Diagram and System Integration

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Figure 3-1: Clock Manager Block Diagram

e following gure shows the major components of the clock manager and its integration in the HPS.

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SDRAM Clock Group

Clock Manager

Peripheral Clock Group

SDRAM

Controller

Subsystem

MPU, L3, L4

& Debug

PLL-Driven Peripherals

Peripheral

PLL 1

f2h_sdram_ref_clk f2h_periph_ref_clk

FPGA Portion

Control & Status

Registers

L4 Bus (osc1_clk)

HPS_CLK2

HPS_CLK1

Flash Controller C locks

Flash

Controllers

osc1_clk

OSC1 Clock Group

Main Clock Group

Dividers

Main PLL 0

SDRAM

PLL

OSC1-Driven

Peripherals

Divider

Dividers

Control

Logic

reset_manager_safe_mode_req

Reset

Manager

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L4 Peripheral Clocks

3-3

L4 Peripheral Clocks

Clock Manager

e L4 peripheral clocks, denoted by l4_mp_clk, range up to 200 MHz.

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3-4

L4 Peripheral Clocks

Table 3-1: Clock List

Peripheral Clock Name Description

USB OTG 0/1

(6)

hclk AHB pmu_hclk PMU AHB clock. pmu_hclk is the

clock

scan clock for the PMU's AHB domain.

Note: Select it as a test clock.

utmi_clk Always used as the PHY domain

clock during DFT Scan mode. Note: Select utmi_clk as a test

clock even when the core is congured for a nonUTMI PHY.

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(6)

pclk APB clock hclk AHB clock ACLK AHB Data port clock mACLK AXI regACLK AHB Register port clock ecc_clk ECC circuitry clock clk_x Bus Interface Clock

Master port clock

Quad SPI Flash Controller

NAND Flash Controller (Locally gated nand_mp_clk.)

EMAC 0/1 aclk Application clock for DMA AXI bus

and CSR APB bus.

SD/MMC Controller sdmmc_clk All registers reside in the BIU clock

domain.

For more information about the specic peripheral clocks, refer to their respective chapters.

Related Information

• SD/MMC Controller on page 15-1

• NAND Flash Controller on page 14-1

• Quad SPI Flash Controller on page 16-1

• Ethernet Media Access Controller on page 18-1

• USB 2.0 OTG Controller on page 19-1

(6)

Clock manager provides CSR bits for soware enables to some peripherals. ese enables are defaulted to enable. In boot mode, these enables are automatically active to ensure all clocks are active if RAM is cleared for security.

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(1 - 64)

Phase Shift

(1/8 Per Step)

C0 Divide

(1 - 512) × K

0 1

Phase Shift

(1/8 Per Step)

C1 Divide

(1 - 512) × K

0 1

CLKOUT1

Phase Shift

(1/8 Per Step)

C2 Divide

(1 - 512) × K

0 1

CLKOUT2

Phase Shift

(1/8 Per Step)

C3 Divide

(1 - 512)

0 1

CLKOUT3

Phase Shift

(1/8 Per Step)

C4 Divide

(1 - 512)

0 1

CLKOUT4

Phase Shift

(1/8 Per Step)

C5 Divide

(1 - 512)

0 1

CLKOUT5

CLKOUT0

PFD VCO

(1 - 4096)

REF

VCO

OUT

PLL Bypass Path

Bypass

Multiplexer

OUT

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Functional Description of the Clock Manager

Clock Manager Building Blocks

PLLs

e clock manager contains three PLLs: PLL 0 (main), PLL 1 (peripherals), and SDRAM. ese PLLs generate the majority of clocks in the HPS. ere is no phase control between the clocks generated by the three PLLs.

Each PLL has the following features:

• Phase detector and output lock signal generation

• Registers to set VCO frequency

• (M) Multiplier range is 1 to 4096

• (N) Divider range is 1 to 64

• Six post-scale counters (C0-C5) with a range of 1 to 512

• PLL can be enabled to bypass all outputs to the osc1_clk clock for glitch-free transitions

e SDRAM PLL has the following additional feature:

Functional Description of the Clock Manager

3-5

• Phase shi of 1/8 per step

• Phase shi range is 0 to 7

FREF, FVCO, and FOUT Equations

Figure 3-2: PLL Block Diagram

Values listed for M, N, and C are actually one greater than the values stored in the CSRs.

Clock Manager

FREF = FIN / N

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3-6

FREF, FVCO, and FOUT Equations

FVCO = F FOUT = F

× M = FIN × M/N

REF

/ (Ci × K) = F

VCO

× M/ (Ci× K) = (FIN × M)/ (N × Ci × K)

REF

Table 3-2: FREF, FVCO, and FOUT Equation variables

Variable Value Description

FVC = VCO frequency FIN = Input frequency FREF = Reference frequency -

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= Post-scale counter i is 0-5 for each of the six counters

K = Internal post-scale counter in main PLL reset values are K = 2 for C0 K=4 for C1

and C2

M = numer + 1 Part of clock feedback path. VCO

N = denom + 1 Part of input clock path. VCO register is

used to program N value. (Range 0 to 64)

Note: e reset values of numer and denom are 1 so that at reset, the M value is 2 and the N value is 2. e vco register is used to program the M and N values. In the table below you can see which sections of

the vco bit eld are used to set the values of M and N.

Table 3-3: VCO Register

Name Bit Reset Range Description

numer 3:15 0x1 0 to 4095 Numerator in VCO

output frequency equation.

denom 16:21 0x1 0 to 63 Denominator in VCO

Unused clock outputs should be set to a safe frequency such as 50 MHz to reduce power consumption and improve system stability.

Related Information

Clock Manager Address Map and Register Denitions on page 3-23

For the full bit eld of the vco register, refer to the Address Map and Register Denitions section.

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Note: Bit 15

reserved.

output frequency equation.

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Dividers

Dividers subdivide the C0-C15 clocks produced by the PLL to lower frequencies. e main PLL C0-C2 clocks have an additional internal post-scale counter.

Clock Gating

Clock gating enables and disables clock signals. Refer to the Peripheral PLL Group Enable Register (en) for more information on what clocks can be gated.

Related Information

Clock Manager Address Map and Register Denitions on page 3-23

Control and Status Registers

e Clock Manager contains registers used to congure and observe the clock manager.

Hardware-Managed and Software-Managed Clocks

When changing values on clocks, the terms hardware-managed and soware-managed dene who is responsible for successful transitions. Soware-managed clocks require that soware manually gate any clock aected by the change, wait for any PLL lock if required, then ungate the clocks. Hardware-managed clocks use hardware to ensure that a glitch-free transition to a new clock value occurs. ere are three hardware-managed sets of clocks in the HPS, namely, clocks generated from the main PLL outputs C0, C1, and C2. All other clocks in the HPS are soware-managed clocks.

Dividers

3-7

Clock Groups

e clock manager contains one clock group for each PLL and one clock group for the HPS_CLK1 pin.

HPS_CLK1 and HPS_CLK2 are powered by the HPS reset and clock input pins power supply (V

For more information on V

CCRSTCLK

OSC1 Clock Group

e clock in the OSC1 clock group is derived directly from the HPS_CLK1 pin. is clock is never gated or divided.

HPS_clk1 is used as a PLL input and also by HPS logic that does not operate on a clock output from a PLL.

Table 3-4: OSC1 Clock Group Clock

Name Frequency Clock Source Destination

osc1_clk 0 to 100 MHz HPS_CLK1 pin OSC1-driven

Main Clock Group

_HPS refer to the Arria V Device Datasheet.

peripherals. Refer to "Main Clock Group Clocks".

CCRSTCLK

_HPS).

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e main clock group consists of a PLL, dividers, and clock gating. e clocks in the main clock group are derived from the main PLL. e main PLL is always sourced from the HPS_CLK1 pin of the device.

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3-8

Main Clock Group

Table 3-5: Main PLL Output Assignments

PLL Output Counter Clock Name Frequency Phase Shift Control

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Main

mpu_base_clk

main_base_clk

dbg_base_clk

main_qspi_base_ clk

main_nand_ sdmmc_base_clk

cfg_h2f_user0_ base_clk

osc1_clk to varies

(7)

osc1_clk to varies

(7)

osc1_clk/4 to mpu_ base_clk/2

Up to 432 MHz No

Up to 250 MHz for

No the NAND ash controller and up to 200 MHz for the SD/ MMC controller

osc1_clk to

No 125 MHz for driving conguration and 100 MHz for the user clock

e

dividers external to the PLL. Transitions to a dierent divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example the clock transitions on cycle 15 of the divide-by-16 divider for the main C2 output and cycle 3 of the divide-by-4 divider for the main C0 output.

e following gure shows how each counter output from the main PLL can have its frequency further divided by programmable post-PLL dividers. Green-colored clock gating logic is directly controlled by soware writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the MPU subsystem clocks.

(7)

e maximum frequency depends on the speed grade of the device.

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counter outputs from the main PLL can have their frequency further divided by programmable

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To Flash

Controller

Clocks

cfg_h2f_user0_base_clk

Clock Gate

mpu_base_clk

main_base_clk

dbg_base_clk

mpu_clkC0

Main

PLL 0

main_qspi_base_clk

main_nand_sdmmc_base_clk

Clock Gate

l3_mp_clk

Clock Gate

l4_mp_clk

Clock Gate

Divide

by 2

Divide

by 4

Clock Gate

l4_sp_clk

Clock Gate

dbg_at_clk

Clock Gate

dbg_clk

Clock Gate

dbg_trace_clk

Clock Gate

dbg_timer_clk

Clock Gate

cfg_clk

Clock Gate

h2f_user0_clock

Divide by

1, 2, or 4

Divide

by 1 or 2

Divide by

1, 2, 4, 8, or 16

Divide

by 1 or 2

Divide

by 2 or 4

mpu_periph_clk

mpu_l2_ram_clk

l4_main_clk

periph_base_clk (from Peripheral PLL C4)

l3_main_clk

l3_sp_clk

Divide by

1, 2, 4, 8, or 16

Divide by

1, 2, 4, 8, or 16

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Figure 3-3: Main Clock Group Divide and Gating

Main Clock Group

3-9

e clocks derived from main PLL C0-C2 outputs are hardware-managed, meaning hardware ensures that a clean transition occurs, and can have the following control values changed dynamically by soware write accesses to the control registers:

• PLL bypass

• PLL numerator, denominator, and counters

• External dividers For these registers, hardware detects that the write has occurred and performs the correct sequence to

Table 3-6: Main Clock Group Clocks

Clock Manager

ensure that a glitch-free transition to the new clock value occurs. ese clocks can pause during the transition.

System Clock Name Frequency Constraints and Notes

mpu_clk

mpu_l2_ram_clk

Send Feedback

Main PLL C0 Clock for MPU subsystem,

mpu_clk/2 Clock for MPU level 2 (L2) RAM

including CPU0 and CPU1

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3-10

Main Clock Group

System Clock Name Frequency Constraints and Notes

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mpu_periph_clk

l3_main_clk

l3_mp_clk

l3_sp_clk

l4_main_clk

l4_mp_clk

l4_sp_clk

mpu_clk/4 Clock for MPU snoop control

unit (SCU) peripherals, such as the general interrupt controller (GIC)

Main PLL C1 Clock for L3 main switch

l3_main_clk/2 Clock for L3 master peripherals

(MP) switch

l3_mp_clk or l3_mp_clk/2 Clock for L3 slave peripherals

(SP) switch

Main PLL C1 Clock for L4 main bus

osc1_clk/16 to 100 MHz divided

Clock for L4 MP bus from main PLL C1 or peripheral PLL C4

osc1_clk/16 to 100 MHz divided

Clock for L4 SP bus from main PLL C1 or peripheral PLL C4

dbg_at_clk

dbg_trace_clk

dbg_timer_clk

dbg_clk

(8)

main_qspi_clk

main_nand_sdmmc_clk

cfg_clk

osc1_clk/4 to main PLL C2/2 Clock for CoreSight

™

debug

trace bus

osc1_clk/16 to main PLL C2 Clock for CoreSight

™

debug

Trace Port Interface Unit (TPIU)

osc1_clk to main PLL C2 Clock for the trace timestamp

generator

dbg_at_clk/2 or dbg_at_clk/4 Clock for Debug Access Port

(DAP) and debug peripheral bus

Main PLL C3 Quad SPI ash internal logic

clock

Main PLL C4 Input clock to ash controller

clocks block

osc1_clk to 100_MHz divided from

main PLL C5

FPGA manager conguration

clock

(8)

dbg_clk must be at least twice as fast as the JTAG clock.

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Changing Values That Aect Main Clock Group PLL Lock

System Clock Name Frequency Constraints and Notes

3-11

h2f_user0_clock

osc1_clk to 100_MHz divided from

main PLL C5

Changing Values That Aect Main Clock Group PLL Lock

To change any value that aects the VCO lock of the main clock group PLL including the hardwaremanaged clocks, soware must put the main PLL in bypass mode, which causes all the main PLL output clocks to be driven by the osc1_clk clock. Soware must detect PLL lock by reading the lock status register prior to taking the main PLL out of bypass mode.

Once a PLL is locked, changes to any PLL VCO frequency that are 20 percent or less do not cause the PLL to lose lock. Iteratively changing the VCO frequency in increments of 20 percent or less allow a slow ramp of the VCO base frequency without loss of lock. For example, to change a VCO frequency by 40% without losing lock, change the frequency by 20%, then change it again by 16.7%.

Peripheral Clock Group

e peripheral clock group consists of a PLL, dividers, and clock gating. e clocks in the peripheral clock group are derived from the peripheral PLL. e peripheral PLL can be programmed to be sourced from the HPS_CLK1 pin, the HPS_CLK2 pin, or the f2h_periph_ref_clk clock provided by the FPGA fabric.

e FPGA fabric must be congured with an image that provides the f2h_periph_ref_clk before selecting it as the clock source. If the FPGA must be recongured and f2h_periph_ref_clk is being used by modules in the HPS, an alternate clock source must be selected prior to reconguring the FPGA.

Auxiliary user clock to the FPGA

fabric

Clocks that always use the peripheral PLL output clocks as the clocks source are:

• emac0_clk

• emac1_clk

• usb_mp_clk

• spi_m_clk

• gpio_db_clk

• h2f_user1_clk In addition, clocks that may use the peripheral PLL output clocks as the clock source are:

• sdmmc_clk

• nand_clk

• qspi_clk

• l4_mp_clk

• l4_sp_clk e counter outputs from the main PLL can have their frequency further divided by external dividers.

Transitions to a dierent divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example, the clock transitions on cycle 15 of the divide-by-16 divider for the main C2 output and cycle 3 of the divide-by-4 divider for the C1 output.

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3-12

Peripheral Clock Group

Table 3-7: Peripheral PLL Output Assignments

PLL Output Counter Clock Name Frequency Phase Shift Control

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Peripheral

emac0_base_clk

emac1_base_clk

periph_qspi_ base_clk

periph_nand_ sdmmc_base_clk

periph_base_ base_clk

h2f_user1_base_ clk

Up to 250 MHz No

Up to 432 MHz No

Up to 250 MHz for

No the NAND ash controller and up to 200 MHz for the SD/ MMC controller

Up to 240 MHz for

No the SPI masters and up to 200 MHz for the scan manager

osc1_clk to

No 100 MHz

e

following gure shows programmable post-PLL dividers and clock gating for the peripheral clock group. Clock gate blocks in the diagram indicate clocks that may be gated o under soware control. Soware is expected to gate these clocks o prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.

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h2f_user1_base_clk

Clock Gate

emac0_base_clk

emac1_base_clk

periph_qspi_base_clk

emac0_clk

emac1_clk

Peripheral

PLL 1

periph_nand_sdmmc_base_clk

periph_base_clk

24-Bit

Divider

Clock Gate

spi_m_clk

Clock Gate

can0_clk

Clock Gate

can1_clk

Clock Gate

gpio_db_clk

Clock Gate

To main PLL group l4_mp_clk & l4_sp_clk multiplexer

Clock Gate

h2f_user1_clock

usb_mp_clk

Divide by

1, 2, 4, 8, or 16

Divide by

1, 2, 4, 8, or 16

Divide by

1, 2, 4, 8, or 16

Divide by

1, 2, 4, 8, or 16

To Flash Controller Clocks

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Figure 3-4: Peripheral Clock Group Divide and Gating

Peripheral Clock Group

3-13

Table 3-8: Peripheral Clock Group Clocks

Clock Manager

System Clock Name Frequency Divided From Constraints and Notes

usb_mp_clk

spi_m_clk

Up to 200 MHz Peripheral PLL C4 Clock for USB

Up to 240 MHz for the SPI masters and up to

Peripheral PLL C4 Clock for L4 SPI master

bus and scan manager 200 MHz for the scan manager

emac0_clk

Up to 250 MHz Peripheral PLL C0 EMAC0 clock. e

250 MHz clock is

divided internally by

the EMAC into the

typical 125/25/2.5 MHz

speeds for 1000/100/

10 Mbps operation.

Send Feedback

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Clock Gate

sdmmc_clk

Divide by 4

Clock Gate

nand_clk

f2h_periph_ref_clk

main_nand_sdmmc_base_clk

periph_nand_sdmmc_base_clk

f2h_periph_ref_clk

main_nand_sdmmc_base_clk

periph_nand_sdmmc_base_clk

Clock Gate

qspi_clk

f2h_periph_ref_clk

main_qspi_base_clk

periph_qspi_base_clk

Clock Gate

nand_x_clk

3-14

Flash Controller Clocks

System Clock Name Frequency Divided From Constraints and Notes

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emac1_clk

l4_mp_clk

l4_sp_clk

gpio_db_clk

h2f_user1_clock

Flash Controller Clocks

Up to 250 MHz Peripheral PLL C1 EMAC1 clock

e 250 MHz clock is

divided internally by

the EMAC into the

typical 125/25/2.5 MHz

speeds for 1000/100/

10 Mbps operation.

Up to 100 MHz Main PLL C1 or peripheral

PLL C4

Up to 100 MHz Main PLL C1 or peripheral

PLL C4

Clock for L4 master

peripheral bus

Clock for L4 slave

peripheral bus

Up to 1 MHz Peripheral PLL C4 Used to debounce

GPIO0, GPIO1, and

GPIO2

Peripheral PLL C5 Peripheral PLL C5 Auxiliary user clock to

the FPGA fabric

Flash memory peripherals can be driven by the main PLL, the peripheral PLL, or from clocks provided by the FPGA fabric.

Figure 3-5: Flash Peripheral Clock Divide and Gating

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Table 3-9: Flash Controller Clocks

SDRAM Clock Group

3-15

System Clock Name Freq

uency

qspi_clk

nand_x_clk

nand_clk

sdmmc_clk

Up to 432 MHz Peripheral PLL C2, main

Up to 250 MHz Peripheral PLL C3, main

nand_x_clk/4 Peripheral PLL C3, main

Up to 200 MHz Peripheral PLL C3, main

Divided From Constraints and Notes

PLL C3, or f2h_periph_

ref_clk

PLL C4, or f2h_periph_

ref_clk

PLL C4, or f2h_periph_

ref_clk

PLL C4, or f2h_periph_

ref_clk

Clock for quad SPI,

typically 108 and

80 MHz

NAND ash controller

master and slave clock

Main clock for NAND

ash controller, sets

base frequency for

NAND transactions

• Less than or equal to memory maximum operating frequency

• 45% to 55% duty cycle

• Typical frequencies are 25 and 50 MHz

• SD/MMC has a subclock tree divided down from this clock

SDRAM Clock Group

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e SDRAM clock group consists of a PLL and clock gating. e clocks in the SDRAM clock group are derived from the SDRAM PLL. e SDRAM PLL can be programmed to be sourced from the HPS_CLK1 pin, the HPS_CLK2 pin, or the f2h_sdram_ref_clk clock provided by the FPGA fabric.

e FPGA fabric must be congured with an image that provides the f2h_sdram_ref_clk before selecting it as the clock source. If the FPGA must be recongured and the f2h_sdram_ref_clk is the clock source for the SDRAM clock group, an alternate clock source must be selected prior to reconguring the FPGA.

e counter outputs from the SDRAM PLL can be gated o directly under soware control. e divider values for each clock are set by registers in the clock manager.

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Page 72

h2f_user2_base_clk

Clock Gate

ddr_dqs_base_clk

ddr_2x_dqs_base_clk

ddr_dq_base_clk

ddr_dqs_clk

ddr_2x_dqs_clk

ddr_dq_clk

h2f_user2_clock

SDRAM

PLL

Unused

3-16

SDRAM Clock Group

Table 3-10: SDRAM PLL Output Assignments

PLL Output Counter Clock Name Frequency Phase Shift Control

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ddr_dqs_ base_clk

ddr_2x_dqs_ base_clk

SDRAM

ddr_dq_base_ clk

h2f_user2_ base_clk

e following gure shows clock gating for SDRAM PLL clock group. Clock gate blocks in the diagram indicate clocks which may be gated o under soware control. Soware is expected to gate these clocks o prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.

Figure 3-6: SDRAM Clock Group Divide and Gating

Varies

(9)

ddr_dqs_base_ clk x 2

ddr_dqs_base_ clk

osc1_clk to

(9)

varies

Yes

e SDRAM PLL output clocks can be phase shied in real time in increments of 1/8 the VCO frequency. Maximum number of phase shi increments is 4096.

Table 3-11: SDRAM Clock Group Clocks

Name Frequency Constraints and Notes

ddr_dqs_clk

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(9)

e maximum frequency depends on the speed grade of the device.

SDRAM PLL C0 Clock for MPFE, single-port

controller, CSR access, and PHY

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Resets

Name Frequency Constraints and Notes

3-17

ddr_2x_dqs_clk

ddr_dq_clk

h2f_user2_clock

Resets

Cold Reset

Cold reset places the hardware-managed clocks into safe mode, the soware-managed clocks into their default state, and asynchronously resets all registers in the clock manager.

Related Information

Safe Mode on page 3-17

Warm Reset

Registers in the clock manager control how the clock manager responds to warm reset. Typically, soware places the clock manager into a safe state in order to generate a known set of clocks for the ROM code to boot the system. e behavior of the system on warm reset as a whole, including how the FPGA fabric, boot code, and debug systems are congured to behave, must be carefully considered when choosing how the clock manager responds to warm reset.

SDRAM PLL C1 Clock for PHY

SDRAM PLL C2 Clock for PHY

SDRAM PLL C5 Auxiliary user clock to the FPGA

fabric

e reset manager can request that the clock manager go into safe mode as part of the reset manager’s warm reset sequence. Before asserting safe mode to the clock manager, the reset manager ensures that the reset signal is asserted to all modules that receive warm reset.

Related Information

Reset Manager on page 4-1

For more information, refer to “Reset Sequencing” in the Reset Manager chapter.

Safe Mode

Safe mode is enabled in the HPS by a cold reset. Also, if the ensfmdwr bit in the ctrl register is set, clock manager responds to the Safe Mode request from Reset Manager on a warm reset and sets the Safe Mode bit. No other control register bits are aected by the safe mode request from the Reset Manager.

Note:

When safe mode is enabled, the main PLL hardware-managed clocks (C0-C2) are bypassed to osc1_clk clock and are directly generated from osc1_clk. While in safe mode, clock manager register settings, which control clock behavior, are not changed. However, the hardware bypasses these settings and uses safe, default settings.

By default the preloader generated by the SoC EDS tool sets the ensfmdwr bit aer bringing the clocks out from reset. In order to ensure the stability of the system, Intel recommends that you do not clear the ensfmdwr bit during any of the later HPS boot stages.

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3-18

Interrupts

e hardware-managed clocks are forced to their safe mode values such that the following conditions occur:

• e hardware-managed clocks are bypassed to osc1_clk, including counters in the main PLL.

• Programmable dividers select the reset default values.

• e ash controller clocks multiplexer selects the output from the peripheral PLL.

• All clocks are enabled. A write by soware is the only way to clear the safe mode bit (safemode) of the ctrl register. Note: Before coming out of safe mode, all registers and clocks must be congured correctly. It is possible

Interrupts

e clock manager provides one interrupt output which is enabled using the interrupt enable register (intren). e interrupt is the OR of the bits in the interrupt status register (inter) that indicate lock and loss of lock for each of the three PLLs.

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to program the clock manager in such a way that only a cold reset can return the clocks to a functioning state. Intel strongly recommends using provided libraries to congure and control HPS clocks.

Clock Usage By Module

e following table lists every clock input generated by the clock manager to all modules in the HPS. System clock names are global for the entire HPS and system clocks with the same name are phase-aligned at all endpoints.

Table 3-12: Clock Usage By Module

Module Name System Clock Name Use

MPU subsystem

mpu_clk

mpu_periph_clk

dbg_at_clk

dbg_clk

mpu_l2_ram_clk

Main clock for the MPU subsystem

Peripherals inside the MPU subsystem

Trace bus

Debug

L2 cache and Accelerator Coherency Port (ACP) ID mapper

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l4_mp_clk

ACP ID mapper control slave

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Clock Usage By Module

Module Name System Clock Name Use

3-19

Interconnect

l3_main_clk

dbg_at_clk

dbg_clk

l3_mp_clk

l4_mp_clk

usb_mp_clk

nand_x_clk

cfg_clk

L3 main switch

System Trace Macrocell (STM) slave and Embedded Trace Router (ETR) master connections

DAP master connection

L3 master peripheral switch

L4 MP bus, Secure Digital (SD) / MultiMediaCard (MMC) master, and EMAC masters

USB masters and slaves

NAND master

FPGA manager conguration data slave

Boot ROM

On-chip RAM

l3_sp_clk

l3_main_clk

mpu_l2_ram_clk

osc1_clk

spi_m_clk

l4_sp_clk

l4_mp_clk

l3_main_clk

L3 slave peripheral switch

L4 SPIS bus master

ACP ID mapper slave and L2 master connections

L4 OSC1 bus master

L4 SPIM bus master

L4 SP bus master

Quad SPI bus slave

Boot ROM

On-chip RAM

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3-20

Clock Usage By Module

Module Name System Clock Name Use

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DMA controller

FPGA manager

HPS-to-FPGA bridge

FPGA-to-HPS bridge

l4_main_clk

dbg_at_clk

l4_mp_clk

cfg_clk

l4_mp_clk

l3_main_clk

l4_mp_clk

l3_main_clk

l4_mp_clk

DMA

Synchronous to the STM module

Synchronous to the quad SPI

ash

Control block (CB) data interface and conguration data slave

Control slave

Data slave

Global programmer's view (GPV) slave

Data master

GPV slave

Lightweight HPS-to-FPGA bridge

Quad SPI ash controller

SD/MMC controller

EMAC 0

l4_mp_clk

qspi_clk

l4_mp_clk

sdmmc_clk

l4_mp_clk

emac0_clk

osc1_clk

GPV masters and the data and GPV slave

Control slave

Reference for serialization

Master and slave

SD/MMC internal logic

Master

EMAC 0 internal logic

IEEE 1588 timestamp

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Clock Usage By Module

Module Name System Clock Name Use

3-21

EMAC 1

USB 0

USB 1

NAND ash controller

OSC1 timer 0

OSC1 timer 1

l4_mp_clk

emac1_clk

osc1_clk

usb_mp_clk

nand_x_clk

nand_clk

osc1_clk

Master

EMAC 1 internal logic

IEEE 1588 timestamp

Master and Slave

NAND high-speed master and slave

NAND ash

OSC1 timer 0

OSC1 timer 1

SP timer 0

SP timer 1

I2C controller 0

I2C controller 1

I2C controller 2

I2C controller 3

UART controller 0

UART controller 1

l4_sp_clk

SP timer 0

SP timer 1

I2C 0

I2C 1

I2C 2

I2C 3

UART 0

UART 1

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Clock Usage By Module

Module Name System Clock Name Use

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GPIO interface 0

GPIO interface 1

GPIO interface 2

System manager

l4_mp_clk

gpio_db_clk

l4_mp_clk

gpio_db_clk

l4_mp_clk

gpio_db_clk

osc1_clk

l4_sp_clk

ddr_dq_clk

Slave

Debounce

Slave

Debounce

Slave

Debounce

System manager

Control slave

O-chip data

SDRAM subsystem

L4 watchdog timer 0

L4 watchdog timer 1

SPI master controller 0

SPI master controller 1

SPI slave controller 0

ddr_dqs_clk

ddr_2x_dqs_clk

mpu_l2_ram_clk

l3_main_clk

osc1_clk

spi_m_clk

l4_main_clk

MPFE, single-port controller, CSRs, and PHY

O-chip strobe data

Slave connected to MPU subsystem L2 cache

Slave connected to L3 intercon‐ nect

L4 watchdog timer 0

L4 watchdog timer 1

SPI master 0

SPI master 1

SPI slave 0

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Clock Manager Address Map and Register Denitions

Module Name System Clock Name Use

3-23

SPI slave controller 1

Debug subsystem

Reset manager

Scan manager

Timestamp generator

l4_main_clk

l4_mp_clk

dbg_clk

dbg_at_clk

dbg_trace_clk

osc1_clk

l4_sp_clk

spi_m_clk

dbg_timer_clk

SPI slave 1

System bus

Debug

Trace bus

Trace port

Reset manager

Slave

Scan manager

Timestamp generator

Clock Manager Address Map and Register Denitions

e address map and register denitions for the HPS-FPGA bridge consist of the following regions:

• Clock Manager Module

Related Information

• Introduction to the Hard Processor System on page 2-1 e base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter.

• https://www.intel.com/content/www/us/en/programmable/hps/arria-v/hps.html

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101 Innovation Drive, San Jose, CA 95134

Reset Manager

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e reset manager generates module reset signals based on reset requests from the various sources in the HPS and FPGA fabric, and soware writing to the module-reset control registers. e reset manager ensures that a reset request from the FPGA fabric can occur only aer the FPGA portion of the systemon-a-chip (SoC) device is congured.

e HPS contains multiple reset domains. Each reset domain can be reset independently. A reset may be initiated externally, internally or through soware.

Table 4-1: HPS Reset Domains

Domain Name Domain Logic

TAP JTAG test access port (TAP) controller, which is used by the debug

access port (DAP).

Debug All debug logic including most of the DAP, CoreSight™ components

connected to the debug peripheral bus, trace, the microprocessor unit (MPU) subsystem, and the FPGA fabric.

System All HPS logic except what is in the TAP and debug reset domains.

Includes non-debug logic in the FPGA fabric connected to the HPS reset signals.

ISO 9001:2015 Registered

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4-2

Reset Manager Block Diagram and System Integration

e HPS supports the following reset types:

• System cold reset

• Used to ensure the HPS is placed in a default state sucient for soware to boot

• Triggered by a power-on reset and other sources

• Resets all HPS logic that can be reset

• Aects all reset domains

• System warm reset

• Occurs aer HPS has already completed a cold reset

• Used to recover system from a non-responsive condition

• Resets a subset of the HPS state reset by a cold reset

• Only aects the system reset domain, which allows debugging (including trace) to operate through the warm reset

• Debug reset

• Used to recover debug logic from a non-responsive condition

• Only aects the debug reset domain

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Reset Manager Block Diagram and System Integration

e following gure shows a block diagram of the reset manager in the SoC device. For clarity, resetrelated handshaking signals to other HPS modules and to the clock manager module are omitted.

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HPS

FPGA Portion

Control

Block

f2h_dbg_rst_req_n f2h_cold_rst_req_n f2h_warm_rst_req_n

h2f_rst_n

h2f_cold_rst_n

h2f_dbg_rst_n

FPGA Fabric

Reset Manager

Reset

Controller

Module Reset Signals

usermode

Watchdog Reset Request[1:0]

Debug Reset Request

POR Voltage Reset Request

System Watchdog Reset Request[1:0]

CSRs

Slave Interface

L4 Peripheral Bus (l4_sp_clk)

MPU

DAP

POR Voltage

Detector

Watchdog (2)

nPOR

nRST

Signal

Assertion /

De-Assertion

(mpumodrst, permodrst, per2modrst, brgmodrst, and miscmodrst)

(swcoldrstreq and swwarmrstreq bits of ctrl)

Scan Manager Reset Request

Scan Manager

load_csr

fpga_config_complete

HPS Modules

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Figure 4-1: Reset Manager Block Diagram

HPS External Reset Sources

4-3

HPS External Reset Sources

e following table lists the reset sources external to the HPS. All signals are synchronous to the osc1_clk clock. e reset signals from the HPS to the FPGA fabric must be synchronized to your user logic clock domain.

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4-4

Reset Controller

Table 4-2: HPS External Reset Sources

Source Description

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f2h_cold_rst_req_n

f2h_warm_rst_req_n

f2h_dbg_rst_req_n

h2f_cold_rst_n

h2f_rst_n

h2f_dbg_rst_n

load_csr

Cold reset request from FPGA fabric (active low)

Warm reset request from FPGA fabric (active low)

Debug reset request from FPGA fabric (active low)

Cold-only reset to FPGA fabric (active low)

Cold or warm reset to FPGA fabric (active low)

Debug reset (dbg_rst_n) to FPGA fabric (active low)

Cold-only reset from FPGA control block (CB) and scan manager

nPOR

nRST

nRST and nPOR are powered by the HPS reset and clock input pins power supply (V

information on V

CCRSTCLK

_HPS, refer to the Arria V Device Datasheet.

Power-on reset pin (active low)

Warm reset pin (active low)

CCRSTCLK

_HPS). For more

Related Information

Arria V GX, GT, SX, and ST Device Datasheet

For information about the required duration of reset request signal assertion, refer to the Arria V Device Datasheet.

Reset Controller

e reset controller performs the following functions:

• Accepts reset requests from the FPGA CB, FPGA fabric, modules in the HPS, and reset pins

• Generates an individual reset signal for each module instance for all modules in the HPS

• Provides reset handshaking signals to support system reset behavior e reset controller generates module reset signals from external reset requests and internal reset requests.

External reset requests originate from sources external to the reset manager. Internal reset requests originate from control registers in the reset manager.

e reset controller supports the following cold reset requests:

• Power-on reset (POR) voltage monitor

• Cold reset request pin (nPOR)

• FPGA fabric

• FPGA CB and scan manager

• Soware cold reset request bit (swcoldrstreq) of the control register (ctrl)

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POR Voltage Monitor

nPOR Pin

FPGA Fabric (f2h_cold_rst_req_n)

FPGA CB & Scan Manager

nRST Pin

FPGA Fabric (f2h_warm_rst_req_n)

MPU Watchdog Reset [1:0]

System Watchdog Reset [1:0]

CDBGRSTREQ (DAP)

FPGA Fabric (f2h_dbg_rst_req_n)

ETR

SDRAM Self-Refresh

FPGA Manager SCAN Manager

FPGA Fabric

(Module Reset Signals)

dbg_rst_n

JTAG TAP (DAP)

CPUCLKOFF[1:0]

CDBGRSTACK (DAP)

ETR SDRAM Self-Refresh FPGA Manager SCAN Manager FPGA

Cold Reset Requests

Warm Reset Requests

Debug Reset Requests

Reset Handshaking Inputs

Module Resets

Debug Domain

Reset

TAP Domain

Reset

MPU Clock

Gating

Reset

Handshaking

Outputs

Reset Manager

APB Slave Interface

osc1_clk

Reset Controller

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e reset controller supports the following warm reset requests:

• Warm reset request pin (nRST)

• FPGA fabric

• Soware warm reset request bit (swwarmrstreq) of the ctrl register

• MPU watchdog reset requests for CPU0 and CPU1

• System watchdog timer 0 and 1 reset requests e reset controller supports the following debug reset requests:

• CDBGRSTREQ from DAP

• FPGA fabric

Figure 4-2: Reset Controller Signals

Module Reset Signals

4-5

Module Reset Signals

e following tables list the module reset signals. e module reset signals are organized in groups for the MPU, peripherals, bridges.

In the following tables, columns marked for Cold Reset, Warm Reset, and Debug Reset denote reset signals asserted by each type of reset. For example, writing a 1 to the swwarmrstreq bit in the ctrl register resets all the modules that have a checkmark in the Warm Reset column.

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Module Reset Signals

e column marked for Soware Deassert denotes reset signals that are le asserted by the reset manager.

Table 4-3: MPU Group, Generated Module Resets

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Module Reset Signal Description Reset

mpu_cpu_rst_n[0] Resets each

System X X processor in the MPU

mpu_cpu_rst_n[1]

Resets each

System processor in the MPU

mpu_wd_rst_n

Resets both per-

System processor watchdogs in the MPU

mpu_scu_periph_rst_n

Resets Snoop

System Control Unit (SCU) and peripherals

mpu_l2_rst_n

Level 2 (L2)

System cache reset

Domain

Cold

Reset

Warm

Reset

Debug

Reset

X X X

X X

Software Deassert

Table 4-4: PER Group, Generated Module Resets

Module Reset Signal Description Reset

emac_rst_n[1:0]

usb_rst_n[1:0]

nand_flash_rst_n

Resets each EMAC System X X

Resets each USB System X X

Resets NAND ash controller

qspi_flash_rst_n

Resets quad SPI ash controller

watchdog_rst_n[1:0]

Resets each system watchdog timer

osc1_timer_rst_n[1:0]

sp_timer_rst_n[1:0]

Resets each OSC1 timer System X X

Resets each SP timer System X X

Domai

Cold

Reset

Warm Reset

System X X

Debug

Reset

Software Deassert

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Module Reset Signals

4-7

Module Reset Signal Description Reset

i2c_rst_n[3:0]

uart_rst_n[1:0]

spim_rst_n[1:0]

spis_rst_n[1:0]

sdmmc_rst_n

gpio_rst_n[2:0]

dma_rst_n

sdram_rst_n

Resets each I2C controller System X X

Resets each UART System X X

Resets SPI master controller System X X

Resets SPI slave controller System X X

Resets SD/MMC controller System X X

Resets each GPIO interface System X X

Resets DMA controller System X X

Resets SDRAM subsystem (resets logic associated with cold or warm reset)

Domai

Cold

Reset

Warm Reset

System X X

Debug

Reset

Software Deassert

Table 4-5: PER2 Group, Generated Module Resets

Module Reset Signal Description Reset

dma_periph_if_rst_n[7:0] DMA controller request

interface from FPGA fabric to DMA controller

Table 4-6: Bridge Group, Generated Module Resets

Module Reset Signal Description Reset

hps2fpga_bridge_rst_n Resets HPS-to-FPGA

AMBA* Advanced eXtensible Interface (AXI) bridge

fpga2hps_bridge_rst_n Resets FPGA-to-HPS AXI

bridge

lwhps2fpga_bridge_rst_n Resets lightweight HPS-to-

FPGA AXI bridge

Domai

Cold

Reset

Warm

Reset

Debu

Reset

SystemX X X

Domai

Cold

Reset

Warm

Reset

Debu

Reset

SystemX X X

Software Deassert

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Module Reset Signals

Table 4-7: MISC Group, Generated Module Resets

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Module Reset Signal Description Reset

Domai

boot_rom_rst_n Resets boot ROM Syste

onchip_ram_rst_n Resets on-chip RAM Syste

sys_manager_rst_n Resets system manager

SystemX X (resets logic associated with cold or warm reset)

sys_manager_cold_rst_n Resets system manager

SystemX (resets logic associated with cold reset only)

fpga_manager_rst_n Resets FPGA manager Syste

acp_id_mapper_rst_n Resets ACP ID mapper Syste

h2f_rst_n Resets user logic in FPGA

SystemX X fabric (resets logic associated with cold or warm reset)

Cold

Reset

X X

Warm

Reset

Debu

Reset

Software Deassert

h2f_cold_rst_n Resets user logic in FPGA

SystemX fabric (resets logic associated with cold reset only)

rst_pin_rst_n Pulls nRST pin low Syste

timestamp_cold_rst_n Resets debug timestamp to

SystemX 0x0

clk_manager_cold_rst_n Resets clock manager

SystemX (resets logic associated with cold reset only)

scan_manager_rst_n Resets scan manager Syste

frz_ctrl_cold_rst_n Resets freeze controller

SystemX (resets logic associated with cold reset only)

sys_dbg_rst_n Resets debug masters and

SystemX X slaves connected to L3 interconnect and level 4 (L4) buses

X X

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Modules Requiring Software Deassert

4-9

Module Reset Signal Description Reset

dbg_rst_n Resets debug components

including DAP, trace, MPU debug logic, and any user debug logic in the FPGA fabric

tap_cold_rst_n Resets portion of TAP

controller in the DAP that must be reset on a cold reset

sdram_cold_rst_n Resets SDRAM subsystem

(resets logic associated with cold reset only)

Table 4-8: L3 Group, Generated Module Resets

Module Reset Signal Description Reset

l3_rst_n Resets L3 interconnect and

L4 buses

Domai

Cold

Reset

Warm

Reset

Debug X X

TAP X

SystemX

Domai

Cold

Reset

Warm

Reset

SystemX X

Debu

Reset

Debu

Reset

Software Deassert

Modules Requiring Software Deassert

e reset manager leaves the reset signal asserted on certain modules even aer the rest of the HPS has come out of reset. ese modules are likely to require soware conguration before they can safely be taken out of reset.

When a module that has been held in reset is ready to start running, soware can deassert the reset signal by writing to the appropriate register, shown in the following table.

Table 4-9: Module Reset Signals and Registers

HPS Peripheral Reset Register Module Reset Signal Reset Group

MPU mpumodrst mpu_cpu_rst_n[1] MPU Ethernet MAC permodrst emac_rst_n[1:0] PER USB 2.0 OTG permodrst usb_rst_n[1:0] PER NAND permodrst nand_flash_rst_n PER Quad SPI permodrst qspi_flash_rst_n PER Watchdog permodrst watchdog_rst_n[1:0] PER Timer permodrst osc1_timer_rst_n[1:0] PER Timer permodrst sp_timer_rst_n[1:0] PER I2C permodrst i2c_rst_n[3:0] PER

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Slave Interface and Status Register

HPS Peripheral Reset Register Module Reset Signal Reset Group

UART permodrst uart_rst_n[1:0] PER SPI Master permodrst spim_rst_n[1:0] PER SPI Slave permodrst spis_rst_n[1:0] PER SD/MMC permodrst sdmmc_rst_n PER GPIO permodrst gpio_rst_n[2:0] PER DMA permodrst dma_rst_n PER SDRAM permodrst sdram_rst_n PER DMA Peripheral Interfaces per2modrst dma_periph_if_rst_n[7:0] PER2 HPS-to-FPGA Bridge brgmodrst hps2fpga_bridge_rst_n Bridge FPGA-to-HPS Bridge brgmodrst fpga2hps_bridge_rst_n Bridge Lightweight HPS-to-FPGA Bridge brgmodrst lwhps2fpga_bridge_rst_n Bridge

Slave Interface and Status Register

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e reset manager slave interface is used to control and monitor the reset states. e status register (stat) in the reset manager contains the status of the reset requester. e register

contains a bit for each monitored reset request. e stat register captures all reset requests that have occurred. Soware is responsible for clearing the bits.

During the boot process, the Boot ROM copies the stat register value into memory before clearing it. Aer booting, you can read the value of the reset status register at memory address (r0 + 0x0038). For more information, refer to the "Shared Memory" section of the Booting and Conguration appendix.

Related Information

Shared Memory on page 30-31

Functional Description of the Reset Manager

e reset manager generates reset signals to modules in the HPS and to the FPGA fabric. e following actions generate reset signals:

• Soware writing a 1 to the swcoldrstreq or swwarmrstreq bits in the ctrl register. Writing either bit causes the reset controller to perform a reset sequence.

• Soware writing to the mpumodrst, permodrst, per2modrst, brgmodrst, or miscmodrst module reset control registers.

• Asserting reset request signals triggers the reset controller. All external reset requests cause the reset controller to perform a reset sequence.

Multiple reset requests can be driven to the reset manager at the same time. Cold reset requests take priority over warm and debug reset requests. Higher priority reset requests preempt lower priority reset requests. ere is no priority dierence among reset requests within the same domain.

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If a cold reset request is issued while another cold reset is already underway, the reset manager extends the reset period for all the module reset outputs until all cold reset requests are removed. If a cold reset request is issued while the reset manager is removing other modules out of the reset state, the reset manager returns those modules back to the reset state.

If a warm reset request is issued while another warm reset is already underway, the rst warm reset completes before the second warm reset begins. If the second warm reset request is removed before the rst warm reset completes, the warm rst reset is extended to meet the timing requirements of the second warm reset request.

e nPOR pin can be used to extend the cold reset beyond what the POR voltage monitor automatically provides. e use of the nPOR pin is optional and can be tied high when it is not required.

Related Information

Arria V GX, GT, SX, and ST Device Datasheet

For information about the required duration of reset request signal assertion, refer to the Arria V Device Datasheet.

Reset Sequencing

e reset controller sequences resets without soware assistance. Module reset signals are asserted asynchronously and synchronously. e reset manager deasserts the module reset signals synchronous to the osc1_clk clock. Module reset signals are deasserted in groups in a xed sequence. All module reset signals in a group are deasserted at the same time.

Reset Sequencing

4-11

e reset manager sends a safe mode request to the clock manager to put the clock manager in safe mode, which creates a xed and known relationship between the osc1_clk clock and all other clocks generated by the clock manager.

Aer the reset manager releases the MPU subsystem from reset, CPU1 is le in reset and CPU0 begins executing code from the reset vector address. Soware is responsible for deasserting CPU1 and other resets, as shown in the MPU Group and Generated Module Resets table. Soware deasserts resets by writing the mpumodrst, permodrst, per2modrst, brgmodrst, and miscmodrst module-reset control registers.

Soware can also bypass the reset controller and generate reset signals directly through the module-reset control registers. In this case, soware is responsible for asserting module reset signals, driving them for the appropriate duration, and deasserting them in the correct order. e clock manager is not typically in safe mode during this time, so soware is responsible for knowing the relationship between the clocks generated by the clock manager. Soware must not assert a module reset signal that would prevent soware from deasserting the module reset signal. For example, soware should not assert the module reset to the processor executing the soware.

Table 4-10: Minimum Pulse Width

Reset Type Value

Warm Reset 6 osc1_clk cycles

Cold Reset 6 osc1_clk cycles

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clk_mgr_cold_rst_n

l3_rst_n

miscmod_rst_n

dbg_rst_n

mpu_clkoff[0]

mpu_rst_n[0]

mpu_wd_rst_n

mpu_scu_rst_n

mpu_periph_rst_n

mpu_l2_rst_n

peripheral resets

Software

brings out

of reset

32 96 100 32 32200

nPOR pin

(1)

(2)

(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins. (2) This dependency applies to all the reset signals.

4-12

Reset Sequencing

Figure 4-3: Cold Reset Timing Diagram

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nRST pin

(1)

l3_rst_n

miscmod_rst_n

mpu_clkoff[0]

mpu_rst_n[0]

mpu_wd_rst_n

mpu_scu_rst_n

mpu_periph_rst_n

mpu_l2_rst_n

peripheral resets

Software

brings out

of reset

cm_rm_safe_mode_ack

h2f_pending_rst_req_n

(2)

(and other wait

request handshakes)

f2h_pending_rst_ack_n

safe_mode_req

nRST Pin Count

(3)

100

32 32

2008 256

(3)

(1) Cold reset can be initiated from several other sources: FPGA CB, FPGA fabric, modules in the HPS, and reset pins. (2) When the nRSTpin count is zero, the 256 cycle stretch count is skipped and the start of the deassertion sequence is determined by the safe mode acknowledge signal or the user releasing the warm reset button, whichever occurs later.

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Figure 4-4: Warm Reset Timing Diagram

Cold Reset Assertion Sequence

4-13

Reset Manager

Cold Reset Assertion Sequence

e cold and warm reset sequences consist of dierent reset assertion sequences and the same deassertion sequence. e following sections describe the sequences.

Note:

Cold and warm reset aect only the cpu0, and by default cpu1 is held in reset until the soware running in the cpu0 releases it.

Related Information

• Module Reset Signals on page 4-5

• Clock Manager on page 3-1 For more information about safe mode, refer to the Clock Manager chapter.

e following list describes the assertion steps for cold reset shown in the Cold Reset timing diagram:

1. Assert module resets

2. Wait for 32 cycles. Deassert clock manager cold reset.

3. Wait for 96 cycles (so clocks can stabilize).

4. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link.

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Warm Reset Assertion Sequence

Related Information

Cold and Warm Reset Deassertion Sequence on page 4-14

Warm Reset Assertion Sequence

e following list describes the assertion steps for warm reset shown in the Warm Reset Timing Diagram:

1. Optionally, handshake with the embedded trace router (ETR) and wait for acknowledge.

2. Optionally, handshake with the FPGA fabric and wait for acknowledge.

3. Optionally, handshake with the SDRAM controller, scan manager, and FPGA manager, and wait for

acknowledges.

4. Assert module resets (except the MPU watchdog timer resets when the MPU watchdog timers are the only request sources).

5. Wait for 8 cycles and send a safe mode request to the clock manager.

6. Wait for the greater of the nRST pin count + 256 stretch count, or the warm reset counter, or the clock

manager safe mode acknowledge, then deassert all handshakes except warm reset ETR handshake (which is deasserted by soware).

7. Proceed to the “Cold and Warm Reset Deassertion Sequence” section using the following link.

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Note:

Related Information

e nRST is a bidirectional signal that is driven out when a warm reset is generated in the chip.

Cold and Warm Reset Deassertion Sequence on page 4-14

Cold and Warm Reset Deassertion Sequence

e following list describes the deassertion steps for both cold and warm reset shown in the Cold Reset Timing Diagram and Warm Reset Timing Diagram:

1. Deassert L3 reset.

2. Wait for 100 cycles. Deassert resets for miscellaneous-type and debug (cold only) modules.

3. Wait for 200 cycles. Assert mpu_clkoff for CPU0 and CPU1.

4. Wait for 32 cycles. Deassert resets for MPU modules.

5. Wait for 32 cycles. Deassert mpu_clkoff for CPU0 and CPU1.

6. Peripherals remain held in reset until soware brings them out of reset.

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nTRST

nPOR

HPS

Arm DAP

Reset Manager

SoC Device

TMS

TCK

nRST

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Reset Pins

Figure 4-5: Reset Pins

Reset Pins

4-15

e test reset (nTRST), test mode select (TMS), and test clock (TCK) pins are associated with the TAP reset domain and are used to reset the TAP controller in the DAP. ese pins are not connected to the reset manager.

e nPOR and nRST pins are used to request cold and warm resets respectively. e nRST pin is an open drain output as well. A warm reset drives the nRST pin low. e amount of time the reset manager pulls

nRST low is controlled by the nRST pin count eld (nrstcnt) of the reset cycles count register (counts).

is technique can be used to reset external devices (such as external memories) connected to the HPS.

Reset Eects

e following list describes how reset aects HPS logic:

• e TAP reset domain ignores warm reset.

• e debug reset domain ignores warm reset.

• System reset domain cold resets ignore warm reset.

• Each module denes reset behavior individually.

Altering Warm Reset System Response

Registers in the clock manager, system manager, and reset manager control how warm reset aects the HPS. You can control the impact of a warm reset on the clocks and I/O elements.

Intel strongly recommends using provided libraries to congure and control this functionality.

e default warm reset behavior takes all clocks and I/O elements through a cold reset response. As your soware becomes more stable or for debug purposes, you can alter the system response to a warm reset. e following suggestions provide ways to alter the system response to a warm reset. None of the register bits that control these items are aected by warm reset.

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Reset Handshaking

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• Boot from on-chip RAM—enables warm boot from on-chip RAM instead of the boot ROM. When enabled, the boot ROM code validates the RAM code and jumps to it, making no changes to clocks or any other system settings prior to executing user code from on-chip RAM.

• Disable safe mode on warm reset—allows soware to transition through a warm reset without aecting the clocks. Because the boot ROM code indirectly congures the clock settings aer warm reset, Intel recommends that safe mode should only be disabled when the HPS is not booting from a ash device.

• Disable safe mode on warm reset for the debug clocks—keeps the debug clocks from being aected by the assertion of safe mode request on a warm reset. is technique allows fast debug clocks, such as trace, to continue running through a warm reset. When enabled, the clock manager congures the debug clocks to their safe frequencies to respond to a safe mode request from the reset manager on a warm reset. Disable safe mode on warm reset for the debug clocks only when you are running the debug clocks o the main PLL VCO and you are certain the main PLL cannot be impacted by the event which caused the warm reset.

• Use the osc1_clk clock for debug control—keeps the debug base clock (main PLL C2 output) always bypassed to the osc1_clk external clock, independent of other clock manager settings. When implemented, disabling safe mode on warm reset for the debug clocks has no eect.

Related Information

Clock Manager on page 3-1

For more information about safe mode, refer to the Clock Manager chapter.

Reset Handshaking

e reset manager participates in several reset handshaking protocols to ensure other modules are safely reset.

Before issuing a warm reset, the reset manager performs a handshake with several modules to allow them to prepare for a warm reset. e handshake logic ensures the following conditions:

• Optionally the ETR master has no pending master transactions to the L3 interconnect

• Optionally preserve SDRAM contents during warm reset by issuing self-refresh mode request

• FPGA manager stops generating conguration clock

• Scan manager stops generating JTAG and I/O conguration clocks

• Warns the FPGA fabric of the forthcoming warm reset

Similarly, the handshake logic associated with ETR also occurs during the debug reset to ensure that the ETR master has no pending master transactions to the L3 interconnect before the debug reset is issued. is action ensures that when ETR undergoes a debug reset, the reset has no adverse eects on the system domain portion of the ETR.

Reset Manager Address Map and Register Denitions

e address map and register denitions for the HPS-FPGA bridge consist of the following regions:

• Reset Manager Module

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FPGA Manager

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e FPGA manager in the hard processor system (HPS) manages and monitors the FPGA portion of the system on a chip (SoC) device. e FPGA manager can congure the FPGA fabric from the HPS, monitor the state of the FPGA, and drive or sample signals to or from the FPGA fabric.

Features of the FPGA Manager

e FPGA manager provides the following functionality and features:

• Full conguration and partial reconguration of the FPGA portion of the SoC device

• Drives 32 general-purpose output signals to the FPGA fabric

• Receives 32 general-purpose input signals from the FPGA fabric

• Receives two boot handshaking input signals from the FPGA fabric (used when the HPS boots from the FPGA)

• Monitors the FPGA conguration and power status

• Generates interrupts based on the FPGA status changes

• Can reset the FPGA

ISO 9001:2015 Registered

Page 97

Slave

Interface

Control

Block

Monitor

Block

Fabric

I/O

Block

Data

Block

Configuration

Slave

Interface

Interconnect

MPU

IRQ

FPGA Fabric

Control Block

nSTATUS

nCONFIG

nSTATUS

nCONFIG

CONF_DONE

f2h_gp[31:0]

h2f_gp[31:0]

f2h_boot_from_fpga_on_failure

f2h_boot_from_fpga_ready

CONFIG_IO Mode MSEL

nCE

INIT_DONE

nSTATUS

nCONFIG

CONF_DONE INIT_DONE CRC_ERROR CVP_CONF_DONE PR_READY PR_ERROR PR_DONE

DCLK DATA[31:0]

CONF_DONE PR_REQUEST

FPGA Manager

FPGA Portion

L4 Master Peripheral Bus

5-2

FPGA Manager Block Diagram and System Integration

Figure 5-1: FPGA Manager Block Diagram

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e register slave interface connects to the level 4 (L4) master peripheral bus for control and status register (CSR) access. e conguration slave interface connects to the level 3 (L3) interconnect for the microproc‐ essor unit (MPU) subsystem or other masters to write the FPGA conguration image to the FPGA control block (CB) when conguring the FPGA portion of the SoC device.

e general-purpose I/O and boot handshake input interfaces connect to the FPGA fabric. e FPGA manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device.

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e FPGA manager consists of the following blocks:

• Conguration slave interface—accepts and transfers the conguration image to the data interface.

• Register slave interface—accesses the CSRs in the FPGA manager.

• Data—accepts the FPGA conguration image from the conguration slave interface and sends it to the FPGA CB.

• Control—controls the FPGA CB.

• Monitor—monitors the conguration signals in the FPGA CB and sends interrupts to the MPU subsystem.

• Fabric I/O—reads and writes signals from or to the FPGA fabric.

Functional Description of the FPGA Manager

FPGA Manager Building Blocks

e FPGA manager has the two blocks - fabric I/O and monitor.

Related Information

FPGA Manager Address Map and Register Denitions on page 5-9

Functional Description of the FPGA Manager

5-3

Fabric I/O

e fabric I/O block contains the following registers to allow simple low-latency communication between the HPS and the FPGA fabric:

• General-purpose input register (gpi)

• General-purpose output register (gpo)

• Boot handshaking input register (misci)

ese registers are only valid when the FPGA is in user mode. Reading from these registers while the FPGA is not in user mode provides undened data.

e 32 general-purpose input signals from the FPGA fabric are read by reading the gpi register using the register slave interface. e 32 general-purpose output signals to the FPGA fabric are generated from writes to the gpo register. For more information about FPGA manager registers, refer to FPGA Manager

Address Map and Register Denitions on page 5-9.

e boot handshake input signals from the FPGA fabric are read by reading the misci register. e

f2h_boot_from_fpga_ready signal indicates that the FPGA fabric is ready to send preloader information

to the boot ROM. e f2h_boot_from_fpga_on_failure signal serves as a fallback in the event that the boot ROM code fails to boot from the primary boot ash device. In this case, the boot ROM code checks these two handshaking signals to determine if it should use the boot code hosted in the FPGA memory as the next stage in the boot process.

ere is no interrupt support for this block.

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Related Information

FPGA Manager Address Map and Register Denitions on page 5-9

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5-4

Monitor

e monitor block is an instance of the SynopsysGPIO IP (DW_apb_gpio), which is a separate instance of the IP that comprises the three HPS GPIO interfaces. e monitor block connects to the conguration signals in the FPGA. is block monitors key signals related to FPGA conguration such as INIT_DONE,

CRC_ERROR, and PR_DONE. Soware congures the monitor block through the register slave interface, and

can either poll FPGA signals or be interrupted. e mon address map within the FPGA manager register address map contains the monitor registers. For more information about FPGA manager registers, refer to

FPGA Manager Address Map and Register Denitions on page 5-9

You can program the FPGA manager to treat any of the monitor signals as interrupt sources. Independent of the interrupt source type, the monitor block always drives an active-high level interrupt to the MPU. Each interrupt source can be of the following types:

• Active-high level

• Active-low level

• Rising edge

• Falling edge

FPGA Conguration

You can congure the FPGA using an external device or through the HPS. is section highlights conguring the FPGA through the HPS.

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e FPGA CB uses the FPGA mode select (MSEL) pins to determine which conguration scheme to use. e MSEL pins must be tied to the appropriate values for the conguration scheme. e table below lists supported MSEL values when the FPGA is congured by the HPS.

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Table 5-1: Conguration Schemes for FPGA Conguration by the HPS

FPGA Conguration

5-5

Conguration

Scheme

FPP ×16

FPP ×32

(13)

Compres‐

sion

Feature

Disabled

Design

Security

Feature

AES Disabled

AES Enabled

Enabled Optional

Disabled

AES Disabled

AES Enabled

POR

Delay

MSEL[4..0]

(10)

(11)

cfgwdth cdratio Supports

Reconguration

Fast 00000 0 1 Yes

Standard 00100 0 1 Yes

Fast 00001 0 2 Yes

Standard 00101 0 2 Yes

Fast 00010 0 4 Yes

Standard 00110 0 4 Yes

Fast 01000 1 1 No

Standard 01100 1 1 No

Fast 01001 1 4 No

Standard 01101 1 4 No

Partial

Fast 01010 1 8 No

Enabled Optional

(12)

Standard 01110 1 8 No

HPS soware sets the clock-to-data ratio eld (cdratio) and conguration data width bit (cfgwdth) in the control register (ctrl) to match the MSEL pins. e cdratio eld and cfgwdth bit must be set before the start of conguration.

e FPGA manager connects to the conguration logic in the FPGA portion of the device using a mode similar to how external logic (for example, MAX II or an intelligent host) congures the FPGA in fast

(10)

For information about POR delay, refer to the Conguration, Design Security, and Remote System Upgrades in Arria V Devices.

(11)

Other MSEL values are allowed when the FPGA is congured from a non-HPS source. For information, refer to the Conguration, Design Security, and Remote System Upgrades in Arria V Devices.

(12)

You can select to enable or disable this feature.

(13)

When the FPGA is congured through the HPS, then FPPx32 is supported. Otherwise, if the FPGA is congured from a non-HPS (external) source, then FPPx32 is not supported. For more information refer to the Conguration, Design Security, and Remote System Upgrades in Arria V Devices.

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Altera Arria V Reference Manual

Contents

Introduction to the Hard Processor System

Features of the HPS

HPS Block Diagram and System Integration

HPS Block Diagram

Cortex-A9 MPCore

HPS Interfaces

HPS–FPGA Memory-Mapped Interfaces

Other HPS Interfaces

System Interconnect

SDRAM Controller Subsystem

SDRAM Controller

DDR PHY

On-Chip Memory

On-Chip RAM

Boot ROM

Flash Memory Controllers

NAND Flash Controller

Quad SPI Flash Controller

SD/MMC Controller

Support Peripherals

Clock Manager

Reset Manager

System Manager

Scan Manager

Timers

Watchdog Timers

DMA Controller

FPGA Manager

Interface Peripherals

EMACs

USB Controllers

I2C Controllers

UARTs

SPI Master Controllers

SPI Slave Controllers

GPIO Interfaces

CoreSight Debug and Trace

Endian Support

Introduction to the Hard Processor System Address Map

HPS Address Spaces

SDRAM Address Space

MPU Address Space

L3 Address Space

HPS Peripheral Region Address Map

Clock Manager

Features of the Clock Manager

Clock Manager Block Diagram and System Integration

L4 Peripheral Clocks

Functional Description of the Clock Manager

Clock Manager Building Blocks

PLLs

FREF, FVCO, and FOUT Equations

Dividers

Clock Gating

Control and Status Registers

Hardware-Managed and Software-Managed Clocks

Clock Groups

OSC1 Clock Group

Main Clock Group

Peripheral Clock Group

Flash Controller Clocks

SDRAM Clock Group

Resets

Cold Reset

Warm Reset

Safe Mode

Interrupts

Clock Usage By Module

Reset Manager

Reset Manager Block Diagram and System Integration

HPS External Reset Sources

Reset Controller

Module Reset Signals

Modules Requiring Software Deassert

Slave Interface and Status Register

Functional Description of the Reset Manager

Reset Sequencing

Cold Reset Assertion Sequence