Alinco DR-435MKIII, DR-135 Service Manual
D R - 1 3 5 / 4 3 5 M k l l l
Service Manual
CONTENTS
SPECIFICATIONS
GENERAL...............................................
TRANSMITTER
.......................................
RECEIVER.............................................
CIRCUIT DISCRIPTION
1) Receiver System DR-135..........................
2) Transmitter System DR-135.......................
3) PLL Synthesizer Circuit DR-135..................
4) Receiver System DR-435
.........
................
5) Transmitter System DR-435.......................
6) PLL Synthesizer Circuit DR-435..................
7) CPU and Peripheral Circuit
8) Power Supply Circuit
9) M38268MCA075GP (XA1130)
SEMICONDUCTOR DATA
1) NJM7808FA (XA0102)
2) TC4S66F (XA0115)
3) AN8010M (XA0119)
..................................
.................................
........................
...............................
....................
..............................
4) BU4052BCF (XA0236)..............................
5) TC4W53FU(XA0348)
6) TA31136FN (XA0404)
7) LA4425A (XA0410)
...............................
...............................
..................................
8) BR24L32FJ (XA0604Z).............................
9) S-80845ALMP (XA0620)
...........................
10) L88MS05TLL (XA0675).............................
11) S-816A50AMC (XA0925)...........................
12) LM2904PWR (XA1103).............................
13) LM2902PWR (XA1106).............................
14) MB15E07SR (XA1107)..............................
15) RA60H1317M1 (XA1108)..........................
16) S-AU82L (XA1142)
...................................
17) Transistor, Diode and LED Outline Drawing...
18) LCD Connection (TTR3626U P FD H N)
EXPLODED VIEW
1) Top and Front View
2) Bottom View
3) LCD Assembly
PARTS LIST
CPU Unit
.................................................
..................................
...........................................
........................................
.........
MAIN Unit DR-135....................................
MAIN Unit DR-435
............
......................
2
2
2
3,4
4
5
5,6
7
7,8
8
9
10-12
13
13
13
13
14
14
15
15
15
15
16
16
16
17
18
19
20
21
22
23
24
25,26
26-29
29-32
Mechanical Parts
Packing Parts
ACCESSORIES............................... 33
ACCESSORIES (SCREW SET)
TNC (EJ41U)
TNC (EJ41U) Packing Parts
DR-135 ADJUSTMENT
1) Adjustment Spot
2) VCO and RX Adjustment Specification.. 37
3) TXAdjustment Specification
4) RX Test Specification
5) TX Test Specification........................ 39
DR-435 ADJUSTMENT
1) Adjustment Spot
2) VCO and RX Adjustment Specification.. 41
3) TX Adjustment Specification
4) RX Test Specification
5) TX Test Specification........................ 44
PC BOARD VIEW
1) CPU Unit Side A DR-135 (UP0536)..... 45
2) CPU Unit Side B DR-135 (UP0536)..... 45
3) CPU Unit Side A DR-435 (UP0543)
4) CPU Unit Side B DR-435 (UP0543)
5) MAIN Unit Side A DR-135 (UP0536)
6) MAIN Unit Side B DR-135 (UP0536).... 47
7) MAIN Unit Side A DR-435 (UP0543)
8) MAIN Unit Side B DR-435 (UP0543).... 48
9) TNC Unit Side A (UP0402) (option)
10) TNC Unit Side A (UP0402) (option)
SCHEMATIC DIAGRAM
1) CPU Unit DR-135............................. 50
2) CPU Unit DR-435............................. 51
3) MAIN Unit DR-135
4) MAIN Unit DR-435
5) TNC Unit (option)............................. 54
BLOCK DIAGRAM
1) DR-135
.......................................... 55
2) DR-435.......................................... 56
..............................
................................... 33
.................................... , 34
..............................
..............................
...........................
...........................
33
..........
33
............. 35
36
..............
37
........................ 38
40
..............
42
........................ 43
.....
46
.....
46
....
47
....
48
.....
49
.....
49
52
53
A UNCO . n c
SPECIFICATIONS
■ General
Frequency coverage DR-135
118.000 - 135.995MHz (AM RX )
TMklll
136.000 ~ 173.995MHz ( RX )
144.000 ~ 147.995MHz ( TX )
DR-435
350.000 - 511.995MHz ( RX )
430.000 ~ 449.995MHz ( TX )
EMklll
Operating mode
Frequency resolution
Number of memory
Channels
Antenna impedance
Power requirement 13.8V DC + / -15% (11.7 - 15.8 V )
Ground method Negative ground
Current drain Receive
Transmit
Operating temperature
Frequency stability
Dimensions
Weight Approx. 1.0 Kg
144.000 - 145.995MHz ( RX,TX ) 430.000 ~ 439.995MHz ( RX.TX)
FM 16K0F3E ( Wide mode) 8K50F3E ( Narrow mode )
5 , 8.33 , 10 , 12.5 , 15 , 20 , 25 , 30 , 50 kHz
100
50ohm unbalanced
0.6 A ( m ax.) 0.4 A ( Squelched )
Approx. 12.0 A max.
-10 °C ~ 60°C
+- 2.5 ppm
142 (w)x40(h)x 174(d) mm
( 142 x 40 x 188 mm for projection included )
■ Transmitter
Output power Hi
Mid
Low
Modulation system
Maximum Frequency
deviation
Spurious emission -60 dB
Adjacent channel power - 60 dB
Noise and hum ratio - 40 dB ( W ide mode ) - 34 dB ( Narrow mode )
Microphone impedance
50 W 35 W
20 W 20 W
Approx. 5 W Approx. 5 W
Variable reactance frequency modulation
+- 5kHz ( Wide mode ) + / - 2.5kHz ( Narrow mode )
2 kohm
■ Receiver
Sensitivity
Receiver circuit Double conversion super-heterodyne
Intermediate frequency
Squelch sensitivity
Adjacent channel selectivity - 65 dB ( Wide mode ) - 55 dB ( Narrow mode )
Inter-modulation rejection
ratio
Spurious and image rejection
ratio
Audio output power
! NOTE : All specifications are subject to change without notice or obligation.
1st 21.7 MHz 2nd 450kHz 1st 30.85 MHz 2nd 455kHz
-14 dBu for 12 dB SINAD
-18 dBu
60 dB
70 dB
2.0 W ( 8ohm , 10%THD)
2
CIRCUIT DESCRIPTION
1) Receiver System DR-135
The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz
second IF.
1. Front End
2. IF Circuit
3. Demodulation Circuit
The received signal at any frequency in the 136.000MHz to 173.995MHz
range is passed through the low-pass filter (L116, L115, L114, L113, C204,
C203, C202, C216 and C215) and tuning circuit (L105, L104 and D105,
D104), and amplified by the RF amplifier (Q107). The signal from Q107 is
then passed through the tuning circuit (L103, L102, and variable capacitor
D103, D102) and converted into21.7MHz by the mixer (Q106). The tuning
circuit, which consists of L105, L104, variable capacitor D105 and D104,
L103, L102, variable capacitor D103 and D102, is controlled by the
tracking voltage from the VCO. The local signal from the VCO is passed
through the buffer (Q145), and supplied to the source of the mixer (Q106).
The radio uses the lower side of the super-heterodyne system.
The mixer mixes the received signal with the local signal to obtain the sum
of and difference between them. The crystal filter (XF102, XF101) selects
217 MHz frequency from the results and eliminates the signal of the
unwanted frequencies. The first IF amplifier (Q105) then amplifies the
signal of the selected frequency.
After the signal is amplified by the first IF amplifier (Q105), it is input to
pin 16 of the demodulator IC (IC108). The second local signal of21.25MHz
(shared with PLL IC reference oscillation), which is oscillated the external
oscillator X102 (VCTCXO), is input through pin 1 of IC108. Then, these
two signals are mixed by the internal mixer in IC108 and the result is
converted into the second IF signal with a frequency of 450kHz. The
second IF signal is output from pin 3 of IC108 to the ceramic filter (FL102
or FL101), where the unwanted frequency band of that signal is
eliminated, and the resulting signal is sent back to the IC108 through pin
5. The second IF signal input via pin 5 is demodulated by the internal
limiter amplifier and quadrature detection circuit in IC 108, and output as
an audio signal through pin 9.
4. Audio Circuit
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC120:A), and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and
amplified by the AF amplifier (IC120:B). The signal is then input to volume
(VR1). The adjusted signal is sent to the audio power amplifier (1C117)
through the pin 1 to drive the speaker.
3
5. Squelch Circuit
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of IC108 after it was been amplified IC120:Aand it is outputted from
pin 7 after the noise component was been, eliminated from the composed
band pass filter in the built in amplifier of the IC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L" level, AF
control signal is begin controlled and sounds is outputted from speaker.
6. AIR Band Reception
(T version only)
When the frequency is within 118.000 - 135.995MHz, Q113 automatically
turns on, pin 5 of IC 121 becomes “H” level and the condition becomes in
AM detection mode.
The receiver signal passed through the duplexer is let to the antenna
switch (D107, D101). After passing through the band-pass filter, the signal
is amplified by RF amplifier Q112. Secondly the signal is mixed with the
signal from the first local oscillator in the first-mixer Q106, then converted
into the first IF. Its unwanted signal is let to pin 16 of IC108. Then
converted into the second IF. And is demodulated by AM decoder of Q118,
and is output from Q108 as the AF signal.
7. WIDE/NARROW
Switching circuit
The second IF 450kHz signal which passes through filter FL101 (wide)
and FL102 (narrow) during narrow, changes its width using the width
control switching D116 and D115.
2) Transmitter System DR-135
1. Modulator Circuit
The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
IC114:D and C consists of two operational amplifiers; one amplifier (pin
12,13 and 14) is composed of pre-emphasis and IDC circuit and the other
(pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency
deviation is obtained by VR107. And input to the signal switch (IC113)
(9600 bps packet signal input switch) and input to the cathode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
2. Power Amplifier Circuit
3. APC Circuit
4
The transmitted signal is oscillated by the VCO, amplified by the younger
amplifier (Q115), and input to the final power module (IC110). The signal is
then amplified by the final power module (IC110) and led to the antenna
switch (D110) and low-pass filter (L113, L114, L115, L116, C215, C216,
C202, C203 and C204), where unwanted high harmonic waves are
reduced as needed, and the resulting signal is supplied to the antenna.
Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:A, 1C114:B), then it controls the APC voltage supplied to
final power module IC110 to fix the transmission power.
3) PLL Synthesizer Circuit DR-135
1.PLL
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in IC116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
2. Reference Frequency
Circuit
3. Phase Comparator Circuit
4. PLL Loop Filter Circuit
5. VCO Circuit
The reference frequency appropriate for the channel steps is obtained by
dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it
is 6.25 kHz, the 12.5 kHz channel step is used.
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the IC116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which is
obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the
reference frequency and the VCO output frequency, the charge pump
output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL loop filter and input to the input to the variable
capacitor of the VCO unit for oscillation frequency control.
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D122 and D123). This change
the oscillation frequency, which is amplified by the VCO buffer (Q134,
Q145) and output from the VCO area.
6. VCO Shift Circuit
During transmission or the AIR band Reception (118 ~ 136 MHz), the VCO
shift circuit turns ON Q138, change control the capacitance of L123 and
safely oscillates the VCO by means of H signal from pin 42 of IC1.
4) Receiver System DR- 435
The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455kHz
second IF.
1. Front End
The received signal at any frequency in the 430.000MHz to 439.995MHz
range is passed through the low-pass filter ( L115, L114, L116, C204,
C203, C202, C216 and C215) and amplified by the RF amplifier (Q107).
The signal from Q107 is then passed through the BPF circuit (L103, L102)
and converted into 30.85MHz by the mixer (Q106). The local signal from
the VCO is passed through the buffer (Q134, Q145), and supplied to the
source of the mixer (Q106). The radio uses the lower side of the
super-heterodyne system.
5
2. IF Circuit
The mixer mixes the received signal with the local signal to obtain the sum
of and difference between them. The crystal filter (XF101) selects 30.85
MHz frequency from the results and eliminates the signal of the unwanted
frequencies. The first IF amplifier (Q105) then amplifies the signal of the
selected frequency.
3. Demodulation Circuit
4. Audio Circuit
5. Squelch Circuit
After the signal is amplified by the first IF amplifier (Q105), it is input to
pin16 of the demodulator IC (IC108). The second local signal of
30.395MHz (Crystal oscillator) is input through pin 1 of IC108. Then, these
two signals are mixed by the internal mixer in IC108 and the result is
converted into the second IF signal with a frequency of 455kHz. The
second IF signal is output from pin 3 of IC108 to the ceramic filter (FL101
or FL102), where the unwanted frequency band of that signal is
eliminated, and the resulting signal is sent back to the IC108 through pin
5.
The second IF signal input via pin 5 is demodulated by the internal limiter
amplifier and quadrature detection circuit in IC 108, and output as an
audio signal through pin 9.
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier
(IC120:A), and switched by the signal switch IC (IC111) and then input it to
the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the
de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and
amplified by the AF amplifier (IC120:B). The signal is then input to volume
(VR1). The adjusted signal is sent to the audio power amplifier (IC117)
through the pin 1 to drive the speaker.
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of IC108 after it was been amplified !C120:A and it is outputted from
pin 7 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the IC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes “L” level, AF
control signal is begin controlled and sounds is outputted from speaker.
6. WIDE/NARROW
Switching circuit
6
The second IF 455kHz signal which passes through filter FL101 (wide)
and FL102 (narrow) during narrow, changes its width using the width
control switching D116 and D115.
5) Transmitter System DR- 435
1. Modulator Circuit
2. Power Amplifier Circuit
3. APC Circuit
The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
IC114:D and C consists of two operational amplifiers; one amplifier (pin
12,13 and 14) is composed of pre-emphasis and IDC circuit and the other
(pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency
deviation is obtained by VR107. And input to the signal switch (IC113)
(9600 bps packet signal input switch) and input to the cathode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the drive
amplifier (Q138) and younger amplifier (Q115), and input to the final
power module (IC110). The signal is then amplified by the final power
module (IC110) and led to the antenna switch (D110) and low-pass filter
(L116, L114, L115, C215, C216, C202, C203 and C204), where unwanted
high harmonic waves are reduced as needed, and the resulting signal is
supplied to the antenna.
Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:A, IC114:B), then it controls the APC voltage supplied to the
final power module IC110 to fix the transmission power.
6) PLL Synthesizer Circuit DR- 435
1. PLL
2. Reference Frequency
Circuit
3. Phase Comparator Circuit
4. PLL Loop Filter Circuit
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in IC116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
The reference frequency appropriate for the channel steps is obtained by
dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it
is 6.25 kHz, the 12.5 kHz channel step is used.
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase
comparator in the 1C116 compares the phase of the frequency from the
VCO with that of the comparison frequency, 5 or 6.25 kHz, which is
obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the
reference frequency and the VCO output frequency, the charge pump
output (pin 5) of IC116 generates a pulse signal, which is converted DC
voltage by the PLL loop filter and input to the input to the variable
capacitor of the VCO unit for oscillation frequency control.
7
5. VCO Circuit
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired
frequency. The frequency control voltage determine in the CPU (IC1) and
PLL circuit is input to the variable capacitor (D122 and D123). This change
the oscillation frequency, which is amplified by the VCO buffer (Q134,
Q145) and output from the VCO unit
7) CPU and Peripheral Circuits
1. LCD Display Circuit
2. Dimmer Circuit
3. Reset and Backup
4. S (Signal) Meter Circuit
5. DTMF Encoder
The CPU turns ON the LCD via segment and common terminals with 1/4
the duty and 1/3 the bias, at the frame frequency is 64 Hz.
The dimmer circuit makes the output of pin 13 of CPU (JC1) into “H” level
at set mode, so that Q9 and Q3 will turn ON to make the lamp control
resistor R84 short and make its illumination bright. But on the other hand,
if the dimmer circuit makes pin 13 Into “L” level, Q9 and Q3 will turn OFF,
R84's illumination will become dimmer as its hang on voltage falls down in
the working LED (D11, D2, D5, D3 and D6).
When the power from the DC cable increases from Circuits 0 V to 2.5 V or
more, “H" level reset signal is output from the reset IC (IC4) to pin 33 of
the CPU (IC1), causing the CPU to reset. The reset signal , however,
waits at 100, and dose not enter the CPU until the CPU clock (X1) has
stabilized.
The DC potential of IF IC is input to pin 1 of the CPU (IC1), converted from
an analog to a digital signal, and displayed as the S-meter signal on the
LCD.
The CPU (IC1) is equipped with an internal DTMF encoder. The DTMF
signal is output from pin 10, through R35, R34 and R261 (for level
adjustment), and then through the microphone amplifier (IC114:A), and is
sent to the variable capacitor of the VCO for modulation. At the same time,
the monitoring tone passes through the AF circuit and is output from the
speaker.
6. Tone Encoder
7. DCS Encoder
8. CTCSS, DCS Decoder
8
The CPU (IC1) is equipped with an internal tone encoder. The tone signal
(67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor
(D122 and D123) of the VCO for modulation.
The CPU (IC1) is equipped with an internal DCS code encoder. The code
(023 to 754) is output from pin 9 of CPU to the volt a ge con trol pin of
VCTCXO (X102) of the PLL reference oscillator. When DCS is ON, DCS
MUTE circuit (Q126-ON, Q133-ON, Q132-OFF) works. The modulation
activates in X102 side only.
The voice band of the AF output signal from pin 1 of IC120:A is cut by
sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin
4 of CPU. The input signal is compared with the programmed tone
frequency code in the CPU. The squelch will open when they match.
During DCS, Q108 is ON, C419 is working and cut off frequency is
lowered.
8) Power Supply Circuit
When power supply is ON, there is a "L" signal being inputted to pin 39 (PSW) of CPU which enables the CPU to
work. Then, “H” signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch control Q8
and Q7 which turns the 5VS ON. 5VS turns ON the PLL IC (1C116), main power supply switch Q127 and Q122,
AF POWER IC117 and the 8V of AVR (IC115). During reception, pin 29 (R5)of CPU outputs “H” level, Q124 is ON,
and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs “L” ievei which is
reverse by Q11 so that the output in Q128 will be “H” level, Q123 is ON, and the transmission circuit is supplied by
8 V. Or, in the case when the condition of PLL is UNLOCK, “H” level is outputted from pin 14 of PLL IC, UNLOCK
switch Q129 is ON, transmission switch Q128 is OFF which makes the transmission to stop.
1. ACC External Power Supply Terminal
When optional power supply cord EDC-37 etc. is connected to the
external power supply terminal JK101, with ACC power supply ON, switch
Q101 will turn ON, 5 V of AVR IC101 pin 2 (STB) becomes “L” which
makes CSV to turn ON. With this, it can turn the power supply of the radio
ON.
9
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/SCLK22/AN3
P62/SCLK21/AN2
P61/S0UT2/AN1
P60/SIN2/AN0
P57/ADT/DA2
P56/DA1
P55/CNTR1
P54/CNTR0
P53/RTP1
P52/RTP0
P51/PWM1
P50/PWM0
P47/SRDYT
P46/SCLK1
P45/TXÜ
P44/RXD
P43/s¿/T0UT
P42/INT2
P41/JNT1
P40
P77
i— c7><r>i— i— 3 S 3 : 3 w m 0 0 n n n 0 n n c 5 G 5 0 —>■ —*■ —
- ‘ - ‘ M K ) W O - ‘ N j W ( / ) ' n O O - ‘ N W J S . U 1 0 1 ' J ( » ( 0 O - ‘ M
< < co o oo < 3 3 'C m m r n rn m m m r n m rn £ 7 > O C T
-, -, ~ C f l W M M M W M M M W m m m
lllllîîîîll ÎÎÎÎÎÎÎÎÎÎÎÎÎ
-£
-[I
-[I
-GE
-Œ
■Œ
“U
o
CO
oo
ho
o>
-E
-1
-QS
oo
o
r~
o
— i
tn
CD
"Ö
o
CO C/ 0 Go
V
----
X
o
SEG13
•SEG14
SEG15
■SEG16
•SEG17
-P30/SEG18
■P31/SEG19
-P32/SEG20
■P33/SEG21
■P34/SEG22
•P35/SEG23
•P36/SEG24
-P37/SEG25
■P00/SEG26
-PÛ1/SEG27
■P02/SEG28
■P03/SEG29
-P04/SEG30
-P05/SEG31
■P06/SEG32
•P07/SEG33
-P10/SEG34
-P11/SEG35
■P12/SEG36
-P13/SEÖ37
o
“0
<
m
C D*
O
o
D
ZJ
< 0
o
I- +
o
3
9) M38268MCL075GP (XA1130)
O
"0
c
m n m t i t i n i m m m
“U "O "O "O "□ "O
—J ■— I -~J
O) U1 A CO M ->
- 0 ^ X X X X < - D -D"D-D-a-D'D'D-D-DT3-0
-~ JmO < T 3 — 1 —*■ —L
O C/O — O Z C M — I 0 > a i - N C J M - ‘ 0 ' - J 0 5 0 1 * .
\ m : z c —i \ \
— —ij —t c o co
z m m
— o o
o co co
co oo
No. Terminal Signal I/O Description
1 P67/AN7
2 P66/AN6
SMT
SQL
I
S-meter input
I Noise level input for squelch
3 P65/AN5 BAT I Battery voltage input
4 P64/AN4 TIN I CTCSS tone input / DCS code input
5 P63/SCLK22/AN3 BP1 I Band plan 1
P62/SCLK21/AN2 BP2 I Band plan 2
6
7 P61/SOUT2/AN1 DCSW 0 DCS signal mute
8 P60/S1N2/AN0
9
10
P57/ADT/DA2 TOUT 0
P56/DA1 DOUT
RE2 I
0
Rotary encoder input
CTCSS tone output / DCS tone output
DTMF output
11 P55/CNTR1 SCL 0 Serial clock for EEPROM
12 P54/CNTR0
TBST
0 Tone burst output
13 P53/RTP1 BP4 I/O Band plan 4 / lamp dimmer HI / LOW switch
14 P52/RTP0 MUTE I/O Microphone mute / Security alarm SW
15 P51/PWM1 CLK o Serial clock output for PLL, scramble
16 P50/PWM0 DATA I/O Serial data output for PLL scramble / PLL unlock signal input
17 P47/SRDY1 TSTB I/O Trunking board detection / Strobe signal to trunking board
18 P46/SCLK1 STB o Strobe for PLL IC
19 P45/TXD UTX o UART data transmission output
20 P44/RXD RTX I UART data reception output
21 P43/cp/TOUT BEEP I/O Beep tone / Band plan 3
22 P42/INT2 SEC I Security voltage input
23 P41/INT1 RE1 I Rotary encoder input
24 P40 DSQ I Digital squelch input
25 P77 PTT I PTT input
26
P76 SSTB 0
Strobe signal to scramble IC / Security mode
27 P75 W/N 0 Wide Narrow SW
28 P74 T5 o TX power ON / OFF output
29 P73 R5 0 RX power ON / OFF output
30 P72 SQC 0 SQL ON / OFF
31 P71 C/S 0 Digital scramble ON / OFF
32 P70/INT0 BU I Backup signal detection input
33 RESET RESET I Reset input
34 XCIN Xcin
35 XCOUT Xcout
36 XIN Xin
37 XOUT Xout
38 VSS GND
- -
- -
-
Main clock input
-
Main clock output
-
CPU GND
39 P27 PSW I Power switch input
40 P26 SDA o Serial data for EEPROM
41 P25 CSC 0 C5V power ON / OFF output
42 P24 AIR 0 Air band SW / Tx middle power
43 P23
LOW
0
Tx low power
44 P22 EXP 0 Trunking / Packet data SW
45
46
47
48
49
50
P21
P20 SW5
P17
P16
P15/SEG39
P14/SEG38
SW6
SW4
SW3 I Key sw 3 (MHz)
SW2 I
SW1 I
I
Key sw 6 (SQL)
I Key sw 5 (CALL)
I Key sw 4 (TSQ)
Key sw 2 (V/M)
Key sw 1 (FUNC)
1 1
No. Terminal Signal
51 P13/SEG37 DOWN
52 P12/SEG36
53 P11/SEG35
54 P10/SEG34
55
56
P07/SEG33 S33 0
P06/SEG32
57 P05/SEG31
58 P04/SEG30
59 P03ÍSEG2Q
60 P02/SEG28
61 P01/SEG27
62 P00/SEG26
63 P37/SEG25
64 P36/SEG24
65 P35/SEG23
66
P34/SEG22
67 P33/SEG21
68
69
70
71
72
P32/SEG20
P31/SEG19 S19 o
P30/SEG18 S18 0
SEG17
SEG16
73 SEG15
74
SEG14
75 SEG13
76
77
SEG12
SEG11
78 SEG10
79 SEG9
80
81
SEG8
SEG7
DUD
SCR
UP
S32
S31 0
S30
S29 o
S28 0
S27
S26
S25
S24
S23
S22
S21
S20
S17
S16
S15 0
S14
S13 0
S12
S11
S10
S9 0
S8
S7
82 SEG6 S6 0
83
SEG5
84 SEG4
85
SEG3
86 SEG2
87 SEG1
88
SEGO
89 VCC
90 VREF
91 AVSS
S5
S4
S3
S2
S1
SO
VDD - CPU power terminal
Vref -
Avss -
92 COM3 COM3 0
93 COM2 COM2 0
94 COM1
COM1
95 COMO COMO 0
96 VL3
97 VL2
98 C2
99 C1
100
VL1 VL1 I LCD power supply
VL3
VL2
I
C1
I/O Description
I Mic down input
Digital unit detect
I
Scramble IC ready signal / PTT input for 9600bps
I
Mic up input
I
0
0
0
0
0
0
0
0
0
o
0
0
LCD segment signal
0
0
0
0
o
0
0
0
0
0
0
0
AD converter power supply
AD converter GND
LCD COM3 output
LCD COM2 output
LCD COM1 output
0
LCD COMO output
-
LCD power supply
-
LCD power supply
-
-
-
-
12
SEMICONDUCTOR DATA
1) NJM7808FA (XA0102)
8V (1 A) Voltage Regulator
1. INPUT
2. COMMON
3. OUTPUT
1 2 3
2) TC4S66F (XA0115)
Bilateral Switch
5 4
B
______
a
C 9
b b b
1 2 3
1. IN/OUT
2. OUT/IN
3. VSS
4. CONT
5. VDD
5
a
a
□ Ü b
1 2 3
□
r p
CONT
Function (IN-OUT)
L Disconnect (Hi Z)
H Connect (290ohm typ.)
3) AN8010M (XA0119)
10V (50mA) Voltage Regulator
■< *
O
u
U
1
2 3
*
u
1. OUTPUT
2. COMMON
3. INPUT
4) BU4052BF (XA0236)
Analog Multiplexer / De-multiplexer
YO \T_
Y2 [T
Y COMMON [ T
Y3 |T
Y1 [ T
INHIBIT [ T
VEE |T
vss [T
YO
Y2
Y
IN/OUT
X
Y3
IN/OUT
Y1 XO
INM X3
VEE
B
X2
XI
A
le] VDD
1X 2
7^ XI
j3 ] X COMMON
I 2] XO
J j] X3
10] A
T ] B
Vin
[4-1
"i
1
&
s
I
INHIBIT A B
L L
COMMON
L
L H L X1 Y1
L L
L
H
H
H . H X3 Y3
* *
X Y
Don’t care
ON SWITCH
XO YO
X2 Y2
NONE
13
5) TC4W53FU (XA0348)
Multiplexer / De-multiplexer
8 7 6 5
P P P P
1. COMMON
2. INH
3. VEE
4. VSS
5. A
6. ch 1
7. ch 0
8. VDD
1 2 3 4
6) TA31136FN (XA0404)
Narrow Band FM IF IC
15 14 13 12 11 10 9
n m h n
1.0SCIN
2. OSC OUT
3. MIX OUT
4. Vcc
5. IF IN
6. DEC
7. FILOUT
8. FILIN
Control input
Don’t’t care
9. AF OUT
10. QUAD
11. IF OUT
12. RSSI
13. N-DET
14. N-REC
15. GND
16. MIX IN
INH
A
ON channel
L L ch 0
L H
H
*
ch 1
NONE
1 2 3 4 5 6 7 8
14
7) LA4425A (XA0410)
5W Audio Power Amplifier
1. Input
LA4425
* * *
1 2 3 4 5
8 ) BR24L32FJ (XA0604Z)
32K-Bit EEPROM
2. Small signal GND
3. Large signal GND
4. Output
5. Vcc
Test Circuit
8 7 6 5
n R R R
L32
o * * * * *
2. A1
3.A2
4. Vss
5. SDA
6. SCL
7. WP
r m
1 2 3 4
8. Vcc
9) S-80845ALMP (XA0620)
4.5V Voltage Detector
5
f l .
B 6 6 *
f l
4
1. GND
2. Vin
3. Vout
4. NC
5. NC
b b b
1 2 3
10) L88MS05TLL (XA0675)
Name
A0...A2
Function
User Configurable Chip Select
Vss Ground
SDA
SCL
WP
Vcc
Serial Address / Data / I/O
Serial Clock
Write Protect Input
+2.5 ~ 6.0V Power Supply
5V (500mA) Voltage Regulator with On/Off Function
1. Vin
2. STB
3. GND
4. Cn
5. Vout
G N D
15
11) S-816A50AMC (XA0925)
External Transistor Type 5V Voltage Regulator with On/Off Function
5
n
4
n
1. EXT
2. Vss
B A Z *
3. ON/OFF
4. Vin
Ö d d
1 2 3
5. Vout
12) LM2904PWR (XA1103)
Dual Operational Amplifiers
8 7 6 5
1. Output A
2. Inverting Input A
•*
o
*
CNJ
— I
o
3. Non-inverting Input A
4. GND
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Vcc
w n
1 2 3
13) LM2902PWR (XA1106)
Quad Operational Amplifiers
1413121110 9 8
1. Output A
2. Inverting Input A
3. Non-inverting Input A
4. Vcc
5. Non-inverting Input B
6. Inverting Input B
7. Output B
8. Output C
9. Inverting Input C
10. Non-inverting Input C
2 3 4 5 6 7
11. GND
12. Non-inverting Input D
13. Inverting Input D
14. Output D
16
14) MB15E07SR (XA1107)
PLL Synthesizer
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7
OSC IN
PS
LE
Data
Clock
Xfin
fin
Reference
Oscillator
In term itte n t
mods co n trol
(power save)
1 - b i t
co n tro l latch
Prescaler
32/33
64/65
Binary 14-bit
reference counter
14-bit latch
Sff
1.0SCIN
2. N. C.
3. Vp
4. Vcc
5. Do
6. GND
7. Xfin
8. fin
Sff FC LDS CS
4-bit latch
19-bit shift register
7-bit latch 11-bit latch
Binaly 7-bit
swallow
counter
Binary 11-bit
programmable
counter
9. Clock
10. Data
11. LE
12. PS
13. N. C.
14. LD / fout
15. N. C.
16. N. C.
fp
fr
Phase
comparator
Lock
detector
LD/fr/fp
selector
Charge pump
LD/fout
Vp
Do
VCC
GND
Parameter
Symbo
1
Power supply voltage Vcc
Power supply current
LPF supply voltage
Icc
Vp
Local oscillator input ievel Vf in
Local oscillator input
frequency
fin
Xin input level Vxin
Xin input frequency
Fxin
( Vcc = 2.7 to 5.0V, Ta = -40°C to +85oC )
Condition Min. Typ. Max. Unit
-
2500MHz
Vcc=A/p=3.75V
-
100MHz to 300MHz
300MHz to 2500MHz
-
-
-
2.7 3.75
8.0 mA
Vcc
-
-6
-15
100 2500 MHz
0.5
3
F 40
5.0
V
5.5 V
+2
+2
dBm
Vcc Vp-p
MHz
15) RA60H1317M1 (XA1108)
144 ~ 146MHz 60W RF Power Module
OUTLINE DRAWING
BLOCK DIAGRAM
© RF Input (Pin) ^
(D Gate Voltage (VGG), Power Control
(3) Drain Voltage (VDD), Battery
(4) RF Output (Pout)
(D RF Ground (Case)
ABSOLUTE MAXIMUM RATING ( Tc = 25 °C, unless otherwise noted )
Symbol
VDD
VGG Gate Voltage
IDD Drain Current 15 A
Pin
Pout
Tease (OP)
Tstg
ELECTRICAL CHARACTERISTICS (Tc = 25 °C, unless otherwise noted )
Symbol
f
Pout Output Power
v T
2fo
Pin
IGG
-
-
Drain Voltage
Input Power f = 135- 175 MHz, Pin=50mW
Output Power 80
Operation Case Temperature
Storage Temprature
Frequency Range 135
Total Efficiency
2na Harmonic -50 dBc
Input VSWR
Gate Current
Stability
Load VSWR
Tolerance
Parameter Conditions
VGG < 5V, ZG = ZL = 50ohm
VDD < 12.5V, Pin=50mW
ZG = ZL = 50ohm
ZG = ZL = 50ohm
Parameter
VDD = 12.5V
VGG = 5V
Pin = 50mW
VDD=10.0-15.2V, Pin=25-70mW,
Pout<70W (VGG control), Load
VSWR=3:1
VDD=15.2V, Pin=50mW, Pout=60W
(VGG control),
Load VSWR=8:1
Conditions
Ratings
17
5.5 V
100 mW
-30 to +110
-40 to +110 °C
Ratings
Min
60 W
45
No parasitic
oscillation
No degradation or
destroy
Typ
1 mA
Max
175
3:1
Unit
V
W
°C
Unit
MHz
%
-
-
18
16) S-AU82L (XA1142)
430 ~ 450MHz 60W RF Power Module
BLOCK DIAGRAM
(D RF Input (Pin)
(2) Gate Voltage (VGG), Power Control
(D Drain Voltage (VDD), Battery
(4) RF Output (Pout)
(D RF Ground (Frange)
ABSOLUTE MAXIMUM RATING ( Tc = 25°C, unless otherwise noted )
Symbol Parameter Conditions Ratings
VDD Drain Voltage VGG < 5V, Pi = 50mW, Po < 60W
VGG
IDD
Pin
Pout
Tease (OP) Operation Case Temperature
Tstg
Gate Voltage
Drain Current 15 A
input Power
Output Power
Storage Temprature
VDD < 12.5V, Pin=50mW
VDD < 12.5V, VGG < 5V
12.5V < VDD < 16.5V, VGG = 5V,
Pi = 50mW
16.5 V
5.5 V
100
80 W
-30 to+100 °C
-40 to +100 °C
ELECTRICAL CHARACTERISTICS ( Tc = 25 °C, unless otherwise noted )
Symbol
f Frequency Range 400 470 MHz
Pout
n T
2fo 2na Harmonic
Pin
IGG
-
-
Parameter Conditions
Output Power
Total Efficiency
Input VSWR
Gate Current
Stability
Load VSWR
Tolerance
VDD = 12.5V
VGG = 5V
Pin = 50mW
ZL = 50ohm
VDD=10.5-16.5V, VGG=0-5V, Pin=50mW,
Pout<60W (VGG control), Load VSWR=3:1
ALL PHASE
VDD=10.5-16.5V, VGG=0-5V, Pin=50mW,
Pout=60W (VGG control), Load
VSWR=20:1 ALL PHASE
Ratings
Min
Typ
60 W
40
1 mA
All sprious output
than 60dB bellow
desired signal
No degradation
Unit
MW
Max
-30 dBc
3.0
Unit
%
-
-
19
Loading...