Alinco DJ-V446 Service Manual

DJ-V446

S er vi ce M an u a l

CONTENTS

SPECIFICATIONS

General.......................................................................2

Transmitter................................................................2

Receiver

CIRCUIT DESCRIPTION

1) Receiver System...............................................3,4

2) Transmitter System.............................................4

3) PLL Synthesizer Circuit......................................5

4) CPU & Peripheral Ciruits.................................5,6

5) M38268MCA-077GP(XA1169)

SEMICONDUCTOR DATA

1) NMJ2070MT1 (XA0210)

2) S24CS64A01-J8T1 G(XA1117)........................10

3) M62429FP/CF0J(XA1118)

4) LM2902PWR(XA1106)

5) TA31136FN(EL)(XA0404)

6) S80845CLNB-B66-T2G(XA1120)

7) MB15E07SR(XA1107)

8) XC6202P502M R(XA1119)

9) Transistor, Diode and LED Outline Drawing

10) LCD Connection(EL0059)

.................................................................... 2

.....................

....................................10

..............................

.....................................

...............................

...................

......................................

..............................

............................

....

7-9

11
11
12
12
13
14
15
15

EXPLODED VIEW

1) Front View

2) Rear View........................................................... 17

PARTS LIST

MAIN Unit.........................................................18-23

Mechanical Unit................................................23,24

Packing Unit........................................................... 24

ADJUSTMENT

1) Required Test Equipment..........................25,26

2) Preparation.........................................................26

3) Adjustment Mode.......................................27-32

4) Re-assembly.......................................................32

PC BOARD VIEW

MAIN SIDE A .........................................................33

MAIN SIDE B .........................................................33

SCHEMATIC DIAGRAM

BLOCK DIAGRAM...........................................35

..........................................................16

...............................

34

AL IN CO , Inc

SPECIFICATIONS

General

Frequency range:

Modulation:
Memory channel:

Ant. impedance:

Frequency stability:
Mic impedance:

Supply voltage:
Current consumption:

Temperature range:

Ground:

Dimension (projections excluded):

Weight:

Sub audible Tone (CTCSS):

TX/RX 446.00625-446.09375MHz
(12.5kHz step, 1~8ch)
8K50F3E (FM)
200 channels
50 Q unbalanced
±2.5ppm
2k Q

DC 7.0-16.0V (EXT DC-IN)
600mA (typical) Transmit
250mA (typical) Receive at 500mW
70mA (typical) Standby
26mA (typical) Battery save on

External DC: -10°C~+60°C (+14°F~+140°F)

Battery packs: -10°C~+45°C (+14°F~+113°F)

Negative ground
58(W) x 110(H) x 36.4(D)mm
(2.28"(W) x 4.33"(H) x 1,43"(D))
(with EBP-65)
Approx. 280g (9.9oz)
(with EBP-65 and antenna)
encoder/decoder installed (39 tones)

Transmitter

Power output:
Modulation:

Spurious emission:

Max deviation:
Mic. impedance:

Receiver

System:
Sensitivity:

Intermediate frequency:

Selectivity:

AF output:

Max. 500mW
Variable reactance

-60dB or less
±2.5kHz
2k Q

Double-conversion super heterodyne

-11 .OdB ju (0.28 ju V)or less

1st IF 38.85MHz 2nd IF 450kHz

-6dB: 6kHz or more

-60dB: 13kHz or less
500mW (MAX)
400mW (8 Q, 10% distortion)

2

CIRCUIT DESCRIPTION

1) Receiver System

The receiver system is a double superheterodyne system with a 38.85 MHz first IF and a 450 kHz second
IF.

1. Front End

The received signal at any frequency in the 446.00625- to

446.09375-MHz (E version : 144.000- to 145.995-MHz) range is
passed through the low-pass filter (L101, L102, L103, L113, C108,
C120, C121, C124, C125, C126, C127 and C176) and ATT
(Attenuator) circuit (Q120, R161, R187 and D112), and tuning circuit
(C192, C193, C215, C216, D115, D116, L125 and L126), then
amplified by the RF amplifier (Q114). The signal from Q114 is then
passed through the tuning circuit (C200, C201, C219, C220, D117,
D118, L128 and L129) and converted into 21.7 MHz by the mixer
(Q116). The tuning circuit, which consists of C192, C193, C215,
C216, L125, L126, variable capacitance diodes D115 and D116 and
C200, C201, C219, C220, L128, L129, variable capacitance diodes
D117 and D118, is controlled by the tracking voltage from the CPU
so that it is optimized for the reception frequency. The local signal
from the VCO is passed through the buffer (Q113), and supplied to
the source of the mixer (Q116). The radio swithes the lower and
upper system at 420.000MHz : the lower side for the frequency up to

419.995 MHz and upper side for 420.000MHz and up.

2. ATT (Attenuator) Circuit

This circuit is used in case the receiving signal is disturbed by
interfering signal(s), attenuating the receiving signal(s) to reduce the
interference. CPU (IC109)’s pin 10 outputs a DC current to drive
Q120, controlling D112’s resistance to adjust the attenuation value.

3. IF Circuit

The mixer(Q116) mixes the received signal with the local signal to
obtain the sum of and difference between them. The crystal filter
(FL101) selects 38.85 MHz frequency from the results and eliminates
the signals of the unwanted frequencies. The first IF amplifier (Q119)
then amplifies the signal of the selected frequency. After the signal is
amplified by the first IF amplifier (Q119), it is input to pin 16 of the
demodulator IC (IC103).The second local signal of 38.85 MHz, which
is oscillated by the internal oscillation circuit in IC103 and output of
tripler circuit (L123, C202, C191, L122, Q115), is input through pin 1
of IC103. Then these two signals are mixed by the internal mixer in

IC103 and the result is converted into the second IF signal with a

frequency of 450kHz. The second IF signal is output from pin 3 of

IC103 tothe ceramic filter (FL103), where the unwanted frequency

band of that signal is eliminated, and the resulting signal is sent back
to the IC103 through 5 pins.

4. Demodulator Circuit

The second IF signal input via pin 5 is demodulated by the internal
limiter amplifier and Quadrature detection circuit in IC103, and output
as an audio signal through pin 9.

3

5. Audio Circuit

6. Squelch Circuit

2) Transmitter System

1. Modulator Circuit

2. Power Amplifier Circuit

3. APC Circuit

The audio signal from pin 9 of IC103 is compensated to the audio
frequency characteristics in the de-emphasis circuit (R223, R224,
C241, C242) and amplified by the AF amplifier (Q196). The signal is
then input to pin 1 of the electronic volume (IC107) for volume
adjustment, and output from pin 2. The adjusted signal is sent to the
audio power amplifier (IC106) through pin 2 to drive the speaker.

Part of the audio signal from pin 9 of IC103 is amplified by the noise

filter amplifier and the internal noise amplifier in IC103. The desired

noise of the signal is output through pin 14 of IC103 and input to pin

2 of CPU (IC109).

The audio signal is converted to an electric signal in either the

internal or external microphone, and input to the microphone

amplifier (IC102).

IC102 consists of four operational amplifiers; 1st amplifier (pins 1, 2,

and 3) is composed of high-pass filter, 2nd amplifier (pins 12, 13, and

14) is composed of pre-emphasis and IDC circuits, 3rd amplifier (pins
8, 9, and 10) is composed of a splatter filter and 4th amplifier (pins 7,
6, and 5) is composed of a splatter filter. The maximum frequency
deviation is determined to its optimal value by VR104 and input to the
cathode of the variable capacitance diode of the VCO, to change the
electric capacity in the oscillation circuit.

The transmitted signal is oscillated by the VCO, amplified by the pre
drive amplifier (Q104) and drive amplifier (Q103), and input to the

power amplifier (Q102). The signal is then amplified by the power

amplifier (Q102) and led to the antenna switch (D101 and D103) and

low-pass filter (L104, L103, L102, L101, C107, C108, C109, C110,

C111, C120, C121, C124, C125, C126, and C127 ), where unwanted

high harmonic signals are reduced as needed, and the resulting

signal is supplied to the antenna.

Part of the transmission power from the low-pass filter is detected by
D105, converted to DC, and then amplified by a differential amplifier
( Q111 ). The output voltage controls the bias voltage from the gate of

Q102 and Q103 to maintain the transmission power constant.

4

3) PLL Synthesizer Circuit

1.CPU control

2. Reference Frequency Circuit

3. Phase Comparator Circuit

4. PLL Loop Fitter Circuit

5. VCO Circuit

The dividing ratio is obtained by sending data from the CPU (IC109)
to pin 10, and sending clock pulses to pin 9 of the PLL IC (IC101).
The oscillated signal from the VCO is amplified by the buffer (Q118),
then input to pin 8 of IC101. Each programmable divider in IC101
divides the frequency of the input signal by N-value according to the
frequency data, to generate a comparison frequency of 5 or 6.25

kHz.

The reference frequency appropriate for the channel steps is
obtained by dividing the 12.8MHz reference oscillation (X102) by
2048 or 2560, according to the data from the CPU (IC109). When the

resulting frequency is 5 kHz, channel steps of 5, 10, 15, 20, and 30
kHz are used. When it is 6.25 kHz, steps of 12.5, 25, and 50 kHz are
used.

The PLL (IC101) uses the reference frequency, 5 or 6.25 kHz. The

phase comparator in the IC101 compares the phase of the frequency

from the VCO with that of the comparison frequency, 5 or 6.25 kHz,
which is obtained by the internal divider in IC101.

If a phase difference is found in the phase comparison between the

reference frequency and VCO output frequency, the charge pump
output (pin 5) of IC101 generates a pulse signal, which is converted
to DC voltage by the PLL loop filter and input to the variable
capacitance diode of the VCO unit for oscillation frequency control.

A Colpitts oscillation circuit driven by Q108 directly oscillates the
desired frequency. The frequency control voltage determined in the
CPU (IC109) and PLL circuit is input to the variable capacitance
diodes (D109 and D110). This changes the oscillation frequency,
which is amplified by the VCO buffer (Q110) and output from the VCO

unit.

4) CPU and Peripheral Circuits

1. LCD Display Circuit

The CPU turns ON the LCD via segment and common terminals with

1/3 the duty and 1/3 the bias, at the frame frequency of 112.5Hz.

2. Display Lamp Circuit

When the LAMP key is pressed, "L" is output from pin 42 of CPU

(IC109) to the bases of Q152 then turns to ON and "H" is output from
emitter of Q152 to the bases of Q146 to light LEDs (D131, D132).

5

3. Reset and Backup Circuits

4. S(Signal)Meter Circuit

5. Tone Encoder

6. CTCSS Decoder

7.Clock Shift

When the Output Voltage from pin 3 of IC110 drops to 4.5 V or below,
the output signal from the reset IC (IC104), which has been input to

pin 33 of the CPU (IC109), changes from "H" to "LM level. The CPU
will then be in the backup state.

The DC potential of pin 12 of IC103 is input to pin 1 of the CPU

(IC109), converted from an analog to a digital signal, and displayed
as the S-meter signal on the LCD.

The CPU (IC109) is equipped with an internal tone encoder. The tone
signal (67.0 to 250.3Hz) is output from pin 9 of the CPU to the
variable capacitance diode of the VCO and 21.25MHz reference
oscillation (X101) of the PLL IC (IC101) for modulation.

The AF signal from the pin 9 of IC103 is filtered by an active filter

(IC108) to eliminate the voice range of the signal then amplified and

input to the pin 4 of the CPU (IC109). The signal is compared in the
CPU with the pre-selected CTCSS values and the squelch opens in
case the value matches.

In case the selected frequency is disturbed by a CPU clock-noise, it

may be eliminated by changing the CPU clock frequency. When the
clock-shift is set, the pin 31 of the CPU (IC109) becomes Low turning
ON the Q124. When Q124 becomes ON, X104’s oscillation frequency
shifts approximately by 200ppm.

a o

LU L U

K> M

> 18

t- 1-t-t-CNCNCNCNCNCNCNC'I W o Z O CyJsSNSSNN

CLCLCLCLCLCLCLCLCLCLCLCL>X>?XXla:CLCLCLCLCLCLCL

************ HtJW******

N r O CI I C Ne i O »B (V r O[ l l l . i l ) n NrO n N Nr r

ÆÆÆ 0 000 000 0 00.0

W WW iu iui uiu iui uiu iu iuiu >5 iO OO O

% % % tO co to CO to to to to to to < U u a a

c
o

o

CD

c
c
o

O

LU

10

>

c

CL

3

O

CL

5) M38268MCA-077GP ( XA1169 )

O

► ¿Zd

►

► - ilN I/i ^ d

► *1NI/*W

► inoi/^/Cfrd

► CFH/n-d

► axj/std
► L>nos/9td

► MOUg/Zftj

► 5WM3/°Sd

► iWMd/iSd
► odia/zsd

► - idiy /e s d

► °HiNOA9d
► iMINO/sSd

► iva/ssd
► zva/iav/¿sd

► 0NV/ZNis/09d

► iNV/^mos/igd
► ZNV/^T3S/29d
► ENV/zz>nos/E9d

► >NV/>9d

► SNV/S9d

► 9NV/99d

► ¿NV/¿9d

No. Terminal Signal I/O

Description

1 P67/AN7 SMT I S-meter input

2

P66/AN6
3 P65/AN5
4 P64/AN4 TIN I
5 P63/SCLK22/AN3

P62/SCLK21/AN2 BP2 I Band plan 2

6
7 P61/SOUT2/AN1
8 P60/SIN2/AN0

P57/ADT/DA2 CTOUT

9

10

P56/DA1 DTOUT

11 P55/CNTR1 SCL
12
13
14

P54/CNTR0

P53/RTP1 BP4 I Band plan 4
P52/RTP0

15 P51/PWM3

SQL I

Noise level input for squelch

BAT I Low battery detection input

CTCSS tone input

BP1 I Band plan 1

- -

FKEY I Function / Monitor Key input

O CTCSS tone output
0 ATT output

Serial clock for EEPROM

0

TBST

MUTE
CLK

I/O Tone burst output

I/O Microphone mute

0 Serial clock output for PLL

Serial data output for PLL, CTCSS / PLL unlock signal input /

16 P50/PWM0
17 P47/SROY1

DATA

I/O

EVR control output

- -

18 P46/SCLK1 STBP 0 Strobe for PLL IC

19 P45/TXD UTX 0 UART data transmission output
20 P44/RXD URX I UART data reception input
21 P43/$TOUT BEEP I/O Beep tone/Band plan 3 ( when the unit is turned on)
22 P42/INT2 RE2 I
23 P41/INT1 RE1 I

Rotary encoder input

24 P40 CLO 0 CLONE ON/OFF output
25 P77 PTTK I PTT input
26 P76 CHG I Battery charge ON/OFF output
27 P75 P5C 0 PLL power ON/OFF output
28 P74 T5C 0 TX power ON/OFF output
29 P73 R5C 0 RX power ON/OFF output
30 P72 AFP 0 AF AMP power ON/OFF output
31 P71 CLSFT 0 CLOCK frequency shift
32 P70/INTO BU I Backup siqnal detection input
33 RESET RESET I Reset input
34 Xcin
35 Xcout
36 Xin XIN
37 Xout XOUT
38 Vss GND

- -

- -

-

Main clock input

-

Main clock output

-

CPU GND
39 P27 PSW I Power switch input
40 P26 SDA 0 Serial data for EEPROM
41 P25 C5C 0 C5V power ON/OFF output
42 P24 LAMP 0 Lamp ON/OFF
43 P23 KI0 I
44 P22 KI1 I
45 P21 KI2 I

Key matrix input
46 P20 KI3 I

47 P17 K03 0
48 P16 K02 0
49 P15/SEG39 KOI 0

Key matrix output
50 P14/SEG38 KOO 0

51 P13/SEG37 DA3 0 DA converter for Tx output power
52 P12/SEG36 DA2 0 DA converter for Tx output power
53 P11/SEG35 DA1 0 DA converter for Tx output power
54 P10/SEG34 AFC/DA0 0 DA converter for Tx output power

Voice Scrambler Board detection
55 P07/SEG33 EXP I/O

(when the unit is turned on )
56 P06/SEG32 SD/PO 0 Siqnal detection output

8

No. Terminal Signal I/O

57

P05/SEG31 SEG31 0

Description

58 P04/SEG30 SEG30 0
59 P03/SEG29 SEG29 0
60 P02/SEG28 SEG28 0
61
62

P01/SEG27 SEG27
P00/SEG26 SEG26 0

0

63 P37/SEG25 SEG25 0
64 P36/SEG24 SEG24

0
65 P35/SEG23 SEG23 0
66
67 P33/SEG21 SEG21

P34/SEG22 SEG22

0

0
68 P32/SEG20 SEG20 0
69 P31/SEG19 SEG19 0
70 P30/SEG18 SEG18 0
71 SEG17 SEG17
72

SEG16 SEG16 0
73 SEG15 SEG15 0
74 SEG14 SEG14

0

LCD segment signal

0
75 SEG13 SEG13 0
76
77

SEG12 SEG12
SEG11 SEG11 0

0

78 SEG10 SEG10 0
79 SEG9 SEG9 0
80 SEG8 SEG8 0
81
82

SEG7 SEG7
SEG6 SEG6 0

0

83 SEG5 SEG5 0
84 SEG4 SEG4

0
85 SEG3 SEG3 0
86
87

SEG2 SEG2
SEG1 SEG1 0

0

88 SEGO SEGO 0
89 Vcc

VDD
90 Vref Vref
91 Avss Avss
92
93

COM3 COM3 0 LCD COM3 output
COM2 COM2

94 COM1 COM1

-

CPU power terminal

-

AD converter power supply

-

AD converter GND

LCD COM2 output

0

LCD COM1 output

0
95 COMO COMO 0 LCD COMO output
96 VL3 VL3
97 VL2 VL2
98

C2 C2

99 C1 C1

-

LCD power supply

-

- -

- -

100 VL1 VL1 I LCD power supply

9

SEMICONDUCTOR DATA

1) NMJ2070MT1 ( XA0210 )

Low V olta ge Po we r Amplifier
Equivalent Circuit

Parameter Condition Symbol Min. Typ.

Supply voltage
Idle current RL=
Output voltage Vo
Input bias current IB

Output power

Distortion
Voltage gain
Input Impedance

Equivalent Input noise
voltage

Power supply voltage
rejection ratio

Power gain band width
(—3dB)

THD=10%, f=1kHz

THD=10%, f=1kHz

Po=0.4W, RL=4 , f=1kHz
f=1kHz
f=1kHz

Rs=10k

f= 100Hz, Cx=100/<F SVR 24 30

RL=8 , Po=250mW P.B

V+=6V, RL=4
V+=4.5V, RL=4
V+=3V, RL=4
V+=2V, RL=4
V+=6V, RL=4
V+=4.5V, RL=4

A curve

B=22Hz to 22kHz Vn2

V+

IQ

Po

THD -

Av

ZlN

Vn1

1.8

-

2.7

-

200

-

0.5 0.6

0.32

-

120

-

-
500

-
250

-

0.25

41 44

100

-

2.5

-

200

-

30

Max.

-

4

-

3

15

7

-

-

-

-

-

-

-

-

- %

47

-

-

-

-

-

Unit

V

mA

V

nA

W

W
mW
mW
mW
mW

dB

k

M V

M V

dB

kHz

2) S24CS64A01-J8T1G ( XA1117 )

16 K bits CM OS Serial E E P R O M

Pin

Number

Remark S ee Dimensions for details of the package drawings.

10

AO Œ
A1 Œ
A2 Œ

GND Œ

1o

2 7
3 6

4 5

8

ZD V CC
ZD WP

=□ SCL
ZD SDA

Pin

Name

1
2 A1
3 A2 Slave address input
4 GN D Groudd
5
6 SCL Serial clock input

7 WP

8

A0 Slave address input

Slave address input

SDA Serial data input / output

Write protection input

Connected to Vcc: Protection valid
Connected to GND: Protection invalid

VCC

Power supply

Function

3) M62429FP/CF0J ( XA1118 )

Electronic Vo lu m e

Vin1

[T

3

I T] Vin2

0>

ro

VoutI

G N D [3

D AT A [4

[2

-Et

IV

(0

3

T1
"Ö

7 ]V out2

l]V cc 1

5] CL O CK

Vin2 Voltt2 Vcc

4) LM2902PWR ( XA1106 )

Qu ad Operational Amplifiers

C LO C K

—® ------

LO G IC

C O NT R OL

D AT A

14 13 12 11 10 9 8

L2902

* **

* * **

o

1 2 3 4 5 6 7

1. Output A

2. Inverting Input A

3. Non-inverting Input A

4. Vcc

5. Non-inverting Input B

5. Inverting Input B

7. Output B

8. Output C

9. Inverting Input C

10. Non-inverting Input C

11.GND

12. Non-inverting Input D

13. Inverting Input D

14. Output D