Akira LCT-32V82ST Schematic

INDEX:

LH

32SXXW SERVICE MANUAL

PART 1：

PART 2:

PART 3

PART 4:

PART 5: Components list

Brief Introduction Of The LH32SXXW

◆

Schematic Diagram Block

◆

Printed Circuit

Exploded view

：

IC Introduction

Detailed Circuit

PART 6: Debug Instruction

Part1:

Schematic Diagram Block

Printed circuit

TV Main Board

Highly Integrated Advanced 3D Comb Video Decoder + HDTV Total Solution

Part3:

TM

LVDS Panel HDTV-Ready Signal Processor

OVERVIEW

The SVPTMAX-32/68 video processor is a highly integrated system­on-a-chip device, designed for the advanced HDTV-ready LVDS
panel TV applications. SVP
advanced multi-standard audio decoders, advanced audio
processors, embedded MPU and HDMI, triple 10-bit high-precision
and high-speed video ADCs, the 7th generation high-performance
multi-format 3D digital comb video decoder that supports NTSC,
PAL and SECAM*, a HDTV sync separator, motion and edge
adaptive de-interlacing engine, and the video format conversion
engine, supporting many output modes.
Trident's DCRE
integrated inside the SVP
cinema-realistic images. The DCRE
advanced 3D-comb video decoding, advanced motion adaptive de­interlacing, object-based digital noise reduction, advanced 7th
generation scaling engine, film mode support, average picture level
(APL), edge smoothing and dynamic sharpness enhancement.
Trident's patented Unified Memory Architecture (UMA) allows
frame rate conversion, 3D comb video decoding, and video
enhancement processing to share the same frame buffer memory.
All these advanced digital processing techniques are combined
with a true 10-bit video data processing for the most optimal video
fidelity to provide the most natural and cinema-quality video
images.
Designed for maximum system design flexibility, SVP
integrates all video interfaces to support converging digital video,
analog video, and PC data applications. The users of Trident's
single chip SVP
many features while maintaining a price competitive advantage
over the existing solution(s).

* In SECAM, SVP™AX-32/68 video decoding mode is only 2D

TM

TM

P

TM

AX-32/68 contains embedded

engine--Digital Cinema Reality Engine, is

TM

AX-32/68 to provide the most natural

TM

technology integrates

TM

AX-32/68

AX-32/68 video processor(s) will benefit from

1 x CVBS, C

4 x Component
2 x FB for SCART

2 x FS for SCART
16-bit CCIR601
8/10-bit CCIR656
4 stereo Line In, 1 SIF

1 shared I2S/SPDIF

INPUTS/OUTPUTS

Analog Video
Inputs

Digital Video
Inputs

Analog
Outputs

Analog Audio
Inputs
Analog Audio
Outputs

Digital Audio
Inputs

Digital Audio
Outputs

1 x CVBS
1 X C
4 x Component
2 x FB (for SCART)
2 x FS (for SCART)

16-bit CCIR601
8/10 bit CCIR656

2 x CVBS outputs
Single 8/10/12/14 bit or Dual 8-bit LVDS

1 SIF

4 Stereo Line In
1 stereo speaker out
1 stereo audio out or SCART1 out
1 headphone out or SCART2 out (shared with
2nd audio out)

1 shared I2S/SPDIF

1 shared I2S/SPDIF

DESCRIPTIONS

Embedded 8051 MPU (up to 100 MHz SPI interface) with external
serial flash inteface
Embedded Advanced Multi-Standard Audio Decoder
Embedded Advanced Audio Processor with lip sync
Embedded HDMI 1.2a
Support for 1440 x 900 and 1080P panels (SVP
Advanced Color Management Engine
Integrated 7th Generation Motion and Edge Adaptive De-interlacing

7th generation adaptive edge smoothing algorithm for
enhancing image clarity and sharpness
Pixel-based motion and edge adaptive de-interlacing

Frame Buffer

TM

SVP

AX

Flash Memory

TM

AX-68)

SVP

AX-32/68

Integrated Triple ADC Port

High-precision 10-bit ADC mode up to 108 MHz for SD/HD
analog video input modes
Direct support of CVBS/S-video/Component and
HD-D1/D2/D3/D4 modes

Auto clock phase adjustment for PC & HD component inputs

Auto position for PC RGB inputs

Advanced 7th Generation Scaling Engine

Horizontal Mirror Image Inversion

DNR-Digital Temporal and Spatial Noise Reduction Filter

Advanced Chroma Processing

Green Color Stretch, blue color stretch, and skin color enhancement

Integrated 7th Generation Motion Adaptive 3D Digital Comb Video
Decoder with Programmable Filter

Supports NTSC, PAL, and SECAM formats

Smooth 3D/2D image transition with Trident's proprietary object
and motion adaptive detection
Programmable comb filter adapts to all possible
environments, and 2D Y/C separation
Color edge enhancement circuit improves the chroma transient
so that the chroma edge looks sharper than the original signal
High precision 10-bit ADC analog front-end

Enhanced NTSC/PAL/SECAM auto detection
Enhanced false color reduction circuitry

Inverse Color Space Conversion

PDP TV

DIGITAL TV

LCD TV

Preliminary Product Brief. December 2006

True 10-Bit Video Processing Path

Preliminary Product Brief. December 2006

LVDS Panel HDTV-Ready Signal Processor

Frame Rate Conversion

Supports frame rate conversion for PC and video mode
Both free-running and line-lock modes are supported

14D: Dynamic Picture Enhancements

Advanced Film Mode Recovery-3:2/2:2 pull down

PWM

One high-precision PWM
Two GPIO shared PWM
18-bit PWM output for VS tuner

Memory Interface

Supports 16 bits DDR memory interface
Memory clock support up to 250 MHz

Trident's

SVP™AX

Solution

(PC Sync)
AIN_H/AIN_V
1xCVBS

1xC

4xComponents

(PC)

FB1/FB2

Audio

from

FS1/FS2

Tuner

SIFP/SIFN

ADCs

Analog

Mux

DCReTM Advanced Image Processing

Advanced LUMA processing for image enhancement
White peak limitation
Black and White extension
Horizontal and vertical sharpness control
User-friendly white balance adjustment
Advanced linear and non-linear panorama scaling algorithms
Integrated sync separator with line-locking PLL
Programmable zoom viewer allows partial still pictures and
live broadcast to be viewed in greater detail.
Gamma correction with 10-bit per color look-up table
Picture controls such as hue, saturation, brightness, and
contrast can be automatically adjusted to their optimal balance
sRGB support

ASS/DSS

LLPLL

3D Video

Decoder

VBI Slicer

(CC/Teletext)

ICSC

MP

Motion & Edge

Adaptive

Deinterlacer

PIP (OSD2)

before

framebuffer

scaling down

DDR upto 250 MHz

1Mx16, 2Mx16, 8Mx16

UMAC Memory Control

MP

th

7

generation

Noise

Reduction

scalar

MP

Chroma Processing

Color Management

adjustment

16-bit DDR interface

MP

Advanced Luma/

H/V Sharpness
Luma Dynamic

Contrast

CSC

PIP
Basic Brightness/
contrast/ hue/Sat.

DLP TV

OSD and VBI/Closed Caption

Advanced OSD Engine

1/4/8/16/32-bit color OSD display
Hardware scrolling for CC display
One OSD Plane

Horizontal Mirror

Packaging

256-Pin PQFP





Link1

Panel upto

Link2

1920 x 1080P

2 x CVBS Out

MP, PIP

OSD

blending

GAMMA

LUT

1024x10x3

LVDS TX

CVBS_OUT

SVPTMAX

(AL/AR) x 4

SPDIF / I2S

PWR5V

HDMi/DVI in (±)

(DDC) DSCL/DSDA

Audio Matrix

4 X Analog Audio Line

Input;

SPDIF or I2S input

supported (shared ports)

HDMi /HDCP

Rx 1.2

Digital Input

Port (165

MHz)

USA Taiwan

Trident Microsystems, Inc. (Headquarters)
3408 Garrett Drive
Santa Clara, CA 95054-2804, USA
Phone: [phone]
Fax: [phone]
Web site: http://www.tridentmicro.com

Audio Demodulation

(Worldwide format, NICAM

included)

Audio Processing

Audio LipSync

XRAM

16K + 8 K

Embedded 8051 CPU

powerful 2 cycle

SPI upto 100MHz

Cache

HongKong

Trident Microelectronics Ltd.
4F. No. 323, Yangguang St.,
Neihu,Taipei, Taiwan ROC
Phone: [phone]
Fax: [phone]
Web site: http://www.trident.com.tw

Audio Out

(DAC & SPDIF

encoder

PWM
I2C (slave &
Master)
UART x 2
JTAG
GPIO

Trident Microsystems (Far East), LTD.
No. 2, 3, & 5, 5/F., Futura Plaza,
111-113 How Ming Street, Kwun Tong,
Kowloon, Hong Kong
Phone: [phone]
Fax: [phone]

©2006. All rights reserved. Trident and its logo are registered trademarks of Trident Microsystems, Inc. All other trademarks and registered trademarks are acknowledged and are properties of their respective owners.

The information in this document is subject to change, as the Company may make changes to the product in order to improve reliability, design, or function, without prior written notice.

SPKOL/SPKOR

AOL1/AOR1

HPHO L/HPHOR(AO L1/

AOR2)

I2S or SPDIF

)

Mute

5

Part4:

Y1_IN
PB1_IN
PR1_IN

SC1_G

D D

C C

B B

SC1_B
SC1_R

SV_Y_MP
SC1_CVBS

SC2_Y_CVBS

SV_C_MP

PC_GIN
PC_BIN
PC_RIN

R10

R10
75R

75R

R17

R17
75R

75R

R22

R22
75R

75R

Pin Name
CVBS1
Y_G3
PB_B3
PR_R3

A A

FB1

FS1
FS2

R1
75RR175R

R7 75RR7 75R

R11

R11

R12

R12

75R

75R

75R

75R

R23

R23

R24

R24

75R

75R

75R

75R

Pin No.

52
42
43
44
57
56FB2
55
54

R3

R2

75RR375R

75RR275R

R9 75RR9 75R

R8 75RR8 75R

PC_HSIN
PC_VSIN

TV_CVBS1

AX_CVBS_OUT1
AX_CVBS_OUT2

AX_VCC33

SC2_C/R

VIDEO_2

DEFINITION IN LCD301
MAIN TUNER INPUT
SVIDEO Y INPUT
SCART1 CVBS INPUT
SCART2 CVBS INPUT
SCART1 FB INPUT
SCART2 or 3 Chroma INPUT
SCART1 FS INPUT
SCART2 FS INPUT

5

R4 10RR4 10R
R5 10RR5 10R
R6 10RR6 10R

R13 10RR13 10R

R14 10RR14 10R
R15 10RR15 10R
R16 10RR16 10R

R18 10RR18 10R

R21 0RR21 0R

C15

C15

10uF/16V

10uF/16V

R25 10RR25 10R

R26

R26

75R

75R

C2 0.1uFC2 0.1uF

C5 0.1uFC5 0.1uF

C8 0.1uFC8 0.1uF

C11 0.1uFC11 0.1uF

C13 0.1uFC13 0.1uF

R19 75RR19 75R
R20 75RR20 75R

C16

C16

0.1uF

0.1uF

TOUCH_IN

R28 10RR28 10R

R27

R27
75R

75R

C1 0.1uFC1 0.1uF
C3 0.1uFC3 0.1uF
C4 0.1uFC4 0.1uF
C6 0.1uFC6 0.1uF
C7 0.1uFC7 0.1uF
C9 0.1uFC9 0.1uF
C10 0.1uFC10 0.1uF
C12 0.1uFC12 0.1uF

C14 0.1uFC14 0.1uF

AX_VREFP_1

AX_VREFN_1

SC1_FB
SC2_FS

4

RX3V1_DDC_SCL

HDMI_RX1-

HDMI_RX2-

HDMI_RX2+

17

Y_G1
PB_B1
PR_R1

Y_G2
PB_B2
PR_R2

Y_G3
PB_B3
PR_R3

PC_G
PC_B
PC_R
AIN_HS
AIN_VS

CVBS
C
CVBS_OUT1

CVBS_OUT2

VREFP
VREFN

C18 0.1uFC18 0.1uF

4

16

RX2-

RX2+

SVP-AX

SVP-AX

56

U1A SVP-AX_256

U1A SVP-AX_256

33
34
35

36
37
38

42
43
44

29
28
30
26
27

52
45
61

60

71
69

C17 0.1uFC17 0.1uF

R29 100R_DNSR29 100R_DNS
R146 100RR146 100R

HDMI_RX0-

HDMI_RX1+

HDMI_RX0+

9

13

8

12

RX0-

RX1-

RX0+

RX1+

PQFP_256

PQFP_256

(1/4)

(1/4)

HDMI

HDMI
AUDIO IN

AUDIO IN
PLL

PLL

FS155FS254FB157FB2

XTALI

194

XI

Y1

24MHzY124MHz
R31 1MR31 1M

C19

C19

18pF

18pF

RX3V1_DDC_SDA

HDMI_RXC-

HDMI_RXC+

19

4

20

5

RXC-

DSCL

RXC+

DSDA

AUD_MCLK

XTALO

MLF1

PLF2

195

197

200

XO

R30

R30
33R

33R

LAYOUT: Place xtal
circuit as compact
and close to chip
as possible

C20

C20

18pF

18pF

AGND

PWR5V

21

PWR5V

HPHOL

HPHOR

SPKOL
SPKOR

AUD_SD

AUD_WS

SIFP
SIFN

AOL1

AOR1

VCM

AL1

AR1

AL2

AR2

AL3

AR3

AL4

AR4

AX_PLF2
AX_MLF1

R38

R38

4.7K_DNS

4.7K_DNS

50
51
63
64
81
82
66
67

70
73
74
75
76
77
78
79
80

85
86
87

AUD_MCLK
AUD_SD
AUD_WS

R684.7K R684.7K

3

AX_VCC33

C24

C24

0.1uF

0.1uF

R39

R39

4.7K_DNS

4.7K_DNS

C23

C23

AGND

0.1uF

0.1uF

A1_LIN

A1_RIN

A2_LIN
A2_RIN

A3_LIN

A3_RIN

A4_LIN
A4_RIN

R37 33R_DNSR37 33R_DNS
R36 33R_DNSR36 33R_DNS
R35 33R_DNSR35 33R_DNS

R34 33R_DNSR34 33R_DNS
R33 33R_DNSR33 33R_DNS
R32 33R_DNSR32 33R_DNS

R65 1KR65 1K
R66 1KR66 1K
R67 1KR67 1K

R694.7K R694.7K

R704.7K R704.7K

3.3V_SB

A_MCLK_IN

A_SD_IN

GPIO00

A_WS_IN

3

AGND

AGND

C21

C21

0.1uF

0.1uF

AGND

CON1

CON1

5x2.0MM_DNS

5x2.0MM_DNS

R40

R40
0R_DNS

0R_DNS

C22

C22

10uF/16V

10uF/16V

A_MCK_OUT
A_SD_OUT
A_WS_OUT

A_MCLK_IN
A_SD_IN
A_WS_IN
AUD_SD

L/R_SW1
L/R_SW2
LED_R

1
2
3
4
5

2

HDMI1_5VIN

PWR5V

R41 10KR41 10K

SIF

R45 220RR45 220R

R46 220RR46 220R

C31

C31

C30

C30

1000pF

1000pF

1000pF

1000pF

AGND

R58 220RR58 220R

R59 220RR59 220R

C36

C36
1000pF

1000pF

C37

C37
1000pF

1000pF

AGND AGND

2

0.01uF

0.01uF

C26 1uFC26 1uF

C27 1uFC27 1uF

C25

C25

R42

R42
10K

10K

C28

C28

R49

R49
100K

100K

470pF

470pF

AGND

C40 1uFC40 1uF

C41 1uFC41 1uF

Schematict Name Rev

Schematict Name Rev

Schematict Name Rev

Size

Size

Size

C38

C38
470pF

470pF

C29

C29
470pF

470pF

B

B

B

Q1

R62

R62
100K

100K

2

3

R50

R50
100K

100K

Q1
2N7002

2N7002

sot_23

sot_23

Audio_out_R

Sheet

Sheet

Sheet

R43

R43
10K

10K

1

R44

R44
10K

10K

3.3V_SB

R47220R R47220R

R48220R R48220R

Audio_out_L

R60 220RR60 220R

R61 220RR61 220R

R63

R63

C39

C39

100K

100K

470pF

470pF

Title

Title

Title

ANALOG CHANNEL

ANALOG CHANNEL

ANALOG CHANNEL

of

of

of

117

117

117

1

SC2_LOUT

SC2_ROUT

SC1_LOUT

SC1_ROUT

AX68 Solution Design

AX68 Solution Design

AX68 Solution Design

Date:

Date:

Date:

Friday, April 20, 2012

Friday, April 20, 2012

Friday, April 20, 2012

1

2.0.3

2.0.3

2.0.3

5

D D

U1B SVP-AX_256

U1B SVP-AX_256

DPA_0

254
253
252
251
250
249
248
247
241
240
239
238
237
236
235
234

242
255
256

DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
DP8
DP9
DP10
DP11
DP12
DP13
DP14
DP15

DP_CLK
DP_HS
DP_VS

SVP-AX

SVP-AX

PQFP_256

PQFP_256

LVDS OUT

LVDS OUT
Digital IN

Digital IN

TA2M

TA2P

TB2M

TB2P

213

212

211

210

AX_TA2-

AX_TA2+

AX_TB2+

AX_TB2-

(2/4)

(2/4)

TC2M

TC2P

209

208

AX_TC2+

AX_TC2-

207

AX_TCLK2-

TCLK2M

206

AX_TCLK2+

TCLK2P

DPA_1
DPA_2
DPA_3

C C

3.3V_SB

R71

R71

4.7K

4.7K

R72

R72

4.7K

4.7K

B B

DPA_4
DPA_5
DPA_6
DPA_7
DPA_8
DPA_9
DPA_10
DPA_11
DPA_12
DPA_13
DPA_14
DPA_15

DPA_CLK
DPA_HS
DPA_VS

4

LCD_TA1+
LCD_TB1+
LCD_TC1+

LCD_TCLK1+

LCD_TA2+
LCD_TB2+
LCD_TC2+

LCD_TCLK2+

LCD_TD2+

3V_SDA_MSTL

C50

C50

27pF_DNS

TA1M

TA1P

TB1M

TB1P

TC1M

TC1P

TCLK1M
TCLK1P

TD1M

TD1P

TD2M

TD2P

205

204

AX_TD2-

AX_TD2+

226
225

224
223

222

221
220

219
218

AX_TA1+
AX_TB1-

AX_TB1+
AX_TC1-

AX_TC1+

AX_TCLK1­AX_TCLK1+

AX_TD1­AX_TD1+

AX_TA1-

227

27pF_DNS

LINE1
LINE2
LINE3
LINE4

3

PVDD

CON2

CON2

BM40B-SRDS-G-TF

BM40B-SRDS-G-TF

12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940

LVDS connector

3.3V_SB

R79

R75

R75

R73

R73

4.7K_DNS

4.7K_DNS

4.7K_DNS

4.7K_DNS

R76

R76

R74

R74

4.7K_DNS

4.7K_DNS

4.7K_DNS

4.7K_DNS

R79

R77

R77

4.7K_DNS

4.7K_DNS

4.7K_DNS

4.7K_DNS

R78

R78

R80

R80

4.7K_DNS

4.7K_DNS

4.7K_DNS

4.7K_DNS

LINE1
LINE2

LINE3
LINE4

LCD_TA1­LCD_TB1­LCD_TC1­LCD_TCLK1­LCD_TD1-LCD_TD1+

LCD_TA2­LCD_TB2­LCD_TC2­LCD_TCLK2­LCD_TD2-

3V_SCL_MSTL

C51

C51

27pF_DNS

27pF_DNS

2

RN1

RN1

0Rx4

0Rx4

1

8

2

7

LCD_TA1+ AX_TA1+

LCD_TB1­LCD_TC1- AX_TC1-

LCD_TC1+

LCD_TCLK1-

LCD_TCLK1+ AX_TCLK1+

LCD_TD1­LCD_TD1+

LCD_TA2­LCD_TA2+
LCD_TB2­LCD_TB2+

LCD_TC2­LCD_TC2+
LCD_TCLK2­LCD_TCLK2+

LCD_TD2­LCD_TD2+ AX_TD2+

6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

RN2

RN2

0Rx4

0Rx4

RN3

RN3

0Rx4

0Rx4

RN4

RN4

0Rx4

0Rx4

RN5

RN5

0Rx4

0Rx4

RN6

RN6

0Rx4

0Rx4

3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

AX_TA1-LCD_TA1-

AX_TB1­AX_TB1+LCD_TB1+

AX_TC1+

AX_TCLK1­AX_TD1-

AX_TD1+

AX_TA2­AX_TA2+
AX_TB2­AX_TB2+

AX_TC2­AX_TC2+
AX_TCLK2­AX_TCLK2+

AX_TD2-

1

LINE3

R81 100R_DNSR81 100R_DNS
R82 100R_DNSR82 100R_DNS

LINE4

A A

5

4

3

BRT_CNTL
VBR_OUT

Title

Title

Title

AX68 Solution Design

AX68 Solution Design

AX68 Solution Design

Schematict Name Rev

Schematict Name Rev

Schematict Name Rev

Size

Size

Size

2

LVDS INTERFACE

LVDS INTERFACE

LVDS INTERFACE

Sheet

Sheet

Sheet

B

B

B

217

217

217

2.0.3

2.0.3

2.0.3

Date:

Date:

Date:

Friday, April 20, 2012

Friday, April 20, 2012

of

of

of

Friday, April 20, 2012

1