ZILOG Z86E0208PECSL1925, Z86E0208PSCSL1925, Z86E0208SECSL1925, Z86E0208SSCSL1925 Datasheet

CP97DZ83501

P R E L I M I N A R Y

1

1

P

RELIMINARY

C

USTOMER

P

ROCUREMENT

S

PECIFICATION

Z86E02 SL1925

1

CMOS Z8

®

OTP M

ICROCONTROLLER

FEATURES

■

18-Pin DIP and SOIC Packages

■

3.5V to 5.5V Operating Range @ 0 ° C to +70 ° C

4.5V to 5.5V Operating Range @ -40 ° C to +105 ° C

■

14 Input / Output Lines

■

Five Vectored, Prioritized Interrupts with Programmable
Polarity

■

Two Analog Comparators

■

WDT/Power-On Reset (POR)

■

Program Options:
– Low Noise
– ROM Protect
– Auto Latch
– Permanent Watch-Dog Timer (WDT)
– EPROM/TEST Mode Disable
– RC Oscillator

■

One Programmable 8-Bit Counter/Timer, with
6-Bit Programmable Prescaler

■

On-Chip Oscillator that Accepts RC, XTAL, Ceramic
Resonance, LC, or External Clock

■

Clock-Free WDT Reset

■

Low-Power Consumption (50 mw)

■

Fast Instruction Pointer (1.5 µ s @ 8 MHz)

GENERAL DESCRIPTION

Zilog's Z86E02 Microcontroller (MCU) is a One-Time Pro­grammable (OTP) member of the Z8

single-chip microcon­troller family which allow easy software development, de­bug, prototyping, and small production runs not
economically desirable with masked ROM versions.

For applications demanding powerful I/O capabilities, the
Z86E02's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.

An on-chip counter/timer, with a large number of user se­lectable modes, offload the system of administering real­time tasks such as counting/timing and I/O data communi­cations.

Note: All Signals with a preceding front slash, “/”, are

active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE
is active Low, only).

Power connections follow conventional descriptions be­low:

Part ROM RAM* Speed
Number (Kilobytes) (Bytes) (MHz)

Z86E02 0.5 61 8

* General-Purpose

Connection Circuit Device

Power

V

CC

V

DD

Ground GND

V

SS

Z86E02 SL1925
CMOS Z8® OTP Microcontroller Zilog

2

P R E L I M I N A R Y

CP97DZ83501

GENERAL DESCRIPTION (Continued)

Figure 1. Functional Block Diagram

Port 3

Counter/

Timer

Interrupt

Control

T wo Analog

Comparators

Port 2

I/O

(Bit Programmable)

FLAG

Register

Pointer

General-Purpose

Register File

Machine

Timing & Inst.

Control

OTP

Program

Counter

Vcc GND

XTAL

Port 0

I/O

Input

ALU

Z86E02 SL1925

Zilog CMOS Z8® OTP Microcontroller

CP97DZ83501

P R E L I M I N A R Y

3

1

Figure 2. EPROM Programming Mode Block Diagram

Z8 MCU

Address

Counter

Address MUX

Data MUX

Z8 PORT2

ROM PROT

Low Noise

0.5K

EPROM

PGM

Mode Logic

D7-D0

D7-D0

D7-D0

A10-A0

A10-A0

A10-A0

3 Bits

Clear

P00

Clock

P01

EPM

P32

/CE

XT1

/PGM

P02

VPP

P33

/OE
P31

Z86E02 SL1925
CMOS Z8® OTP Microcontroller Zilog

4

P R E L I M I N A R Y

CP97DZ83501

PIN DESCRIPTION

Figure 3. 18-Pin EPROM Mode Configuration

Table 1. 18-Pin DIP Pin Identification

EPROM Programming Mode
Pin # Symbol Function Direction

1–4 D4–D7 Data 4, 5, 6, 7 In/Output

5V

CC

Power Supply

6 N/C No Connection
7 /CE Chip Enable Input
8 /OE Output Enable Input
9 EPM EPROM Prog Mode Input

10 V

PP

Prog V oltage Input

11 Clear Clear Clock Input
12 Clock Address Input
13 /PGM Prog Mode Input
14 GND Ground

15–18 D3–D0 Data 0,1, 2, 3 In/Output

D4
D5
D6
D7

VCC

N/C
/CE
/OE

EPM

D3
D2
D1
D0
GND
/PGM
CLOCK
CLEAR
VPP

18

DIP 18 - Pin

1

910

Figure 4. 18-Pin DIP/SOIC Standard Mode

Configuration

Table 2. 18-Pin DIP/SOIC Pin Identification

Standard Mode

Pin # Symbol Function Direction

1–4 P24–P27 Port 2, Pins 4,5,6,7 In/Output

5V

cc

Power Supply

6 XTAL2 Crystal Osc. Clock Output
7 XTAL1 Crystal Osc. Clock Input
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input

10 P33 Port 3, Pin 3, REF Input

11–13 P00–P02 Port 0, Pins 0,1,2 In/Output

14 GND Ground

15–18 P20–P23 Port 2, Pins 0,1,2,3 In/Output

P24
P25
P26
P27

VCC
XTAL2
XTAL1

P31
P32

P23
P22
P21
P20
GND
P02
P01
P00
P33

18

DIP 18 - Pin

1

910

Z86E02 SL1925

Zilog CMOS Z8® OTP Microcontroller

CP97DZ83501

P R E L I M I N A R Y

5

1

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper­ational sections of these specifications is not implied. Ex­posure to absolute maximum rating conditions for an ex­tended period may affect device reliability. Total power

dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig­ure 5).

Total Power Dissipation = V

DD

x [I

DD

- (sum of I

OH

)]

+ sum of [(V

DD

- V

OH

) x I

OH

]

+ sum of (V

0L

x I

0L

)

Parameter Min Max Units Note

Ambient Temperature under Bias –40 +105 C
Storage Temperature –65 +150 C
Voltage on any Pin with Respect to V

SS

–0.7 +12 V 1

Voltage on V

DD

Pin with Respect to V

SS

–0.3 +7 V

Voltage on Pins 7, 8, 9, 10 with Respect to V

SS

–0.6 V

DD

+1 V 2

Total Power Dissipation 462 mW
Maximum Allowable Current out of V

SS

240 mA

Maximum Allowable Current into V

DD

240 mA

Maximum Allowable Current into an Input Pin –600 +600

µ

A3

Maximum Allowable Current into an Open-Drain Pin –600 +600

µ

A4
Maximum Allowable Output Current Sinked by Any I/O Pin 20 mA
Maximum Allowable Output Current Sourced by Any I/O Pin 20 mA

Notes:

[1] This applies to all pins except where otherwise noted. Maximum current into pin must be ± 600 µ A.
[2] There is no input protection diode from pin to V

DD

(not applicable to EPROM Mode).

[3] This excludes Pin 6 and Pin 7.
[4] Device pin is not at an output Low state.

Figure 5. Test Load Diagram

From Output

Under Test

150 pF

Z86E02 SL1925
CMOS Z8® OTP Microcontroller Zilog

6

P R E L I M I N A R Y

CP97DZ83501

CAPACITANCE

T

A

= 25 ° C, V

CC

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

DC ELECTRICAL CHARACTERISTICS

Parameter Min Max

Input capacitance 0 10 pF
Output capacitance 0 20 pF
I/O capacitance 0 25 pF

T

A

= 0 ° C to +70 ° C

Typical

Note 4

Sym Parameter

V

CC

[4]

Min Max @ 25 ° C Units Conditions Notes

V

inmax

Max Input Voltage 3.5V 12 V I

In

<250 µ A 1

5.5V 12 V I

In

<250

µ

A 1

V

CH

Clock Input High
Voltage

3.5V 0.8 V

CCVCC

+0.3 1.7 V Driven by External

Clock Generator

5.5V 0.8 V

CCVCC

+0.3 2.8 V Driven by External

Clock Generator

V

CL

Clock Input Low
Voltage

3.5V VSS–0.3 0.2 V

CC

0.8 V Driven by External
Clock Generator

5.5V VSS–0.3 0.2 V

CC

1.7 V Driven by External
Clock Generator

V

IH

Input High Voltage 3.5V

5.5V

0.7 V

CC

0.7 V

CC

VCC+0.3
VCC+0.3

1.8

2.8

V
V

V

IL

Input Low Voltage 3.5V

5.5V

VSS–0.3
VSS–0.3

0.2 V

CC

0.2 V

CC

0.8

1.5

V
V

V

OH

Output High Voltage 3.5V VCC–0.4 3.0 V IOH = –2.0 mA 5

5.5V VCC–0.4 4.8 V IOH = –2.0 mA 5

3.5V VCC–0.4 3.0 V Low Noise @ IOH = –0.5 mA

5.5V VCC–0.4 4.8 V Low Noise @ IOH = –0.5 mA

V

OL1

Output Low Voltage 3.5V 0.8 0.2 V IOL = +4.0 mA 5

5.5V 0.4 0.1 V IOL = +4.0 mA 5

3.5V 0.4 0.2 V Low Noise @ IOL = 1.0 mA

5.5V 0.4 0.1 V Low Noise @ I

OL

= 1.0 mA

V

OL2

Output Low Voltage 3.5V 1.2 1.0 V IOL = +10 mA, 5

5.5V 1.2 0.8 V IOL = +10 mA, 5

V

OFFSET

Comparator Input
Offset V oltage

3.5V 25.0 10.0 mV

5.5V 25.0 10.0 mV

V

LV

VCC Low Voltage
Protection

2.6 3.2 2.9 V @ 4 MHz Max.
Int. CLK Freq.

I

IL

Input Leakage
(Input Bias
Current of
Comparator)

3.5V –1.0 1.0 µAVIN = 0V, V

CC

5.5V –1.0 1.0 µAVIN = 0V, V

CC