12
Z86C61/62/96
Z8® MICROCONTROLLER
PIN DESCRIPTION (Continued)
Table 6. Z86C96 68-Pin PLCC Pin Identification
Pin # Symbol Function Direction
1-2 P44-P43 Port 4, Pins 3,4 In/Output
3VCCPower Supply Input
4 P45 Port 4, Pin 5 In/Output
5 XTAL2 Crystal, Oscillator Clock Output
6 XTAL1 Crystal, Oscillator Clock Input
7 P37 Port 3, Pin 7 Output
8 P30 Port 3, Pin 0 Input
9 /RESET Reset Input
10 R//W Read/Write Output
11 /P0DS Port 0 Data Strobe Output
12 /DS Data Strobe Output
13-14 P47-P46 Port 4, Pins 6,7 In/Output
15 /P1DS Port 1 Data Strobe Output
16 /AS Address Strobe Output
17 /DTIMER Disable Timers Input
18 P35 Port 3, Pin 5 Output
19 N/C Not Connected Input
20 GND Ground Input
21 P32 Port 3, Pin 2 Input
22-23 P51-P50 Port 5, Pins 0,1 In/Output
PIN FUNCTIONS
XTAL1, XTAL2
Crystal 1, Crystal 2
(time-based input and
output, respectively). These pins connect a parallelresonant crystal, ceramic resonator, LC, or any external
single-phase clock to the on-chip oscillator and buffer.
R//W (output, write Low). The Read/Write signal is Low
when the MCU is writing to the external program or data
memory.
/RESET (input, active Low). To avoid asynchronous and
noisy reset problems, the Z86C61/62/96 is equipped with
a reset filter of four external clocks (4TpC). If the external
/RESET signal is less than 4TpC in duration, no reset
occurs.
On the fifth clock after the /RESET is detected, an internal
RST signal is latched and held for an internal register count
of 18 external clocks, or for the duration of the external
/RESET, whichever is longer. During the reset cycle, /DS is
held active Low while /AS cycles at a rate of TpC/2. When
/RESET is deactivated, program execution begins at location 000C (HEX). Reset time must be held Low for 50 ms,
or until VCC is stable, whichever is longer.
R//RL (input, active Low). This pin when connected to
GND disables the internal ROM and forces the device to
function as a Z86C96 ROMless Z8. (Note: When left
unconnected or pulled High to VCC the part functions as a
normal Z86C61/62 ROM version.) This pin is only available
on the 44-pin version of the Z86C61, and both versions of
the Z86C62.
/DS (output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
/AS (output, active Low). Address Strobe is pulsed once
at the beginning of each machine cycle. Address output is through Port 1 for all external programs. Memory
address transfers are valid at the trailing edge of /AS.
Under program control, /AS can be placed in the highimpedance state along with Ports 0 and 1, Data Strobe,
and Read/Write.
Pin # Symbol Function Direction
24-31 P07-P00 Port 0, Pins 0,1,2,3,4,5,6,7 In/Output
32 V
CC
Power Supply Input
33-36 P55-P52 Port 5, Pins 2,3,4,5 In/Output
37-38 P11-P10 Port 1, Pins 0,1 In/Output
39-40 P57-P56 Port 5, Pins 6,7 In/Output
41-46 P17-P12 Port 1, Pins 2,3,4,5,6,7 In/Output
47-48 P63-P62 Port 6, Pins 3,2 In/Output
49 P34 Port 3, Pin 4 Output
50 P33 Port 3, Pin 3 Input
51 GND Ground Input
52 /SYNC Synchronization Output
53 SCLK System Clock Output
54-55 P21-P20 Port 2, Pins 0,1 In/Output
56-57 P61-P60 Port 6, Pins1,0 In/Output
58-63 P27-P22 Port 2, Pins 2,3,4,5,6,7 In/Output
64-65 P41-P40 Port 4, Pins 0,1 In/Output
66 P31 Port 3, Pin 1 Input
67 P36 Port 3, Pin 6 Output
68 P42 Port 4, Pin 2 In/Output