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Z86C9616PEC
Datasheet
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ZILOG Z86C9616PEC, Z86C9616PSC, Z86C9616VEC, Z86C9616VSC Datasheet

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1
Z86C96
CPS DC-4049-02
GENERAL DESCRIPTION
The Z86C96 microcontroller introduces a new level of sophistication to single-chip architecture. The Z86C96 is a member of the Z8 single-chip microcontroller family with 256 bytes of general-purpose RAM.
The MCU is housed in 64-pin DIP and 68-pin Leaded Chip­Carrier packages and is manufactured in CMOS technol­ogy.
The Z86C96 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many indus­trial and advanced consumer applications.
DC-4049-02 (6-8-93)
Z86C96
CMOS Z8
®
MICROCONTROLLER
4-bit port. The ports are configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory.
There are three basic address spaces available to support this wide range of configuration: program memory, data memory and 236 general-purpose registers.
To unburden the program from coping with the real-time problems such as counting/timing and serial data commu­nication, the Z86C96 offers two on-chip Counter/Timers with a large number of user selectable modes, and a Asynchronous Receiver/Transmitter (UART - see block diagram).
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
C
USTOMER PROCUREMENT SPECIFICATION
2
Z86C96
CPS DC-4049-02
GENERAL DESCRIPTION (Continued)
Functional Block Diagram
Port 3
Counter/
Timers (2)
Interrupt
Control
Port 2
ALU
Flags
Register
Pointer
Register File
256 x 8-Bit
Machine Timing and
Instruction Control
Program
Counter
Vcc GND XTAL R//W /RESETOutput Input
UART
Port 0 Port 1
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
44 8
/AS /DS
Z-BUS When Used
As Address/Data Bus
Port 4Port 5Port 6
I/O
(Bit Programmable)
3
Z86C96
CPS DC-4049-02
PIN DESCRIPTION
P44
VCC
P45
XTAL2
P47
AS
P35
N/C
GND
P32 P50
P51
P43 P42 P36 P31 P41 P40 P27 P26 P25 P24 P23 P22 P60 P61 P21 P20 GND P33 P34 P62
XTAL1
P37 P30
N/C
/RESET
R/W
/DS
P46
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Z86C96
DIP
P00 P01 P02
P03
P63 P17 P16 P15
21 22 23 24
43 42 41 40
P06
P07
VCC
P52
P53 P54
P14 P13 P12 P57 P56 P11 P10 P55
P04 P05
25 26 27 28 29 30 31 32
39 38 37 36 35 34 33
64
64-Pin Dual In-Line Plastic Pin Assignments
4
Z86C96
CPS DC-4049-02
PIN DESCRIPTION (Continued)
Z86C96
PLCC
789
654321 10 11 12 13 14 15 16 17
18 19 20 21 22 23 24 25 26
68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
/RESET
P30
P37
XTAL1
XTAL2
P45
VCC
P44
P43
P42
P36
P31
P41
P40
P26
P25
P27
R/W
/P0DS
/DS P46 P47
/P1DS
/AS
/DTIMERS
P35
N/C
GND
P32 P50 P51 P00 P01
P02
P54
VCC
P07
P14
P13
P12
P57
P56
P11
P10
P55
P53
P52
P06
P04
P03
P05
/SYNC
P24
P23
P22 P60 P61 P21 P20 SCLK
GND P33 P34 P62 P63 P17 P16 P15
68-Pin Plastic Leaded Chip Carrier Pin Assignments
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Z86C96
CPS DC-4049-02
ABSOLUTE MAXIMUM RATINGS
Symbol Description Min Max Units
V
CC
Supply Voltage* –0.3 +7.0 V
T
STG
Storage Temp –65 +150° C
T
A
Oper Ambient Temp † C
Notes:
* Voltages on all pins with respect to GND. † See Ordering Information
Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec­tions of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended pe­riod may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Test Load Diagram).
+5V
From Outpu
t
Under Tes
t
9.1 kΩ
2.1 kΩ
150 pF
Test Load Diagram
PLEASE NOTE
This device will not operate in extended Timing mode. Set Register 248 (F8H), D5 = 0.
6
Z86C96
CPS DC-4049-02
DC CHARACTERISTICS
T
A
= 0°C TA = –40°C Typical
Parameter to +70°C to +105°Cat
Sym VCC = 4.5 V to 5.5 V Min Max Min Max 25°C Units Conditions
Max Input Voltage 7 7 V I
IN
< 250 µA
V
CH
Clock Input High Voltage 3.8 VCC+ 0.3 3.8 VCC+ 0.3 V Driven by External Clock Generator
V
CL
Clock Input Low Voltage –0.3 0.8 –0.3 0.8 V Driven by External Clock Generator
V
IH
Input High Voltage 2.0 VCC+ 0.3 2.0 VCC+ 0.3 V
V
IL
Input Low Voltage –0.3 0.8 –0.3 0.8 V
V
OH
Output High Voltge 2.4 2.4 V IOH = -2.0 mA
V
OH
Output High Voltge VCC–100mV VCC–100mV V I
OH
= -100 µA
V
OL
Output Low Voltage 0.4 0.4 V IOL = +5.0 mA
V
RH
Reset Input High Voltage 3.8 VCC+ 0.3 3.8 VCC+ 0.3 V
V
RL
Reset Input Low Voltage –0.3 0.8 –0.3 0.8 V
I
IL
Input Leakage –2 2 –2 2 µAV
IN
= 0 V, V
CC
I
OL
Output Leakage –2 2 –2 2 µAV
IN
= 0 V, V
CC
I
IR
Reset Input Current –80 –80 µAV
RL
= 0 V
I
CC
Supply Current 35 35 24 mA [1] @ 16 MHz
I
CC1
Standby Current 6.5 6.5 4 mA [1] HALT Mode VIN = O V, VCC@12 MHz
7.0 7.0 4.5 mA [1] HALT Mode V
IN
= O V,VCC@ 16 MHz
I
CC2
Standby Current 10 20 5 µA [1] STOP Mode V
IN
= O V,V
CC
Notes:
[1] All inputs driven to either 0 V or VCC, outputs floating.
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Z86C96
CPS DC-4049-02
AC CHARACTERISTICS
External I/O or Memory Read or Write Timing Diagram
R//W
9
12
19 3
16
13
4
5
8 18 11
6
17
10
15
7
14
21
Port 0, /DM
Port 1
/AS
/DS
(Read)
Port1
/DS
(Write)
A7 - A0 D7 - D0 IN
D7 - D0 OUTA7 - A0
17
External I/O or Memory Read/Write Timing
8
Z86C96
CPS DC-4049-02
AC CHARACTERISTICS
External I/O or Memory Read or Write Timing Table
T
A
= 0°C to +70°CTA = –40°C to +105°C
16 MHz 16 MHz
No Symbol Parameter Min Max Min Max Units Notes
1 TdA(AS) Address Valid to /AS Rise Delay 25 25 ns [2,3] 2 TdAS(A) /AS Rise to Address Float Delay 35 35 ns [2,3] 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 180 180 ns [1,2,3] 4 TwAS /AS Low Width 40 40 ns [2,3]
5 TdAZ(DS) Address Float to /DS Fall 0 0 ns 6 TwDSR /DS (Read) Low Width 135 135 ns [1,2,3] 7 TwDSW /DS (Write) Low Width 80 80 ns [1,2,3] 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 75 75 ns [1,2,3]
9 ThDR(DS) Read Data to /DS Rise Hold Time 0 0 ns [2,3] 10 TdDS(A) /DS Rise to Address Active Delay 50 50 ns [2,3] 11 TdDS(AS) /DS Rise to /AS Fall Delay 35 35 ns [2,3] 12 TdR/W(AS) R//W Valid to /AS Rise Delay 20 25 ns [2,3]
13 TdDS(R/W) /DS Rise to R//W Not Valid 35 35 ns [2,3] 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 25 25 ns [2,3] 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 35 35 ns [2,3] 16 TdA(DR) Address Valid to Read Data Req’d Valid 230 230 ns [1,2,3]
17 TdAS(DS) /AS Rise to /DS Fall Delay 45 45 ns [2,3] 18 TdDI(DS) Data Input Setup to /DS Rise 60 60 ns [1,2,3] 19 TdDM(AS) /DM Valid to /AS Rise Delay 30 30 ns [2,3]
Notes:
[1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See Clock Dependent Formulas table.
Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0.
Clock Dependent Formulas
Number Symbol Equation
1 TdA(AS) 0.40 TpC + 0.32 2 TdAS(A) 0.59 TpC – 3.25 3 TdAS(DR) 2.83 TpC + 6.14 4 TwAS 0.66 TpC – 1.65
6 TwDSR 2.33 TpC – 10.56 7 TwDSW 1.27 TpC + 1.67 8 TdDSR(DR) 1.97 TpC – 42.5 10 TdDS(A) 0.8 TpC
11 TdDS(AS) 0.59 TpC – 3.14 12 TdR/W(AS) 0.4 TpC 13 TdDS(R/W) 0.8 TpC – 15 14 TdDW(DSW) 0.4 TpC
15 TdDS(DW) 0.88 TpC – 19 16 TdA(DR) 4 TpC – 20 17 TdAS(DS) 0.91 TpC – 10.7 18 TsDI(DS) 0.8 TpC – 10 19 TdDM(AS) 0.9 TpC – 26.3
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Z86C96
CPS DC-4049-02
Clock
1
3
4
5
2 2 3
T
IRQ
IN
N
AC CHARACTERISTICS
Additional Timing Diagram
Additional Timing
AC CHARACTERISTICS
Additional Timing Table
T
A
= 0°C to +70°CTA = –40°C to +105°C
16 MHz 16 MHz
No Symbol Parameter Min Max Min Max Units Notes
1 TpC Input Clock Period 62.5 1000 62.5 1000 ns [1] 2 TrC,TfC Clock Input Rise & Fall Times 10 10 ns [1] 3 TwC Input Clock Width 25 25 ns [1] 4 TwTinL Timer Input Low Width 75 75 ns [2]
5 TwTinH Timer Input High Width 3TpC 3TpC [2] 6 TpTin Timer Input Period 8TpC 8TpC [2] 7 TrTin,TfTin Timer Input Rise & Fall Times 100 100 ns [2]
8A TwIL Interrupt Request Input Low Times 70 50 ns [2,4] 8B TwIL Interrupt Request Input Low Times 3TpC 3TpC [2,5] 9 TwIH Interrupt Request Input High Times 3TpC 3TpC [2,3]
Notes:
[1] Clock timing references use 3.8 V for a logic 1 and 0.8 V for a logic 0. [2] Timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30.
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Z86C96
CPS DC-4049-02
AC CHARACTERISTICS
Handshake Timing Diagrams
Input Handshake Timing
Data In
1 2
3
4 5 6
/DAV
(Input)
RDY
(Output)
Next Data In Valid
Delayed RDY
Delayed DAV
Data In Valid
Data Out
/DAV
(Output)
RDY
(Input)
Next Data Out Valid
Delayed RDY
Delayed DAV
Data Out Valid
7
8 9
10
11
Output Handshake Timing
AC CHARACTERISTICS
Handshake Timing Table
T
A
= 0°C to +70°CT
A
= –40°C to +105°C
16 MHz 16 MHz Data
No Symbol Parameter Min Max Min Max Direction
1 TsDI(DAV) Data In Setup Time 0 0 IN 2 ThDI(DAV) Data In Hold Time 145 145 IN 3 TwDAV Data Available Width 110 110 IN 4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 115 115 IN
5 TdDAVId(RDY) DAV Rise to RDY Rise Delay 115 115 IN 6 TdRDY0(DAV) RDY Rise to DAV Fall Delay 0 0 IN 7 TdD0(DAV) Data Out to DAV Fall Delay TpC TpC OUT 8 TdDAV0(RDY) DAV Fall to RDY Fall Delay 0 0 OUT
9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 115 115 OUT 10 TwRDY RDY Width 110 110 OUT 11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay 115 115 OUT
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Z86C96
CPS DC-4049-02
Low Margin:
Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specifcation requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncer­tain and that, in addition to all other limitations on Zilog
liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in mate­rials and workmanship.
Zilog’s products are not authorized for use as critical compo­nents in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056
© 1993 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of mer­chantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
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