GENERAL DESCRIPTION
C
USTOMER PROCUREMENT SPECIFICATION
Z86C95
CMOS Z8® DIGITAL
SIGNAL PROCESSOR (DSP)
Z86C95 DSP
CPS DC-4067-13
The Z86C95 MCU (Microcontroller Unit ) introduces a new
level of sophistication to Superintegration™ ICs. The
Z86C95 is a member of the Z8® single-chip microcontroller
family incorporating a CMOS ROMless Z8 microcontroller
with an embedded DSP processor for digital servo control.
The DSP slave processor can perform 16-bit x 16-bit
multiplicates and accumulates in one clock cycle. Additionally, the Z86C95 is further enhanced with a hardwired
16-bitx16-bit multiplier and a 32-bit/16-bit divider, three
16-bit counter timers with capture and compare registers,
a half flash 8-channel 8-bit A/D converter with a 2 µsec
conversion time, an 8-bit DAC with 1/4 programmable gain
stage, UART, serial peripheral interface, and a PWM
output channel (Functional Block Diagram). It is fabricated
using CMOS technology and offered in an 80-pin QFP, 84pin PLCC, or 100-pin VQFP package.
The Z86C95 provides up to 16 output address lines thus
permitting an address space of up to 64 Kbytes of data and
program memory each. Eight address outputs (AD7-AD0)
are provided by a multiplexed, 8-bit, Address/Data bus.
The remaining 8 bits are provided via output address bits
A15-A8.
There are 256 registers located on chip and organized as
236 general-purpose registers, 16 control and status registers, and four I/O port registers. The register file can be
divided into sixteen groups of 16 working registers each.
Configuration of the registers in this manner allows the use
of short format instructions; in addition, any of the individual registers can be accessed directly. Also, the Z86C95
contains 512 bytes of DSP Program RAM and 128 words
of DSP data RAM.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
Ground GND V
CC
V
DD
SS
OPERATING ERRATA
This notice only applies to devices top marked "Z86C9524
ASC/FSC/VSC" with a date code of 9237 or later.
1. A DSP load to the DAC Register fails below approximately VCC = 4.7V.
2. Clipping occurs in the linearity of the DAC with a 100K
load at about 3.3V output (VDHI = 3.5V).
3. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds.
4. ICC2 at STOP Mode and DSP Pause will show a current
of 1-2 mA, then will jump to 5-7 mA, and will settle at 34 mA. Settling time is about 10-15 seconds.
DC-4067-13 (5-17-94)
The following operating errata only applies to devices
topmarked with "Z86C95 ASC/FSC/VSC."
1. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds.
2. ICC2 at STOP Mode and DSP Pause will show a
current of 1-2 mA, then will jump to 5-7 mA, and will
settle at 3-4 mA. Settling time is about 10-15 seconds.
The following operating errata only applies to devices
topmarked with "Z86C9540 ASC/FSC/VSC or SL 1636."
1. ICC1 at HALT Mode will show a current of 17-18 mA,
then will jump to 40-70 mA, and will settle between 1724 mA. Settling time is about 10-15 seconds.
1
GENERAL DESCRIPTION (Continued)
Z86C95 DSP
CPS DC-4067-13
2. ICC2 at STOP Mode and DSP Pause will show a
current of 1-2 mA, then will jump to 5-7 mA, and will
settle at 3-4 mA. Settling time is about 10-15 seconds.
/AS /DS
Output Input
Port 3
SPI
UART
Three 16-Bit
Counter/
Timers
32 ÷ 16
Divider
16 x 16
Multiplier
Interrupt
Control
Vcc GND
ALU
Flags
Register
Pointer
Register File
256 x 8-Bit
XTAL
Machine Timing and
Instruction Control
Program
Counter
3. The zero error for the ADC at 25°C is about 180 mV.
R//W /RESET
/WAIT
Digital Signal Processor
DSP RAM
Bank 1
DSP RAM
Bank 2
Program
RAM
Port 2
I/O
(Bit Programmable)
Address
A15-A0*
* In multiplexed mode,
A7-A0 reflects the DSP
address bus for emulation.
Functional Block Diagram
AD7-AD0
8
Address/Data
ADC
8 Channel
Analog In
DAC
Analog
Out
PWM
PWM
2
PIN DESCRIPTION
P2(0)
P2(1)
P2(2)
P2(3)
P2(5)
P2(6)
P2(7)
VSS
ANGND
AVCC
VAHI
VALO
ANA(0)
ANA(1)
ANA(2)
A3
A2A1A0
AD0
VSS
AD1
AD2
AD3
AD4
AD5
AD6
AD7
R/W
/DS
/AS
P2(4)
C
1
24
25
40
41
64
65
80
/WAIT
C01
DSP_SSN
C02
DSP_RW
DSP_SYN
SLAVESELSKDI
DO
VDD
A15
A14
VSS
Z86C95
80-Lead QFP
A13
A12
A11
A10A9A8
A7
A6
A5
Z86C95 DSP
CPS DC-4067-13
A4
DAC
VDD
VDHI
P3(7)
P3(6)
P3(5)
P3(3)
P3(2)
P3(0)
ANA(3)
ANA(4)
ANA(5)
ANA(6)
ANA(7)
VDLO
P3(1)
XTAL1
XTAL2
PWM
/RESET
SCLK
SYNC
IACK
P3(4)
80-Lead QFP Pin Assignments
3
PIN DESCRIPTION (Continued)
1
84
3
424332535411127574
ANA4
ANA5
ANA6
ANA7
DAC
VDHI
VDD
P37
P36
P35
P33
P32
P31
P30
XTAL1
XTAL2
PWM
/RESET
SCLK
SYNC
C01
C02
DSP_SYNC
DSP_RW
SLAVESEL
SKD1D0
VDD
VSS
A15
A14
A13
A12
A11
A10A9A8A7A6
A5
VDLO
ANA3
ANA2
N/C
ANA1
ANA0
VALO
VAHI
ANGND
AVCC
84-Lead PLCC
VSS
P27
Z86C95
P26
P25
P24
P23
P22
P21
P20
/WAIT
N/C
Z86C95 DSP
CPS DC-4067-13
DSP_SSN
3
N/C
IACK
P34
/AS
/DS
R//W
AD7
AD6
AD5
AD4
AD3
AD2
84-Lead PLCC Pin Assignments
AD1
VSS
AD0
A0
A1
A2
A3
A4
DSP-A8
4
NC
SYNC
SCLKNCRESET
PWM
XTAL2
XTAL1
P30
P31
P32
P33
P35
P36
P37
VDD
VDHI
DAC
VDLO
ANA7
ANA6
ANA5
ANA4NCNC
A4A5A6A7A8A9A10
A11
A12
A13
A14
A15
VSS
VDDNCD0D1SK
SLAVESEL
DSP_RW
DSP_SYNC
C02
C01
DSP_SSN
/WAIT
8
506065707555251510512080859095454035
30
PIN DESCRIPTION (Continued)
Z86C95 DSP
CPS DC-4067-13
NCNCNC
DSP_A
A3
A2A1A0
AD0
AD1
AD2
VSS
Z86C95
100-Lead VQFP
AD3
AD4
AD5
AD6
AD7
R//W
/DS
/AS
IACKNCNC
P34
NC
NC
NC
P20
P21
P22
P23
P24
P25
P26
P27
VSS
NCNCNC
100-Pin VQFP Pin Assignments
AVCC
ANGND
AVHI
AVLO
ANA0
ANA1
ANA2
ANA3
NCNCNC
5
PIN FUNCTIONS
t
Z86C95 DSP
CPS DC-4067-13
Address
A15-A0
A7-A0
(DSP Emulator
Support)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
+5V
GND
P20
Clock
XTAL1
P21
XTAL2
P22
Emulation Pins
IACK
SCLK
P23
P24
P25
/SYNC
P26
DSP
Single
Step
DSP-A8
P27
DSP
Read
Write
DSP_SSN
Z86C95
P30
P31
DSP
Sync
Timing and Control
/DS
/AS
P36
/RESET
P37
DSP_RW
P32
DSP_SYNC
P33
P34
P35
Analog Power
R//W
VAHI
ANVCC
ANGND
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VDLO
VDHI
DAC
PWM
SLAVESEL
/WAIT
VALO
C01
C02
SK
DO
Analog
Inputs
To A/D
D/A Ref
Voltage
DAC Output
PWM Output
Compare
Outputs
SPI Slave Selec
SPI Clock
DI
SPI Data
Asynchronous
WAIT States
Port 2
(Bit Programmable I/O)
Port 3
A/D
Ref Voltage
6
ABSOLUTE MAXIMUM RATINGS
Z86C95 DSP
CPS DC-4067-13
Symbol Description Min Max Unit
V
DD
T
STG
T
A
Notes:
* Voltages on all pins with respect to GND.
† See Ordering Information
Supply Voltage* –0.3 +7.0 V
Storage Temp –65 +150 C
Oper Ambient Temp † † C
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted (Test Load Diagram).
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended period may affect device reliability.
I
OL
DUT
Device Under Test
V Commutation
50 pf
I
OH
Test Load Diagram
7
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V ± 10%
TA = 0°C to +70°C Typical
Sym Parameter Min Max at 25°C Units Conditions
Max Input Voltage 7 V IIN 250 µA
V
Clock Input High Voltage 0.8 V
CH
V
Clock Input Low Voltage –0.03 0.1xV
CL
V
Input High Voltage 0.6xV
IH
V
Input Low Voltage –0.3 0.2xV
IL
V
Output High Voltge 2.0 V IOH = –1.0 mA
OH
V
Output High Voltge VCC – 100 mV V IOH = –100 µA
OH
V
Output Low Voltage 0.4 V IOL = +1.0 mA
OL
V
Reset Input High Voltage 0.8xV
RH
V
Reset Input Low Voltage –0.03 0.2xV
Rl
I
Input Leakage –2 2 µA Test at 0V, V
IL
I
Output Leakage –2 2 µA Test at 0V, V
OL
I
Reset Input Current –180 µAV
IR
I
Supply Current 50 40 mA @ 24 MHz [1]
CC
I
HALT 15 10 mA HALT Mode VIN=OV, VCC @ 24 MHz [1]
CC1
I
STOP and Pause Mode 20 6 µA STOP Mode VIN=OV, VCC [1]
CC2
I
Auto Latch Low Current –10 10 5 µA
ALL
Note:
[1] All inputs driven to 0V, VCC and outputs floating.
CC
CC
CC
V
CC
CC
V
CC
CC
V
CC
CC
V Driven by External Clock Generator
V Driven by External Clock Generator
V
V
V
V
CC
CC
RL
= 0V
Z86C95 DSP
CPS DC-4067-13
8
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
TA = 0°C to +70°C Typical
Sym Parameter Min Max at 25°C Units Conditions
Max Input Voltage 7 V IIN 250 µA
V
Clock Input High Voltage 3.8 V
CH
V
Clock Input Low Voltage –0.03 0.8 V Driven by External Clock Generator
CL
V
Input High Voltage 2.0 V
IH
V
Input Low Voltage –0.3 0.8 V
IL
V
Output High Voltge 2.4 V IOH = –2.0 mA
OH
V
Output High Voltge VCC – 100mV V IOH = –100 µA
OH
V
Output Low Voltage 0.4 V IOH = +2.0 mA
OL
V
Reset Input High Voltage 3.8 V
RH
V
Reset Input Low Voltage –0.03 0.8 V
Rl
I
Input Leakage –2 2 µA Test at 0V, V
IL
I
Output Leakage –2 2 µA Test at 0V, V
OL
I
Reset Input Current –180 µAV
IR
I
Supply Current 82 50 mA @ 24 MHz [1]
CC
CC
CC
CC
120 70 mA @ 33 MHz [1]
150 85 mA @ 40 MHz [1], [2]
V Driven by External Clock Generator
V
V
CC
CC
RL
= 0V
Z86C95 DSP
CPS DC-4067-13
I
HALT 20 13 mA HALT Mode VIN=OV, VCC @ 24 MHz [1]
CC1
30 20 mA HALT Mode VIN=OV, VCC @ 33 MHz [1]
45 30 mA HALT Mode VIN=OV, VCC @ 40 MHz [1], [2]
I
STOP and Pause Mode 20 6 µA STOP Mode VIN=OV, VCC [1]
CC2
I
Auto Latch Low Current –20 20 5 µA
ALL
Note:
[1] All inputs driven to 0V, VCC and outputs floating.
[2] Preliminary values, to be characterized.
9
AC CHARACTERISTICS
External I/O or Memory Read/Write Timing Diagram
R/W, /DM
Z86C95 DSP
CPS DC-4067-13
Port 0
Port 1
/AS
/DS
(Read)
Port1
19
12
20
13
A8 - A15
16
A0 - A7
2
4
1
17
A0 - A7
3
8 11
5
6
D0 - D7 OUT
14
D0 - D7 IN
7
21
A0 - A7
9
10
A0-A7
15
/DS
(Write)
External I/O or Memory Read/Write Timing
10
Z86C95 DSP
CPS DC-4067-13
AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
TA = 0°C to +70°C
40 MHz** 33 MHz 24 MHz
No Sym Parameter Min Max Min Max Min Max Units
1 TdA(AS) Address Valid To /AS Rise Delay 8 15 22 ns
2 TdAS(A) /AS Rise To Address Hold Time 15 20 25 ns
3 TdAS(DI) /AS Rise Data In Req’d Valid Delay 75 96 130 ns
4 TwAS /AS Low Width 10 15 28 ns
5 TdAZ(DSR) Address Float To /DS Fall (Read) 0 0 0 ns
6 TwDSR /DS (Read) Low Width 60 65 100 ns
7 TwDSW /DS (Write) Low Width 35 40 65 ns
8 TdDSR(DI) /DS Fall (Read) To Data Req'd Valid Delay 40 45 80 ns
9 ThDSR(DI) /DS Rise (Read) to Data In Hold Time 0 0 0 ns
10 TdDS(A) /DS Rise To Address Active Delay 20 25 40 ns
11 TdDS(AS) /DS Rise To /AS Delay 16 16 30 ns
12 TdR/W(AS) R/W To Valid /AS Rise Delay 10 12 26 ns
13 TdDS(R/W) /DS Rise To R/W Not Valid Delay 12 12 30 ns
14 TdDO(DSW) Data Out To /DS Fall (Write) Delay 12 12 34 ns
15 ThDSW(DO) /DS Rise (Write) To Data Out Hold Time 12 12 34 ns
16 TdA(DI) Address Valid To Data Req’d Valid Delay 90 115 160 ns
17 TdAS(DSR) /AS Rise To /DS Fall (Read) Delay 20 20 40 ns
19 TdDM(AS) /DM Valid To /AS Rise Delay 10 10 22 ns
20 TdDS(DM) /DS Rise To /DM Valid Delay 15 15 35 ns
21 ThDS(A) /DS Rise To Address Valid Hold Time 15 15 30 ns
22 TdXT(SCR) XTAL Falling to SCLK Rising 30 35 40 ns
23 TdXT(SCF) XTAL Falling to SCLK Falling 30 35 40 ns
24 TdXT(DSRF) XTAL Falling to/DS Read Falling 40 45 50 ns
25 TdXT(DSRR) XTAL Falling to /DS Read Rising 30 35 45 ns
26 TdXT(DSWF) XTAL Falling to /DS Write Falling 40 45 50 ns
27 TdXT(DSWF) XTAL Falling to /DS Write Rising 30 35 45 ns
28 TsW(XT) Wait Set-up Time 5 5 5 ns
29 ThW(XT) Wait Hold Time 15 15 15 ns
30 TwW Wait Width (One Wait Time) 20 20 25 ns
Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
** Preliminary values, to be characterized.
11
AC CHARACTERISTICS (Continued)
Timing Diagrams
XTAL1
(External Clock Drive)
SCLK
Z86C95 DSP
CPS DC-4067-13
2322
XTAL1
/DS
(Read)
/DS
(Write)
24
26
XTAL/SCLK To DSR and DSW Timing
T1 T2 TW TW TW T3 T1
25
27
12
SCLK
/AS
/DS
/WAIT
30
28
29
XTAL/SCLK To WAIT Timing
Clock
1
34822
3
6
577
9
T IN
IRQ N
Z86C95 DSP
CPS DC-4067-13
Additional Timing
AC CHARACTERISTICS
Additional Timing Table
TA = 0°C to +70°C
40 MHz 24 MHz 33 MHz
No Symbol Parameter Min Max Min Max Min Max Units Notes
1 TpC Input Clock Period 25 1000 42 1000 30 1000 ns [1]
2 TrC,TfC Clock Imput Rise & Fall Times 5 10 5 ns [1]
3 TwC Input Clock Width 8 11 10 ns [1]
4 TwTinL Timer Input Low Width 75 75 75 ns [2]
5 TwTinH Timer Input High Width 3 TpC 3 TpC 3 TpC [2]
6 TpTin Timer Input Period 8 TpC 8 TpC 8 TpC [2]
7 TrTin,TfTin Timer Input Rise & Fall Times 100 100 100 ns [2]
8a TwIL Interrupt Request Input Low Times 70 70 70 ns [2,4]
8b TwIL Interrupt Request Input Low Times 5 TpC 5 TpC 5 TpC [2,5]
9 TwIH Interrupt Request Input High Times 3 TpC 3 TpC 3 TpC [2,3]
Notes:
[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.
[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
[3] Interrupt references request via Port 3.
[4] Interrupt request via Port 3 (P33-P31).
[5] Interrupt request via Port 30.
13
AC CHARACTERISTICS
13456
2
7891011
Handshake Timing Diagrams
Z86C95 DSP
CPS DC-4067-13
Data In
/DAV
(Input)
RDY
(Output)
Data Out
/DAV
(Output)
Data In Valid
Delayed DAV
Input Handshake Timing
Data Out Valid
Next Data In Valid
Delayed RDY
Next Data Out Valid
Delayed DAV
RDY
(Input)
Delayed RDY
Output Handshake Timing
14
Z86C95 DSP
CPS DC-4067-13
AC CHARACTERISTICS
Handshake Timing Table
TA = 0°C to +70°C Data
No Symbol Parameter Min Max Units Direction
1 TsDI(DAV) Data In Setup Time to /DAV 0 ns In
2 ThDI(DAV) RDY to Data In Hold Time 0 ns In
3 TwDAV /DAV Width 40 ns In
4 TdDAVIf(RDYf) /DAV to RDY Delay 70 ns In
5 TdDAVIr(RDYr) DAV Rise to RDY Wait Time 40 ns In
6 TdRDYOr(DAVIf) RDY Rise to DAV Delay 0 ns In
7 TdD0(DAV) Data Out to DAV Delay TpC ns Out
8 TdDAV0f(RDYIf) /DAV to RDY Delay 0 ns Out
9 TdRDYIf(DAVOr) RDY to /DAV Rise Delay 70 ns Out
10 TwRDY RDY Width 40 ns Out
11 TdRDYIr(DAVOf) RDY Rise to DAV Wait Time 40 ns Out
15
CPS DC-4067-13
AC CHARACTERISTICS (Continued)
A/D Converter Electrical Characteristics
VCC = 3.3V ± 10%
Parameter Minimum Typical Maximum Units
Resolution 8 Bits
Integral non-linearity 0.5 1 LSB
Differential non-linearity 0.5 1 LSB
Zero Error at 25°C 5.0 mV
Supply Range 2.7 3.0 3.3 Volts
Power dissapation, no load 20 40 mW
Clock frequency 24 MHz
Input voltage range VA
LO
Conversion time 2 µsec
Input capacitance on ANA 25 40 pF
VAHI range VA
VALO range AN
VAHI -–VA
Notes:
Voltage 2.7V – 3.3V
Temp 0-70°C
LO
+2.5 AV
LO
GND
2.5 AV
VA
HI
CC
AVCC–2.5 Volts
CC
Z86C95 DSP
Volts
Volts
Volts
D/A Converter Electrical Characteristics
VCC = 3.3V ± 10%
Parameter Minimum Typical Maximum Units
Resolution 8 Bits
Integral non-linearity 0.25 1 LSB
Differential non-linearity 0.25 0.5 LSB
Setting time, 1/2 LSB 1.5 3.0 µsec
Zero Error at 25°C1020mV
Full Scale error at 25°C 0.25 0.5 LSB
Supply Range 2.7 3.0 3.3 Volts
Power dissapation, no load 10 mW
Ref Input resistance 2K 4K 10K Ohms
Output noise voltage 50 µVp-p
VD
range at 3 volts 1.5 1.8 2.1 Volts
HI
VDLO range at 3 volts 0.2 0.5 0.8 Volts
VDHI–VDLO, at 3 volts 1.3 1.6 1.9 Volts
Capacitive output load, CL 20 pF
Resistive output load, RL 50K Ohms
Output slew rate 1.0 3.0 V/µsec
Notes:
Voltage 2.7V – 3.3V
Temp 0-70°C
16
Z86C95 DSP
CPS DC-4067-13
A/D Converter Electrical Characteristics
VCC = 5.0V ± 10%
Parameter Minimum Typical Maximum Units
Resolution 8 Bits
Integral non-linearity 0.5 1 LSB
Differential non-linearity 0.5 1 LSB
Zero Error at 25°C45mV
Supply Range 4.5 5.0 5.5 Volts
Power dissapation, no load 50 85 mW
Clock frequency 33 MHz
Input voltage range VA
LO
VA
HI
Volts
Conversion time 2 µsec
Input capacitance on ANA 25 40 pF
VAHI range VA
VALO range AN
VAHI -–VA
Notes:
Voltage 4.5V –5.5V
Temp 0-70°C
LO
+2.5 AV
LO
GND
AVCC–2.5 Volts
2.5 AV
CC
CC
Volts
Volts
D/A Converter Electrical Characteristics
VCC = 5.0V ± 10%
Parameter Minimum Typical Maximum Units
Resolution 8 Bits
Integral non-linearity 0.25 1 LSB
Differential non-linearity 0.25 0.5 LSB
Setting time, 1/2 LSB 1.5 3.0 µsec
Zero Error at 25°C1020mV
Full Scale error at 25°C 1 2 % FSR
Supply Range 4.5 5.0 5.5 Volts
Power dissapation, no load 50 85 mW
Ref Input resistance 2K 4K 10K Ohms
Output noise voltage 50 µVp-p
VD
range at 3 volts 2.6 3.5 Volts
HI
VDLO range at 5V volts 0.8 1.7 Volts
VDHI–VDLO, at 5V volts 0.9 2.7 Volts
Capacitive output load, CL 30 pF
Resistive output load, RL 20K* Ohms
Output slew rate 1.0 3.0 V/µsec
Notes:
Voltage 4.5V - 5.5V
Temp 0-70°C
* 100K for 24 MHz device.
17
Z86C95 DSP
CPS DC-4067-13
© 1994 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
18
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agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
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Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
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