![](/html/e2/e2d5/e2d5e06962fff85c88daf8656fa72367667db52f52097ecee8ad2af4a3eaa53b/bg1.png)
GENERAL DESCRIPTION
C
USTOMER PROCUREMENT SPECIFICATION
Z86C93
CMOS Z8® MULT/DIV
MICROCONTROLLER
CPS DC-4020-12
Z86C93
The Z86C93 is a CMOS ROMless Z8 microcontroller enhanced with a hardwired 16-bit x 16-bit multiplier,
32-bit/16-bit divider, and three 16-bit counter timers (see
Functional Block Diagram). A capture register and a fast
decrement mode are also provided. It is offered in 40-pin
PDIP, 44-pin PLCC, 44-pin QFP, and 48-pin VQFP packages. The Z86C93 is functionally compatible with the
Z86C91, yet it offers a more powerful mathematical capability. In the PDIP package, the Z86C93 is fully pin compatible with the Z86C91. In the PLCC package, the Z86C93 is
also pin compatible to the Z86C91, with the addition of four
signals (SCLK, /IACK, /SYNC, and /WAIT). The /WAIT
signal is only available on the 25 MHz and 33 MHz devices.
The Z86C93 provides up to 16 output address lines permitting an address space of up to 64 Kbytes of data and
program memory each. Eight address outputs (AD7-AD0)
are provided by a multiplexed, 8-bit, Address/Data bus.
The remaining 8 bits can be provided by the software
configuration of Port 0 to output address bits A15-A8.
There are 256 registers located on chip and organized as
236 general-purpose registers, 16 control and status registers, one reserved register, and up to three I/O port
registers. The register file can be divided into 16 groups of
16 working registers each. Configuration of the registers in
this manner allows the use of short format instructions; in
addition, any of the individual registers can be accessed
directly. There are an additional 17 registers implemented
in the Expanded Register File in Banks D and E. Two of the
registers may be used as general-purpose registers, while
15 registers supply the data and control functions for the
Multiply/Divide Unit and additional Counter/Timer blocks.
Notes:
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
Ground GND V
CC
V
DD
SS
DC-4020-12 (2-16-94)
1
![](/html/e2/e2d5/e2d5e06962fff85c88daf8656fa72367667db52f52097ecee8ad2af4a3eaa53b/bg2.png)
GENERAL DESCRIPTION (Continued)
Output
Input
VCC GND
XTAL
/AS
/DS
R//W
/RESET
SCLK
IACK
/WAIT
/SYNC
(25 MHz & 33 MHz
CPS DC-4020-12
Z86C93
Devices Only.)
Port 3
UART
Three 16-Bit
Counter/Timers
32 ÷ 16
Divider
16 x 16
Multiplier
Interrupt
Control
ALU
FLAGS
Register
Pointer
Register File
256 x 8-Bit
Machine Timing, Emulation
and Instruction Control
Program
Counter
Port 2
I/O
(Bit Programmable)
Port 0
44
Address or I/O
(Nibble Programmable)
Functional Block Diagram
Port 1
8
Address/Data
2
![](/html/e2/e2d5/e2d5e06962fff85c88daf8656fa72367667db52f52097ecee8ad2af4a3eaa53b/bg3.png)
PIN CONFIGURATION
CPS DC-4020-12
Z86C93
VCC
XTAL2
XTAL1
P37
P30
/RESE
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
P03
P04 P13
P05
P06
P07
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
Z86C93
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
2714
26
25
24
23
22
21
P36
P31
P27
P26
P25
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
P14
P12
P11
P10
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
XTAL2
XTAL1
Z86C93
MCU
P07
P06
+5V
P10
P11
P12
P13
P37
P30
SCLK
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
P05
P04
P03
P27
P31
P36
44-Pin PLCC Package
(20 MHz)
P26
P14
P25
39
38
37
36
35
34
33
32
31
30
29
/SYNC
NC
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
40-Pin DIP Package
(20 MHz)
NC
P24
P23
P22
P21
P20
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
1234567891011
/RESET
R//W
/DS
Z86C93
MCU
/AS
P35
GND
P33
P32
P34
P00
P17
P01
P16
P02
P15
22
21
20
19
18
17
16
15
14
13
12
IACK
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P25
P26
P27
P31
P36
NC
+5V
XTAL2
XTAL1
P37
P30
SCLK
NC
P24
P23
P22
P21
P20
P33
P34
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
43
44
45
46
47
48
23456789101112
1
NC
R//W
/RESET
Z86C93
/AS
/DS
MCU
P35
GND
P32
P17
P00
P16
P01
P15
P02
25
NC
24
23
22
21
20
19
18
17
16
15
14
13
IACK
/SYNC
P14
P13
P12
P11
P10
P07
NC
P06
P05
P04
P03
44-Pin QFP Package
(20 MHz)
48-Pin VQFP Package
(20 MHz)
3
![](/html/e2/e2d5/e2d5e06962fff85c88daf8656fa72367667db52f52097ecee8ad2af4a3eaa53b/bg4.png)
PIN CONFIGURATIONS (Continued)
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
CPS DC-4020-12
Z86C93
VCC
XTAL2
XTAL1
P37
P30
/RESE
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
P03
P04 P13
P05
P06
P07
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
Z86C93
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
2714
26
25
24
23
22
21
P36
P31
P27
P26
P25
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15
P14
P12
P11
P10
/RESET
R//W
/DS
/AS
P35
GND
P32
P00
P01
P02
IACK
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
Z86C93
MCU
44-Pin PLCC Package
(25 MHz and 33 MHz)
39
/WAIT
38
P24
37
P23
36
P22
35
P21
34
P20
33
P33
32
P34
31
P17
30
P16
29
P15
P25
P26
P27
P31
P36
+5V
XTAL2
XTAL1
P37
P30
SCLK
40-Pin DIP Package
(25 MHz and 33 MHz)
/WAIT
P24
P23
P22
P21
P20
P33
33 32 31 30 29 28 27 26 25 24 23
34
35
36
37
38
39
40
41
42
43
44
1234567891011
/RESET
R//W
/DS
Z86C93
MCU
/AS
P35
GND
P32
P34
P00
P17
P01
P16
P02
P15
22
21
20
19
18
17
16
15
14
13
12
IACK
/SYNC
P14
P13
P12
P11
P10
P07
P06
P05
P04
P03
P25
P26
P27
P31
P36
NC
+5V
XTAL2
XTAL1
P37
P30
SCLK
/WAIT
P24
P23
P22
P21
P20
P33
P34
36 35 34 33 32 31 30 29 28 27 26
37
38
39
40
41
42
43
44
45
46
47
48
23456789101112
1
NC
R//W
/RESET
Z86C93
/AS
/DS
MCU
P35
GND
P32
P17
P00
P16
P01
P15
P02
25
NC
24
23
22
21
20
19
18
17
16
15
14
13
IACK
/SYNC
P14
P13
P12
P11
P10
P07
NC
P06
P05
P04
P03
44-Pin QFP Package
(25 MHz and 33 MHz)
4
48-Pin VQFP Package
(25 MHz and 33 MHz)