ZILOG Z86C7216FSC, Z86C7216PSC, Z86C7216VSC, Z86C9216VSC, Z86L7208FSC Datasheet

1

P

RODUCT

S

PECIFICATION

FEATURES

ROM

Part

Z86C72 16 748 31 4.5V to 5.5V Z86C92 0 748 31 4.5V to 5.5V

Z86L72 16 748 31 2.0V to 3.9V Z86L92 0 748 31 2.0V to 3.9V

Note: *General-Purpose

■

Expanded Register File Control Registers

■

Low Power Consumption - 40 mW (typical)

■

Three Standby Modes: – STOP

– HALT – Low V oltage

■

Automatic External ROM Access Beyond 16K (Z86LX2/C72 Version)

■

Special Architecture to Automate Both Generation and Reception of Complex Pulses or Signals:

– One Programmable 8-Bit Counter/Timer with Two

Capture Register

– One Programmable 16-Bit Counter/Timer with

One Capture Register

(KB)

RAM*

(Bytes) I/O Voltage Range

Z86C72/C92/L72/L92

IR M

ICROCONTROLLER

– Programmable Input Glitch Filter for Pulse

Reception

■

Five Priority Interrupts – Three External

– Two Assigned to Counter/Timers

■

Low Voltage Detection and Standby Mode

■

Programmable Watch-Dog/Power-On Reset Circuits

■

Two Independent Comparators with Programmable Interrupt Polarity

■

On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC (mask option), or External Clock Drive

■

Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3 – All Eight Port 2 Bits at one time or Not

– Pull-Ups Automatically Disabled Upon Selecting

Individual Pins as Outputs

■

Maskable Mouse/Trackball Interface on P00 Through P03 is available on the L72 version.

■

32 kHz Oscillator Mask Option

1

GENERAL DESCRIPTION

The Z86LX2/CX2 family of IR (Infrared) are ROM/ROMless-based members of the Z8 controller family with 768 bytes of internal RAM. The differentiating factor between these devices is the availability of RAM, ROM and package options. The use of external memory enables these Z8 microcontrollers to be used where code flexibility is required. Offering the 5V versions (Z86CXX) and gives optimum performance in both the low and high voltage ranges. Zilog's CMOS microcontrollers

DS97LVO0900

®

MCU single-chip micro-

P R E L I M I N A R Y

offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up resistors. The Z86LX2/CX2 product line offers easy hardware/software system expansion with cost-effective and low power consumption.

The Z86LX2/CX2 architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow

6-1

Z86C72/C92/L72/L92 IR Microcontroller Zilog

GENERAL DESCRIPTION (Continued)

access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z86C72/C92/L72/L92 offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications.

Many applications demand powerful I/O capabilities. The Z86LX2/CX2 family fulfills this with three package options in which the L72 version provides 31 pins of dedicated input and output. These lines are grouped into four ports. Each port consists of eight lines (Port 3 has seven lines) and is configurable under software control to provide timing, status signals, parallel I/O with or without handshake, and an address/data bus for interfacing external memory.

There are five basic address spaces available to support a wide range of configurations: Program Memory, Register

HI16

8

File, Expanded Register File, Extended Data RAM and External Memory. The register file is composed of 256 bytes of RAM. It includes four I/O port registers, 16 control and status registers and the rest are General-Purpose registers. The Extended Data RAM adds 512 bytes of usable general-purpose registers. The Expanded Register FIle consists of two additional register groups (F and D).

To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86LX2/CX2 family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two on-board comparators to process analog signals with separate reference voltages (Figure 2).

LO16

8

Input

SCLK

Glitch

Filter

1

2

48

Clock

Divider

Edge Detect Circuit

16-Bit

T16

16

8

TC16H

HI8 LO8

8

8-Bit

T8

8

TC8H

TC16L

TC8L

Timer 16

8

And/Or

Logic

8

Timer 8/16

Timer 8

6-2

Figure 1. Counter/Timer Block Diagram

P R E L I M I N A R Y

DS97LVO0900

1

Z86C72/C92/L72/L92

Zilog IR Microcontroller

P00 P01 P02 P03

P04 P05 P06 P07

P10

P11 P12 P13 P14 P15 P16 P17

P20 P21 P22 P23 P24 P25 P26 P27

Port 0

Port 1

Port 2

Register Bus

ROM

16K/0K x 8

Expanded

Register

512 x 8-Bit

Counter/Timer 8

Register File

256 x 8-Bit

Internal Data Bus

File

8-Bit

Internal

Address Bus

Register Bus

Expanded

Counter/Timer 16

Z8 Core

16-Bit

Port 3

Machine

Timing

&

Instruction

Control

Power

P31 P32 P33

P34 P35 P36 P37

XTAL

/AS /DS R/W /RESET

VDD VSS

Figure 2. Functional Block Diagram

Note: All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

CC

Ground GND V

V

DD SS

DS97LVO0900

P R E L I M I N A R Y

6-3

Z86C72/C92/L72/L92 IR Microcontroller Zilog

PIN DESCRIPTION

R//W

P25 P26 P27 P04 P05 P06 P14 P15 P07

VDD

P16

P17 XTAL2 XTAL1

P31

P32

P33

P34

/AS

1

Z86C72/C92

Z86L72/L92

DIP

20 21

40

/DS P24 P23 P22 P21 P20 P03 P13 P12 VSS P02 P11 P10 P01 P00 Pref1 P36 P37 P35 /RESET

Figure 3. 40-Pin DIP Pin Assignments

P20

P03

P13

P12

VSS

P02

P11

P10

P21 P22 P23 P24

/DS

R//RL

R//W

P25 P26 P27 P04

7

17

6

P05

P06

P14

1

Z86C72/C92

Z86L72/L92

PLCC

P15

P07

VDD

P16

P17

Figure 4. 44-Pin PLCC Pin Assignments

P01

40

29

2818

XTAL2

P00

39

XTAL1

Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31

6-4

P R E L I M I N A R Y

DS97LVO0900

1

Z86C72/C92/L72/L92

Zilog IR Microcontroller

P20

P03

P13

P12

VSS

P02

P11

P10

P21 P22 P23 P24

/DS

R//RL

R//W

P25 P26 P27 P04

34

44

1

P05

P06

Z86C72/C92

Z86L72/L92

QFP

P14

P15

P07

VDD

P16

P17

Figure 5. 44-Pin QFP Pin Assignments

P01

2333

12

11

XTAL2

P00

22

XTAL1

Pref1 P36 P37 P35 /RESET VSS /AS P34 P33 P32 P31

DS97LVO0900

P R E L I M I N A R Y

6-5

Z86C72/C92/L72/L92 IR Microcontroller Zilog

PIN DESCRIPTION (Continued)

Table 1. Pin Identiﬁcation

40-Pin

DIP #

26 27 30 34

5 6 7

10 28

29 32 33

8

9 12 13

35 36 37 38 39

2

3

4 16

17 18 19 22 24 23

20 40

1 21 15 14 11 31 25

44-Pin

PLCC

40 41 44

5 17 18 19 22

42 43

3

4 20 21 25 26

6

7

8

9 10 14 15 16

29 30 31 32 36 38 37

33 11 13 35 28 27

23,24

1,2,34

39 12

44-Pin

QFP# Symbol Direction Description

23 24 27 32 44

1 2 5

25 26 30 31

3 4 8 9

33 34 35 36 37 41 42 43

12 13 14 15 19 21 20

16 38 40 18 11 10

6,7

17,28,29

22 39

P00 P01 P02 P03 P04 P05 P06 P07

P10 P11 P12 P13 P14 P15 P16 P17

P20 P21 P22 P23 P24 P25 P26 P27

P31 P32 P33 P34 P35 P36 P37

/AS

/DS

R//W

/RESET

XTAL1 XTAL2

V

DD

V

SS

Pref1

R//RL

Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output

Input Input Input Output Output Output Output

Output Output Output Input Input Output

Input Input

Port 0 is Nibble Programmable Port 0 can be conﬁgured as A15-A8 external program ROM/DATA Address Bus. Port 0 can be conﬁgured as a mouse/trackball input.

Port 1 is byte programmable Port 1 can be conﬁgured as multiplexed A7-A0/D7-D0 external program ROM Address/Data Bus.

Port 2 pins are individually conﬁgurable as input or output.

IRQ2/Modulator Input IRQ0 IRQ1 T8 output T16 output T8/T16 output

Address Strobe Data Strobe Read/Write Reset Crystal, Oscillator Clock Crystal, Oscillator Clock Power Supply Ground Comparator 1 Reference ROM/ROMless

6-6

P R E L I M I N A R Y

DS97LVO0900

1

Zilog IR Microcontroller

Z86C72/C92/L72/L92

ABSOLUTE MAXIMUM RATINGS

Symbol Description Min Max Units

V

T

STG

T

Notes:

* Voltage on all pins with respect to GND † See Ordering Information

Supply V oltage (*) -0.3 +7.0 V

CC

Storage Temp. -65 ° +150 ° Oper. Ambient

A

Temp.

C

†C

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 6).

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.

From Output

Under Test

150 pFI

CAPACITANCE

T

= 25 ° C, V

A

Parameter Max

Input capacitance 12 pF

Output capacitance 12 pF

I/O capacitance 12 pF

= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

CC

Figure 6. Test Load Diagram

DS97LVO0900

P R E L I M I N A R Y

6-7

Z86C72/C92/L72/L92 IR Microcontroller Zilog

DC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)

Preliminary

= 0 ° C to +70 ° C

Sym Parameter

Max Input Voltage 2.0V

V

CH

Clock Input High Voltage

V

CL

Clock Input Low V oltage

V

IH

IL

OH1

Input High Voltage2.0V

Input Low Voltage 2.0V

Output High Voltage

V

OH2

Output High Voltage (P36, P37,P00, P01)

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

T

A

V

CC

Min Max 25 ° C Units Conditions Notes

7 7

0.8 V

CC

0.8 V

CC

V

– 0.3

SS

V

– 0.3

SS

0.7 V

CC

0.7 V

CC

VSS – 0.3 V

– 0.3

SS

V

CC

V

CC

0.2 V

0.2 V V

CC

V

CC

0.2 V

+ 0.3

CC

+ 0.3 + 0.3

CC CC

VCC – 0.4 V

– 0.4

CC

VCC - 0.8 V

- 0.8

CC

Typ @

0.5V

CC

0.5V

CC

0.5V

CC

0.5V

CC

1.7

3.7

VVI

<250 µ A

IN

I

<250 µ A

IN

VVDriven by External

Clock Generator Driven by External Clock Generator

VVDriven by External

Clock Generator Driven by External Clock Generator

V V

VVI

= –0.5 mA

OH

I

= –0.5 mA

OH

= –7 mA

OH

I

= –7 mA

OH

6-8

P R E L I M I N A R Y

DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

T

Sym Parameter

V

OL1

Output Low Voltage

V

OL2*

Output Low Voltage

2.0V

3.9V

2.0V

3.9V

= 0°C to +70°C

A

V

CC

Min Max 25°C Units Conditions Notes

0.4

0.8

Typ @

0.1

0.2

0.5

0.3

VVIOL = 1.0 mA

I

= 4.0 mA

OL

VVIOL = 5.0 mA

I

= 7.0 mA

OL

V

OL2

V

RH

V

Rl

V

OFFSET

I

IL

I

OL

I

IR

I

CC

Output Low Voltage(P36,

2.0V

3.9V

P37,P00,P01) Reset Input

High Voltage Reset Input

Low V oltage Comparator Input

Offset V oltage

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

Input Leakage 2.0V

3.9V

Output Leakage 2.0V

3.9V

Reset Input PullUp Current

2.0V

3.9V

Supply Current 2.0V

3.9V

2.0V

3.9V

0.8 V

CC

0.8 V

CC

VSS – 0.3 V

– 0.3

SS

-1

–1 –1

0.8

V

CC

V

CC

0.2 V

0.2 V 25

25

1 1

–230 –400

10 15

250 850

CC CC

0.3

0.2

1.5

2.0

0.5

0.9 10

10

< 1 < 1

-50

–90

4

10

100 500

VVIOL = 10 mA

I

= 10 mA

OL

V V

mV mV

VIN = OV, V

µA

VIN = OV, V

µA

VIN = OV, V

µA

VIN = OV, V

µA

VIN = O

µA µA

mA mA

µA µA

VIN = O @ 8.0 MHz

@ 8.0 MHz @ 32 kHz @ 32 kHz

V V

CC CC

1,2 1,2 1,2,8

DS97LVO0900 P R E L I M I N A R Y 6-9

Z86C72/C92/L72/L92 IR Microcontroller Zilog

= 0°C to +70°C

T

Sym Parameter

I

CC1

Standby Current (WDT Off)

2.0V

A

V

CC

Min Max 25°C Units Conditions Notes

3

Typ @

1

mA

HALT Mode VIN = OV, V

CC

1,2

@

8.0 MHz

3.9V

5

4

mA

HALT Mode V

= OV, V

IN

CC

1,2

@ 8.0 MHz

2.0V

2

0.8

mA

Clock Divide-by-

1,2

16 @ 8.0 MHz

3.9V

4

2.5

mA

Clock Divide-by-

1,2

16 @ 8.0 MHz

I

CC2

Standby Current 2.0V

8

2

µA

STOP Mode VIN = OV, V

3,5

CC

WDT is not Running

3.9V

10

3

µA

STOP Mode VIN = OV, V

3,5

CC

WDT is not Running

2.0V

500

310

µA

STOP Mode VIN = OV, V

CC

WDT is not

3.9V

800

600

µA

Running STOP Mode VIN = OV, V

CC

WDT is not Running

T

V

POR

RAM

Power-On Reset 2.0V

3.9V

Static RAM Data

Vram 0.8 0.5 V 6

12

75

5

20

18

ms

7

ms

Retention V oltage

V

LV

(VBO)

Notes:

1. All outputs unloaded, inputs at rail

2. CL1 = CL2 = 100 pF

3. Same as note [4] except inputs at V

4. The VLV increases as the temperature decreases

5. Oscillator stopped

6. Oscillator stops when V

7. 32 kHz clock driver input

* All Outputs excluding P00, P01, P36, and P37

Low Voltage

V

CC

Protection

I

CC1

Crystal/Resonator External Clock Drive

falls below VLV limit

CC

Typ

3.0 mA

0.3 mA

CC

Max

5 5

2.15 1.7 V 8 MHz max Ext. CLK Freq.

Unit

mA mA

Frequency

8.0 MHz

4

6-10 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)

Preliminary

= 0°C to +70°C

Sym Parameter

Max Input Voltage

V

CH

Clock Input High V oltage

CL

Clock Input

V

Low V oltage

V

IH

Input High Voltage

IL

Input Low

V

Voltage

V

OH1

Output High Voltage

V

OH2

Output High Voltage (P36, P37)

V

OL1

Output Low Voltage

V

OL2*

Output Low Voltage

V

OL2

Output Low Voltage (P00, P01, P36,P37)

RH

Reset Input

V

High V oltage

Rl

Reset Input

V

Low V oltage

V

OFFSET

Comparator Input Offset V oltage

I

Input Leakage 4.5V

IL

Output Leakage 4.5V

OL

Reset Input

IR

Current

I

CC

Supply Current 4.5V

WDT Off 4.5V

V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

3.9 V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

T

A

Min Max 25°C Units Conditions Notes

7 7

0.9 V

CC

0.9 V

CC

VSS – 0.3

V

–0.3

SS

0.7 V

CC

0.7 V

CC

VCC + 0.3 V

+ 0.3

CC

0.2 V

CC

0.2 V

CC

VCC + 0.3 V

+ 0.3

CC

VSS – 0.3 V

– 0.3

SS

VCC – 0.4 V

– 0.4

CC

VCC – 0.8 V

– 0.8

CC

0.4

0.8

0.8 V

CC

0.8 V

CC

VSS – 0.3 V

– 0.3

SS

V V

0.2 V

CC CC

25 25

-1

1 1

-500

-800 20

30

1000 1250

Typ @

0.5Vcc

4.4

5.4

0.1

0.2

0.3

0.4

0.3

0.2

2.5

3.0

0.5

0.9 10

10

<1 <1

VVIIN 250 µA

I

250 µA

IN

V Driven by

External Clock Generator

V Driven by

External Clock Generator

V Driven by

External Clock Generator

V

VI

VVI

= –0.5 mA

OH

I

= –0.5 mA

OH

= –7 mA

OH

I

= –7 mA

OH

VVIOL = 1.0 mA

I

= 4.0 mA

OL

VVIOL = 5.0 mA

I

= 7.0 mA

OL

VIOL = 10 mA

V V

mV mV

µAµAVIN = OV, V

VIN = OV, V

µAµAVIN = OV, V

VIN = OV, V

CC CC

µA µA

mAmA@8.0 MHz

@8.0 MHz

µAµA@ 32 kHz

@ 32 kHz

1,2

1.2 1,2,8

1,2,8

DS97LVO0900 P R E L I M I N A R Y 6-11

Z86C72/C92/L72/L92 IR Microcontroller Zilog

DC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS) (Continued)

4.5V

V

CC

Sym Parameter

I

CC1

Standby Current (WDT Off)

5.5V

4.5V

5.5V

I

CC2

Standby Current 4.5V

5.5V

4.5V

5.5V

T

POR

Power-On Reset 4.5V

5.5V

V

RAM

Static RAM Data

Vram 0.8 0.5 V 6

Retention V oltage

V

LV

(VBO)

Notes:

1. All outputs unloaded, inputs at rail

2. CL1 = CL2 = 100 pF

3. Same as note [4] except inputs at V

4. The VLV increases as the temperature decreases

5. Oscillator stopped

6. Oscillator stops when V

7. 32 kHz clock driver input

* All Outputs excluding P00, P01, P36, and P37

Low Voltage

V

CC

Protection

I

CC1

Crystal/Resonator External Clock Drive

falls below VLV limit

CC

Typ

3.5 mA

0.8 mA

CC

TA = 0°C to +70°C

Typ @

Min Max 25°C Units Conditions Notes

6

2

mA

HALT Mode VIN = OV, V

CC

1,2

@

8.0 MHz

8 5

5

1.0

mA mA

HALT Mode V

= OV, V

IN

CC

1,2 1,2

@ 8.0 MHz

7

3.0

mA

Clock Divide-by-

1,2

16 @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz

8

2

µA

STOP Mode VIN = OV, V

CC

3,5

WDT is not Running

10 500 800

3 310 600

µA µA µA

STOP Mode VIN = OV, V

WDT is not

CC

3,5 3,5

Running STOP Mode VIN = OV, V

CC

WDT is Running

5.0

4.0

75 20

8.0

6.0

ms ms

2.15 1.7 V 8 MHz max

4

Ext. CLK Freq.

Max

5 5

Unit

mA mA

Frequency

8.0 MHz

6-12 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

AC CHARACTERISTICS

External I/O or Memory Read and Write Timing Diagram

R//W

Port 0, /DM

Port 1

/AS

/DS

(Read)

Port 1

12

16

18

3

13

19

20

A7 - A0 D7 - D0 IN

21

8 11

4

5

17

6

9

10

D7 - D0 OUTA7 - A0

14

7

15

/DS

(Write)

Figure 7. External I/O or Memory Read/Write Timing

DS97LVO0900 P R E L I M I N A R Y 6-13

Z86C72/C92/L72/L92 IR Microcontroller Zilog

AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)

Preliminary External I/O or Memory Read and Write Timing Table

No Symbol Parameter

1 TdA(AS) Address Valid to

/AS Rising Delay

2 TdAS(A) /AS Rising to Address

Float Delay

3 TdAS(DR) /AS Rising to Read

Data Required Valid

V

CC

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

4 TwAS /AS Low Width 2.0V

3.9V

5 Td Address Float to

/DS Falling

2.0V

3.9V

6 TwDSR /DS (Read) Low Width 2.0V

3.9V

7 TwDSW /DS (Write) Low Width 2.0V

3.9V

8 TdDSR(DR) /DS Falling to Read

Data Required Valid

9 ThDR(DS) Read Data to /DS Rising

Hold Time

10 TdDS(A) /DS Rising to Address

Active Delay

11 TdDS(AS) /DS Rising to /AS

Falling Delay

12 TdR/W(AS) R//W Valid to /AS

Rising Delay

13 TdDS(R/W) /DS Rising to

R//W Not Valid

14 TdDW(DSW) Write Data Valid to /DS

Falling (Write) Delay

15 TdDS(DW) /DS Rising to Write

Data Not Valid Delay

16 TdA(DR) Address Valid to Read

Data Required Valid

17 TdAS(DS) /AS Rising to

/DS Falling Delay

18 TdDM(AS) /DM Valid to /AS

Falling Delay

19 TdDS(DM) /DS Rise to

/DM V alid Delay

20 ThDS(A) /DS Rise to Address

Valid Hold Time

Notes:

1. When using extended memory timing add 2 TpC

2. Timing numbers given are for minimum TpC

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

Standard Test Load All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0

TA = 0°C to +70°C

8.0MHz

Min Max Units Notes

55 55

70 70

400 400

80 80

0 0

300 300

165 165

260 260

0 0

85 95

60 70

70 70

80 80

70 80

475 475

100 100

55 55

70 70

70

ns ns

ns

70

2

2 2

1,2

2

1,2

2

1,2

2

6-14 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

AC CHARACTERISTICS (Z86C72/C92 SPECIFICATIONS)

Preliminary External I/O or Memory Read and Write Timing Table

TA = 0°C to +70°C

16.0 MHz

No Symbol Parameter

1 TdA(AS) Address Valid to /AS

Rising Delay

2 TdAS(A) /AS Rising to Address

Float Delay

3 TdAS(DR) /AS Rising to Read

Data Required Valid

4 TwAS /AS Low Width 4.5V

5 Td Address Float to /DS

Falling

6 TwDSR /DS (Read) Low Width 4.5V

7 TwDSW /DS (Write) Low Width 4.5V

8 TdDSR(DR) /DS Falling to Read

Data Required Valid

9 ThDR(DS) Read Data to

/DS Rising Hold Time

10 TdDS(A) /DS Rising to Address

Active Delay

11 TdDS(AS) /DS Rising to /AS 4.5V

12 TdR/W(AS) R//W Valid to /AS

Rising Delay

13 TdDS(R/W) /DS Rising to

R//W Not Valid

14 TdDW(DSW) Write Data Valid to

/DS Falling (Write) Delay

15 TdDS(DW) /DS Rising to Write

Data Not Valid Delay

16 TdA(DR) Address Valid to Read

Data Required Valid

17 TdAS(DS) /AS Rising to /DS

Falling Delay

18 TdM(AS) /DM Valid to /AS

Falling Delay

19 TdDS(DM) /DS Rise to /DM Valid

Delay

20 ThDS(A) /DS Rise to Address

Valid Hold Time

Notes:

1. When using extended memory timing add 2 TpC.

2. Timing numbers given are for minimum TpC. Standard Test Load All timing references use 0.9 V

for a logic 1 and 0.1 VCC for a logic 0.

CC

V

CC

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

Min Max Units Notes

25 25

35 35

180 180

40 40

0 0

135 135

80 80

75 75

0 0

50 50

35 35

25 25

35 35

25 25

35 35

230 230

45 45

30 30

70 70

ns ns

2

1,2

2

1,2

2

1,2

2

DS97LVO0900 P R E L I M I N A R Y 6-15

Z86C72/C92/L72/L92 IR Microcontroller Zilog

AC CHARACTERISTICS

Additional Timing Diagram

Clock

T

IN

IRQ

Clock

Setup

3

7 7

1

2 2 3

4

5

6

N

8

9

11

Stop

Mode

Recovery

Source

10

Figure 8. Additional Timing

6-16 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)

Preliminary Additional Timing Table

No Sym Parameter

1 TpC Input Clock Period 2.0V

2 TrC,TfC Clock Input Rise

and Fall Times

3 TwC Input Clock Width 2.0V

4 TwTinL Timer Input

Low Width

5 TwTinH Timer Input

High Width

6 TpTin Timer Input

Period

7 TrTin,TfTin Timer Input Rise

and Fall Timers

8A TwIL Interrupt Request

Low Time

8B TwIL Interrupt Request

Low Time

9 TwIH Interrupt Request

Input High Time

10 Twsm Stop-Mode Recovery

Width Spec

11 T ost Oscillator

Start-Up Time

12 T wdt Watch-Dog Timer

Delay Time (5 ms) (10 ms)

(20 ms) (80 ms)

Notes:

1. Timing Reference uses 0.9 V

2. Interrupt request through Port 3 (P33-P31).

3. Interrupt request through Port 3 (P30).

4. SMR bit D5 = 0

for a logic 1 and 0.1 VCC for a logic 0.

CC

V

CC

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

TA = 0°C to +70°C

8.0MHz

Min Max Units Notes

121 121

37 37

100

70

3TpC 3TpC

8TpC 8TpC

100

70

5TpC 5TpC

12

12 5 TpC 5 TpC

12

5 25 10 50 20

225

80

DC DC

25 25

100 100

5TpC 5TpC

75 20

150

40

300

80

1200

320

ns ns

ns ns ns ns

ms ms ms ms ms ms ms ms

1 1

1,2 1,2

1,3 1,3

1,2 1,2

7 7 6 6

4 4

DS97LVO0900 P R E L I M I N A R Y 6-17

Z86C72/C92/L72/L92 IR Microcontroller Zilog

AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)

Preliminary Additional Timing Table

TA = 0°C to +70°C

16.0 MHz

No Symbol Parameter

1 TpC Input Clock Period 4.5V

2 T rC , TfC Clock Input Rise and

Fall Times

3 TwC Input Clock Width 4.5V

4 TwTinL Timer Input Low

Width

5 TwTinH Timer Input High

Width

6 TpTin Timer Input Period 4.5V

7 TrTin, TfTin Timer Input Rise 4.5V

8A TwIL Interrupt Request

Low Time

8B TwIL Int. Request Low

Time

9 TwIH Interrupt Request

Input High Time

10 Twsm Stop-Mode

Recovery Width Spec

11 Tost Oscillator Start-up

Time

12 T wdt Watch-Dog Timer

Delay Time (2.0 ms)

4.0 ms 4.5V

8.0 ms 4.5V

32 ms 4.5V

Notes:

1. Timing Reference uses 0.9 V

2. Interrupt request through Port 3 (P33-P31).

3. Interrupt request through Port 3 (P30).

4. SMR bit D5 = 0

5. Reg. WDTMR bit D0=1

6. Reg. SMR bit D5 = 0

7. Reg. SMR bit D5 = 1

8. Reg. WDTMR bit D1-0

for a logic 1 and 0.1 VCC for a logic 0.

CC

V

CC

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

Min Max Units Notes

63 63

31 31

100

70

5TpC 5TpC

8TpC 8TpC

100

70

5TpC 5TpC

12

12 5TpC 5TpC

2.0

4.0

8.0

8.0 32

32

DC DC

15 15

100 100

5TpC 5TpC

ns ns

ms ms

1 1

1,2 1,2

1,3 1,3

1,2 1,2

8 8 7 7

4 4

D0=0, 5 D1=0, 5

D0=1, 5 D1=0, 8

6-18 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

AC CHARACTERISTICS

Handshake Timing Diagrams

Data In

/DAV

(Input)

RDY

(Output)

Data Out

/DAV

(Output)

1

Data In Valid

2

3

Delayed DAV

4

Next Data In Valid

Figure 9. Port I/O with Input Handshake Timing

Data Out Valid

7

5 6

Delayed RDY

Next Data Out Valid

Delayed DAV

RDY

(Input)

8 9

10

Delayed RDY

Figure 10. Port I/O with Output Handshake Timing

11

DS97LVO0900 P R E L I M I N A R Y 6-19

Z86C72/C92/L72/L92 IR Microcontroller Zilog

AC CHARACTERISTICS (Z86L72/L92 LOW VOLTAGE SPECIFICATIONS)

Preliminary Handshake Timing Table

= 0°C to +70°C

No Sym Parameter

V

CC

1 TsDI(DAV) Data In Setup Time 2.0V

3.9V

2 ThDI(DAV) Data In Hold Time 2.0V

3.9V

3 TwDAV Data Available Width 2.0V

3.9V

4 TdDAVI(RDY) DAV Falling to RDY

Falling Delay

5 TdDAVId(RDY) DAV Rising to RDY

Falling Delay

6 TdRDYO(DAV) RDY Rising to DAV

Falling Delay

7 TdDO(DAV) Data Out to DAV

Falling Delay

8 TdDAV0(RDY) DAV Falling to RDY

Falling Delay

9 TdRDY0(DAV) RDY Falling to DAV

Rising Delay

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

10 T wRDY RDY Width 2.0V

3.9V

11 TdRDY0d(DAV) RDY Rising to DAV

Falling Delay

2.0V

3.9V

T

A

Min Max Direction

0 0

155 110

160 115

120

80

0 0

63 63

0 0

160 115

110

80

110

80

Data

IN IN

OUT OUT

6-20 P R E L I M I N A R Y DS97LVO0900

Z86C72/C92/L72/L92

1

Zilog IR Microcontroller

AC CHARACTERISTICS(Z86C72/C92 SPECIFICATIONS)

Preliminary Handshake Timing Table

No Symbol Parameter

1 TSD(DAV) Data in Setup Time 4.5V

2 ThD(DAV) Data in Hold Time 4.5V

3 TwDAV Data Available Width 4.5V

4 TdDAVI(RDY) DAV Falling to RDY

Falling Delay

5 TdDAVId(RDY) DAV Rising to RDY

Falling Delay

6 TdRDY)(DAV) RDY Rising to DAV

Falling Delay

7 TdD0(DAV) Data Out to DAV

Falling Delay

8 TdDAV0(RDY) DAV Falling to RDY

Falling Delay

9 TdRDY0(DAV) RDY Falling to DAV 4.5V

10 TwRDY RD Y Width 4.5V

11 TdRDY0d(DAV) RDY Rising to DAV

Falling Dealy

V

CC

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

4.5V

5.5V

TA = 0°C to +70°C

16.0 MHz

Min Max Data Direction

0 0

160 115

155 110

160 115

120

80

0 0

31 31

0 0

160 115

110

80

110

80

IN IN

OUT OUT

DS97LVO0900 P R E L I M I N A R Y 6-21

Z86C72/C92/L72/L92 IR Microcontroller Zilog

PIN FUNCTIONS

/DS (Output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid.

/AS (Output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 0/Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS is placed in the high-impedance state along with Ports 0 and 1, Data Strobe, and Read/Write.

XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network or an external single-phase clock to the on-chip oscillator input.

XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output.

R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory.

R//RL (input). This pin, when connected to GND, disables the internal ROM and forces the device to function as a ROMless Z8. (Note that, when left unconnected or pulled high to V

, the part functions normally as a Z8 ROM ver-

CC

sion.)

Port 0 (P07-P00). Port 0 is an 8-bit, bi-directional, CMOS compatible port. These eight I/O lines are configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The output drivers are push-pull. Port 0 is placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0. Handshake signal direction is dictated by the I/O direction to Port 0 of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble.

For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. After a hardware reset, Port 0 is configured as an input port.

Port 0 is set in the high-impedance mode (if selected as an address output) along with Port 1 and the control signals /AS, /DS, and R//W through P3M bits D4 and D3(Figure

11). A ROM mask option is available to program 0.4 V

DD

CMOS trip inputs on P00-P03 of the L72. This allows direct interface to mouse/trackball IR sensors.

An optional 200 kOhm pull-up is available as a mask option on all Port 0 bits with nibble select. These pull-ups are disabled when configured (bit by bit) as an output.

6-22 P R E L I M I N A R Y DS97LVO0900