XILINX XC1700E, XC1700EL, XC1700L User Manual

<

R

EPROM

Cell

Matrix

Address Counter

CE

DATA

OE

Output

CLK

V

CC

V

PP

GND

DS027_01_021500

TC

OE

RESET/

OE/

RESET

or

CEO

B
L

XC1700E, XC1700EL, and XC1700L

Series Configuration PROMs

DS027 (v3.4) July 9, 2007

8

Features

• One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices

• Simple interface to the FPGA; requires only one user
I/O pin

• Cascadable for storing longer or multiple bitstreams

• Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

• XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration

• Low-power CMOS floating-gate process

Description

The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.

When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the

pin. The

IN

Product Specification

• XC1700E series are available in 5V and 3.3V versions

• XC1700L series are available in 3.3V only

• Available in compact plastic packages: 8-pin SOIC,

8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC,
44-pin PLCC or 44-pin VQFP

• Programming support by leading programmer
manufacturers

• Design support using the Xilinx Alliance and
Foundation™ series software packages

• Guaranteed 20 year life data retention

• Lead-free (Pb-free) packaging available

PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.

Multiple devices can be concatenated by using the CEO
output to drive the CE

input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or
Foundation series development system compiles the FPGA
design file into a standard Hex format, which is then
transferred to most commercial PROM programmers.

© 1998-2000, 2004-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS027 (v3.4) July 9, 2007 www.xilinx.com
Product Specification 1

Figure 1: Simplified Block Diagram (Does not Show Programming Circuit)

XC1700E, XC1700EL, and XC1700L Series Configuration PROMs

R

Pin Description

DATA

Data output is in a high-impedance state when either CE or
OE

are inactive. During programming, the DATA pin is I/O.
Note that OE
active Low.

CLK

Each rising edge on the CLK input increments the internal
address counter, if both CE

RESET/OE

When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE
document describes the pin as RESET/OE
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET
driven by the FPGAs INIT

The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.

CE

When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I

can be programmed to be either active High or

and OE are active.

or OE/RESET. To avoid confusion, this

, although the

, because it can be

pin.

standby mode.

CC

V

PP

Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
operation, this pin must be connected to V

. Failure to do

CC

so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave V

floating!

PP

VCC and GND

Positive supply and ground pins.

PROM Pinouts

Pins not listed are "no connects."

"

8-pin
PDIP

(PD8/

)

PDG8

Pin Name

DATA 1 1 2 40 2

CLK 2 3 4 43 5

RESET/OE
(OE/RESET)

CE 4 10 8 15 21

GND 5 11 10 18, 41 24, 3

CEO 6 13 14 21 27

V

PP

V

CC

SOIC

(SO8/

SOG8)

VOIC

(VO8/

VOG8)

20-pin

SOIC

(SO20)

3861319

718173541

820203844

20-pin

PLCC

(PC20/

PCG20)

44-pin

VQFP

(VQ44)

44-pin

PLCC

(PC44)

Capacity

CEO

Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE
OE

inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO
CE

as long as OE is active. When OE goes inactive, CEO

stays High until the PROM is reset. Note that OE

can be

programmed to be either active High or active Low.

DS027 (v3.4) July 9, 2007 www.xilinx.com
Product Specification 2

and

follows

Devices Configuration Bits

XC1704L 4,194,304

XC1702L 2,097,152

XC1701/L 1,048,576

XC17512L 524,288

XC1736E 36,288

XC1765E/EL 65,536

XC17128E/EL 131,072

XC17256E/EL 262,144

R

Pinout Diagrams

6 5 4 3 2 14443424140

39
38
37
36
35
34
33
32
31
30
29

1819202122232425262728

7
8
9
10
11
12
13
14
15
16
17

PC44

Top View

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

RESET/OE

NCCENC

NC

GND

NC

NC

CEO

NC

NC

CLKNCGND

DATA(D0)NCVCC

NC

NC

VPP

NC

DS027_05_090602

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

VQ44

Top View

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

RESET/OE

NCCENC

NC

GND

NC

NC

CEO

NC

NC

CLKNCGND

DATA(D0)NCVCC

NC

NC

VPP

NC

DS027_07_090602

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1
2
3
4
5
6
7
8
9
10
11

4443424140393837363534

33
32
31
30
29
28
27
26
25
24
23

1213141516171819202122

DS027_08_110102

SO20

Top

View

VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

DATA(D0)

NC

CLK

NC
NC
NC
NC

OE/RESET

NC
CE

XC1700E, XC1700EL, and XC1700L Series Configuration PROMs

DATA(D0)

CLK

OE/RESET

CE

1

PD8/PDG8

2

VO8/VOG8
SO8/SOG8

3

Top View

4

8

VCC

7

VPP

6

CEO

5

GND

DS027_06_060705

DS027 (v3.4) July 9, 2007 www.xilinx.com
Product Specification 3

CLK

NC

OE/RESET

NC
CE

NC

DATA(D0)NCVCC

321
4
5

PC20/PCG20

6

Top View

7

8

910111213

NC

GND

20

NCNCNC

NC

19
18

NC

17

VPP

16

NC

15

NC

14

CEO

DS027_09_060705

R

Xilinx FPGAs and Compatible PROMs

XC1700E, XC1700EL, and XC1700L Series Configuration PROMs

Device

XC4003E 53,984 XC17128E

XC4005E 95,008 XC17128E

XC4006E 119,840 XC17128E

XC4008E 147,552 XC17256E

XC4010E 178,144 XC17256E

XC4013E 247,968 XC17256E

XC4020E 329,312 XC1701

XC4025E 422,176 XC1701

XC4002XL 61,100 XC17128EL

XC4005XL 151,960 XC17256EL

XC4010XL 283,424 XC17512L

XC4013XL/XLA 393,632 XC17512L

XC4020XL/XLA 521,880 XC17512L

XC4028XL/XLA 668,184 XC1701L

XC4028EX 668,184 XC1701

XC4036EX/XL/XLA 832,528 XC1701L

XC4036EX 832,528 XC1701

XC4044XL/XLA 1,014,928 XC1701L

XC4052XL/XLA 1,215,368 XC1702L

XC4062XL/XLA 1,433,864 XC1702L

XC4085XL/XLA 1,924,992 XC1702L

XC40110XV 2,686,136 XC1704L

XC40150XV 3,373,448 XC1704L

XC40200XV 4,551,056

XC40250XV 5,433,888

XC5202 42,416 XC1765E

XC5204 70,704 XC17128E

XC5206 106,288 XC17128E

XC5210 165,488 XC17256E

XC5215 237,744 XC17256E

XCV50 559,200 XC1701L

XCV100 781,216 XC1701L

XCV150 1,040,096 XC1701L

XCV200 1,335,840 XC1702L

XCV300 1,751,808 XC1702L

XCV400 2,546,048 XC1704L

XCV600 3,607,968 XC1704L

XCV800 4,715,616

XCV1000 6,127,744

XCV50E 630,048 XC1701L

Configuration

Bits

PROM

XC1704L +

XC17512L

XC1704L+

XC1702L

XC1704L +

XC1701L

XC1704L +

XC1702L

(1)

(1)

Device

XCV100E 863,840 XC1701L

XCV200E 1,442,016 XC1702L

XCV300E 1,875,648 XC1702L

XCV400E 2,693,440 XC1704L

XCV405E 3,340,400 XC1704L

XCV600E 3,961,632 XC1704L

XCV812E 6,519,648 2 of XC1704L

XCV1000E 6,587,520 2 of XC1704L

XCV1600E 8,308,992 2 of XC1704L

XCV2000E 10,159,648 3 of XC1704L

XCV2600E 12,922,336 4 of XC1704L

XCV3200E 16,283,712 4 of XC1704L

Notes:

1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.

Configuration

Bits

PROM

Controlling PROMs

Connecting the FPGA device with the PROM:

• The DATA output(s) of the of the PROM(s) drives the
D

input of the lead FPGA device.

IN

• The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).

• The CEO
next PROM in a daisy chain (if any).

• The RESET
the INIT
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
Other methods—such as driving RESET
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s
internal power-on-reset. This may not be a safe
assumption.

• The PROM CE
or DONE pins. Using LDC
on the D

• The CE
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC
unconditionally High during user operation. CE
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.

output of a PROM drives the CE input of the

/OE input of all PROMs is best driven by

output of the lead FPGA device. This

glitch.

CC

/OE from LDC

input can be driven from either the LDC

avoids potential contention

pin.

IN

input of the lead (or only) PROM is driven by

can be used to drive CE, but must then be

can

DS027 (v3.4) July 9, 2007 www.xilinx.com

Product Specification 4