Xilinx ChipScope PLBv46 IBA Specification
DS619 April 7, 2009 www.xilinx.com 1
Product Specification
© 2009 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
Introduction
The ChipScope™ PLB Integrated Bus Analyzer (IBA) core
is a specialized bus analyzer core designed to debug embedded systems that contain the IBM CoreConnect™ Processor
Local Bus (PLB) version 4.6. The ChipScope PLB46 IBA
core in EDK is based on a Tcl script that generates an Hardware Description Language (HDL) wrapper to the PLB IBA
and calls the ChipScope Core Generator (Coregen) to generate the netlist based on user parameters.
The ChipScope PLBv46 IBA is a soft IP core designed for
Xilinx® FPGAs and contains the following features:
• Probes the master, slave, arbiter, and error status signals
of the PLBv46 bus
• Probes the PLBv46 OR'ed slave signals
• Automatically adjusts ports to the PLBv46 bus width
• Separates master, slave, and error status signals into
independent match units which can be enabled or
disabled by a design parameter
• Allows independent enabling or disabling of probed
master, slave, and error status signals for data capture
• Supports trigger port customization by a design
parameter
• Supports match unit type customization for each trigger
port by a design parameter
• Supports sample depths from 1024-131,072 on
Virtex™-5 Devices selectable by a design parameter
• Can probe as few as 1 signals and as many as 1115
signals on a Virtex-5 device
• Provides a separate input bus to allow a user-defined
input debug port
• Supports a trigger output indicator pin that can be sent
off chip or to other cores
For more information about the PLBv46 IBA core, refer to
the ChipScope Pro Software and Cores User Guide.
ChipScope PLBv46 IBA
(Bus Analyzer) (v. 1.00a, 1.01a)
DS619 April 7, 2009 Product Specification
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Spartan®-3, Spartan-3A, Spartan-3AN,
Spartan-3A DSP, Spartan-3E,
Virtex®-4, Virtex-4 FX, Virtex-4 LX,
Virtex-4 SX, Virtex-5 LX,
Virtex-5 LXT, Virtex-5 SXT
Version of Core chipscope_plb46_iba v1.00a
Resources Used
Min Max
Slices N/A N/A
LUTs N/A N/A
FFs N/A N/A
Block RAMs N/A N/A
Provided with Core
Documentation Product Specification
Design File Formats VHDL/EDIF
Constraints File N/A
Verification N/A
Instantiation Template N/A
Reference Designs None
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.1 or later
Verification ChipScope Pro 11.1 or later
Simulation Not Supported in Simulation
Synthesis XST
Support
Provided by Xilinx, Inc.
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Product Specification
ChipScope PLB46 IBA I/O Signals
Table 1: IBA_PLBv46 Pin Descriptions
Port MU Signal Name Interface I/O Description
P1 CONTROL ICON I/O Icon control bus IO
P2 PLB_Clk System I System Clock
P3 MU_1C iba_trigin_in GENERIC I Generic Trigger Inputs
P4 iba_trig_out GENERIC O IBA Trigger Output
Reset & Error Status
P5 MU_1A PLB_Rst System I Registered reset output from arbitration
logic
P6 MU_1A Bus_Error_Det System I Bus Error Interrupt
P7 MU_1A PLB_lockErr Slave I PLB lock error indicator
P8 MU_1B PLB_MRdErr[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master slave read error indicator
P9 MU_1B PLB_MWrErr[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master slave write error indicator
P10 MU_1B PLB_MIRQ[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master interrupt request. For each master,
indicates when a slave has encountered an
event that is significant to the master
P11 MU_1B PLB_MTimeout[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB address-phase timeout indicator
Common Signals
P12 MU_2A PLB_PAValid Slave I PLB primary address valid indicator
P13 MU_2A PLB_SAValid Slave I PLB secondary address
P14 MU_2A PLB_busLock Slave I PLB BusLock
P15 MU_2A PLB_abort Slave I PLB abort bus request indicator
P16 MU_2A PLB_Swait Simulation I Output of Sl_wait OR gate
P17 MU_2A PLB_SaddrAck Simulation I Output of Sl_addrAck OR gate
P18 MU_2A PLB_Srearbitrate Simulation I Output of Sl_rearbitrate OR gate
P19 MU_2A PLB_RNW Slave I PLB read not write
P20 MU_2A PLB_SwrDAck Simulation I Output of Sl_wrDAck OR gate
P21 MU_2A PLB_SwrComp Simulation I Output of Sl_wrComp OR gate
P22 MU_2A PLB_SwrBTerm Simulation I Output of Sl_wrBTerm OR gate
P23 MU_2A PLB_wrBurst Slave I PLB burst write transfer indicator
P24 MU_2A PLB_SrdDAck Simulation I Output of Sl_rdDAck OR gate
P25 MU_2A PLB_SrdComp Simulation I Output of Sl_rdComp OR gate
P26 MU_2A PLB_SrdBTerm Simulation I Output of Sl_rdBTerm OR gate
P27 MU_2A PLB_rdBurst Slave I PLB burst read transfer indicator
P28 MU_2B PLB_size[0:3] Slave I PLB Transfer size
P29 MU_2B PLB_type[0:2] Slave I PLB Transfer type
P30 MU_2B PLB_MSize[0:1] Slave I PLB data bus port width indicator.
P31 MU_2B PLB_Ssize[0:1] Simulation I Output of slave Sl_SSize OR gate
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Product Specification
P32 MU_2B PLB_masterID[0:
C_PLBV46_MID_WIDTH-1]
Slave I PLB current master identifier
P33 MU_2B PLB_BE[0:
C_PLBV46_DWIDTH/8-1]
Slave I PLB byte enables
P34 MU_2C PLB_TAttribute[0:15] Slave I PLB Transfer Attribute
Address
P35 MU_3A PLB_ABus[0:31] Slave I PLB address bus, lower 32 bits
P36 MU_3B PLB_UABus[0:31] Slave I PLB address bus, upper 32 bits
Data
P37 MU_4 PLB_wrDBus[0:
C_PLBV46_DWIDTH-1]
Slave I PLB write data bus
P38 MU_5 PLB_SrdDBus[0:
C_PLBV46_DWIDTH-1]
Sim I Output of SL_rdDBus OR gate
Slave
P39 MU_6A PLB_rdPrim[0:
C_PLBV46_NUM_SLAVES-1]
Slave I PLB secondary to primary read request
indicator
P40 MU_6A PLB_wrPrim[0:
C_PLBV46_NUM_SLAVES-1]
Slave I PLB secondary to primary write request
indicator
P41 MU_6A Sl_AddrAck[0:
C_PLBV46_NUM_SLAVES-1]
Slave I Slave Address acknowledge
P42 MU_6A Sl_Rearbitrate[0:
C_PLBV46_NUM_SLAVES-1]
Slave I Slave bus re-arbitrate indicator
P43 MU_6A Sl_wait[0:
C_PLBV46_NUM_SLAVES-1]
Slave I Slave wait indicator
P44 MU_6A Sl_rdBTerm[0:
C_PLBV46_NUM_SLAVES -1]
Slave I Slave terminate read burst indicator
P45 MU_6A Sl_rdComp[0:
C_PLBV46_NUM_SLAVES -1]
Slave I Slave read transfer complete indicator
P46 MU_6A Sl_rdDAck[0:
C_PLBV46_NUM_SLAVES-1]
Slave I Slave read data acknowledge
P47 MU_6A Sl_wrBTerm[0:
C_PLBV46_NUM_SLAVES -1]
Slave I Slave terminate write burst indicator
P48 MU_6A Sl_wrComp[0:
C_PLBV46_NUM_SLAVES -1]
Slave I Slave write transfer complete indicator
P49 MU_6A Sl_wrDAck[0:
C_PLBV46_NUM_SLAVES-1]
Slave I Slave write data acknowledge
P50 MU_6B Sl_rdWdAddr[0:
C_PLBV46_NUM_SLAVES*4-1]
Slave I Slave read word address
P51 MU_6B Sl_SSize[0:
C_PLBV46_NUM_SLAVES*2-1]
Slave I Slave data bus port size indicator
P52 MU_7 Sl_MBusy[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave I Slave busy indicator
P53 MU_8 Sl_MRdErr[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave I Slave read error indicator
Table 1: IBA_PLBv46 Pin Descriptions (Cont’d)
Port MU Signal Name Interface I/O Description
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Product Specification
P54 MU_9 Sl_MWrErr[0:
C_PLBV46_NUM_SLAVES
*C_PLBV46_NUM_MASTERS-1]
Slave I Slave write error indicator
PLB Arbitration Signals
P55 MU_10 M_request[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master bus request
P56 MU_10 M_priority[0:
C_PLBV46_NUM_MASTERS*2-1]
Master I Master bus request priority
P57 MU_10 M_busLock[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master Bus Lock
P58 MU_10 M_abort[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master abort bus request indicator
P59 MU_10 PLB_rdPendPri[0:1] Master I PLB pending read request priority
P60 MU_10 PLB_wrPendPri[0:1] Master I PLB pending write request priority
P61 MU_10 PLB_rdPendReq Master /
Slave
I PLB pending bus read request indicator
P62 MU_10 PLB_wrPendReq Master /
Slave
I PLB pending bus write request indicator
P63 MU_10 PLB_reqPri[0:1] Master /
Slave
I PLB current request priority
PLB Master Signals
P64 MU_11 M_lockErr[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master lock error indicator
P65 MU_11 M_rdBurst[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master read burst indicator
P66 MU_11 M_wrBurst[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master write burst indicator
P67 MU_11 M_RNW[0:
C_PLBV46_NUM_MASTERS-1]
Master I Master read not write
P68 MU_11 PLB_MBusy[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master slave busy indicator
P69 MU_11 PLB_MAddrAck[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master Address acknowledge
P70 MU_11 PLB_MRdBTerm[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master terminate read burst indicator
P71 MU_11 PLB_MRdDAck[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master read data acknowledge
P72 MU_11 PLB_MRearbitrate[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master bus re-arbitrate indicator
P73 MU_11 PLB_MWrBTerm[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master terminate write burst
indicator
P74 MU_11 PLB_MWrDAck[0:
C_PLBV46_NUM_MASTERS-1]
Master I PLB Master write data acknowledge
P75 MU_12 M_mSize[0:
C_PLBV46_NUM_MASTERS*2-1]
Master I Master data bus port width
Table 1: IBA_PLBv46 Pin Descriptions (Cont’d)
Port MU Signal Name Interface I/O Description
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