CAN FD v2.0
LogiCORE IP Product Guide
Vivado Design Suite
PG223 December 5, 2018
Table of Contents
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IP Facts
Chapter 1: Overview
Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3: Designing with the Core
Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CAN FD v2.0 2
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Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 6: Test Bench
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Appendix A: Verification, Compliance, and Interoperability
Compliance Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix B: Upgrading
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CAN FD v2.0 3
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IP Facts
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Introduction
The Xilinx® LogiCORE™ IP CAN with Flexible
Data Rate (CAN FD) core is ideally suited for
automotive and industrial applications such as
automotive body control units, automotive test
equipment, instrument clusters, sensor
controls, and industrial networks. The core can
be used in standalone mode or connected to
Xilinx MicroBlaze™ processors or the Arm
Cortex-A9 processors in Zynq
®
-7000 SoCs.
®
Features
• Designed to ISO 11898-1/2015
specification [Ref 1]
• Supports both CAN and CAN FD frames
• Supports the CAN FD frame format
specified in the ISO 11898:2015
specification [Ref 1]
• Supports up to 64 byte CAN FD frames
• Supports flexible data rates up to 8 Mb/s
• Supports nominal data rates up to 1Mb/s
• Up to three data bit transmitter delay
compensation
• TX and RX mailbox buffers with
configurable depth
• Two 64-deep RX FIFOs with 32 ID
Filter-Mask pairs
• Message with lowest ID transmitted first
• Supports TX message cancellation
IMPORTANT: It is required to have a valid Bosch CAN
FD protocol license before selling a device containing
the Xilinx CAN FD IP core.
LogiCORE™ IP Facts Table
Core Specifics
UltraScale+™
Supported
Device Family
Supported User
Interfaces
Resources Performance and Resource Utilization web page
(1)
Zynq UltraScale+ MPSoC Architecture
Zynq
®
UltraScale™
-7000 SoC, 7 Series,
AXI4-Lite, APB
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File XDC
Simulation
Model
Supported
S/W Driver
(2)
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation
Synthesis Vivado Synthesis
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Not Provided
Standalone and Linux
(3)
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog
.
2. Standalone driver details can be found in the SDK directory
(\Xilinx\SDK\<release_version>\data\embeddedsw\XilinxPro
cessorIPLib\drivers\canfd_version). Linux OS and driver
support information is available from the Linux CAN FD
Driver Page.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
• Separate error logging for fast data rate
CAN FD v2.0 4
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Other Features
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• Timestamp for transmitted and received messages
• Supports transmit event FIFO
• Supports the following modes:
Disable Auto-Retransmission (DAR) mode
°
Snoop (Bus Monitoring) mode
°
Sleep mode with Wake-Up Interrupt
°
Internal Loopback mode
°
Bus-Off Recovery mode
°
-Auto-Recovery
- User intervention for Auto-Recovery
Disable Protocol Exception Event mode
°
IP Facts
CAN FD v2.0 5
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Overview
CAN FD Core
Host
Control
Object Layer/LLC
AXI4-Lite
I/F
TX Block
RAM
TBMM
Register Module
RX Block
RAM
RBMM
CDC
Sync
AXI Clock Domain
CAN FD Protocol Engine
Transfer Layer/MAC
CAN Clock Domain
PHY
CAN Bus
TX
RX
AXI4-Lite Bus
X14811-081418
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This product guide describes features of the CAN FD core and the functionality of the
various registers in the design. In addition, the core interface and its customization options
are defined in this document. Information on the CAN or CAN FD protocol is outside the
scope of this document, and knowledge of the relevant CAN and CAN FD specifications is
assumed. Figure 1-1 illustrates the high-level architecture of the CAN FD core and provides
the interface connectivity.
X-Ref Target - Figure 1-1
Chapter 1
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Note:
Figure 1-1: CAN FD Core Layered Architecture and Connectivity
The core requires an external PHY to be connected to communicate on the CAN bus.
Chapter 1: Overview
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Core Description
The core functions are divided into two independent layers as shown in Figure 1-1. The
object layer interfaces with the host control through the AXI4-Lite/APB interface and works
in the AXI4-Lite/APB clock domain. The transfer layer interfaces with the external PHY and
operates in the CAN clock domain. Information exchange between the two layers is done
through the CDC synchronizers. The CAN FD object layer provides a state-of-the-art
transmission and reception method to manage message buffers.
Object Layer (Logical Link Layer)
The object layer is divided into the following submodules:
• Register Module – This module allows for read and write access to the registers
through the external host interface.
• TX Buffer Management Module – The TX Buffer Management Module (TBMM)
interfaces with the CAN FD protocol engine to provide the next buffer to transmit on
the CAN bus. It manages the host access to the TX block RAM.
• RX Buffer Management Module – The RX Buffer Management Module (RBMM)
interfaces with the CAN FD protocol engine to provide storage for message reception
from the CAN bus. It manages the host access to the RX block RAM.
Transfer Layer (Medium Access Control Layer)
The transfer layer provides the following main functions:
• Initiation of the transmission process after recognizing bus idle (compliance with
inter-frame space)
Serialization of the frame
°
Bit stuffing
°
Arbitration and passing into receive mode in case of loss of arbitration
°
ACK check
°
Presentation of a serial bitstream to PHY for transmission
°
CRC sequence calculation including stuff bit count for FD frames
°
Bit rate switching
°
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• Reception of a serial bitstream from the PHY
Deserialization and recompiling of the frame structure
°
Bit destuffing
°
Chapter 1: Overview
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Transmission of ACK
°
Bit rate switching
°
• Bit timing functions
• Error detection and signaling
• Recognition of an overload condition and reaction
Licensing and Ordering
IMPORTANT: It is required to have a valid Bosch CAN FD protocol license before selling a device
containing the Xilinx CAN FD IP core.
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• Vivado synthesis
• Vivado implementation
• write_bitstream (Tcl command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
License Type
The core is provided under the terms of the CAN FD LogiCORE™ IP License Agreement for
Automotive or Non-Automotive applications. Click here for more information about
obtaining a CAN FD license.
For more information, visit the CAN FD product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
CAN FD v2.0 8
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Product Specification
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Standards
The CAN FD core conforms to the ISO-11898-1/2015 standard specification [Ref 1].
Performance
For full details about performance, visit the Performance and Resource Utilization web
page.
Chapter 2
Resource Utilization
For full details about resource utilization, visit the Performance and Resource Utilization
web page.
Port Descriptions
The host interface of the CAN FD core is either the AXI4-Lite or the APB interface,
depending on the parameter selected in the Vivado™ IDE. Ta bl e 2-1 defines the core
interface signaling.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
AXI4-Lite Interface Signals
(1)
s_axi_*
ip2bus_intrevent Interrupt O 0x0 Active-High interrupt line.
S_AXI_LITE – –
Clock, Interrupt, and PHY Signals
See the Vivado AXI Reference Guide (UG1037)
[Ref 7] for the description of the AXI4 signals.
(2)(3)
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Chapter 2: Product Specification
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Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
can_clk Clock
can_phy_tx PHY O 1 CAN bus transmit signal to PHY.
can_phy_rx PHY I – CAN bus receive signal from PHY.
can_clk_x2 Clock I - This is fully synchronous to the CAN clock and is
I–
CAN clock input. Oscillator frequency tolerance
according to the standard specification.
a multiple by 2 in frequency.
APB Interface Signals
apb_clk Clock I - APB clock.
apb_resetn Reset I - Active-Low synchronous reset.
apb_pwdata[31:0] APB I - Write data bus.
apb_paddr[14:0] I - Address bus.
apb_pwrite I - Read or Write signaling:
• 0 for Read Transaction.
• 1 for Write Transaction.
apb_psel I - Active-High select.
apb_penable I - Active-High enable.
apb_prdata[31:0] O 0x0 Read Data bus.
apb_pready O 0x0 Active-High ready signal.
apb_perror APB O 0x0 Active-High R/W er ro r s ignal. Re served fo r f ut ure
use.
Notes:
1. The core does not support the wstrb signal on the AXI4-Lite interface.
2. The interrupt line is level-sensitive. Interrupts are indicated by the transition of the interrupt line logic from 0 to 1.
3. The AXI4-Lite interface signals and ip2bus_intrevent are synchronous to the s_axi_aclk clock.
Register Space
The CAN FD core requires a 32 KB memory mapped space to be allocated in the system
memory. Division of this addressable space within the core is shown in Tab le 2 -2.
Note:
and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For write access, both the AXI
Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted
together.
The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal,
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Chapter 2: Product Specification
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Table 2-2: CAN FD Address Space Division
Start Address End Address Section Notes
0x0000 0x00FF Core Registers Space
0x0100 0x1FFF TX Message Space
0x2000 0x7FFF RX Message Space
This space is implemented with flip-flops. See
Tabl e 2- 3 and Ta ble 2 -4.
This space is implemented with TX block RAM
and provides storage for a maximum 32 TX
buffers. For RX Sequential buffer mode (FIFO
mode), it also
provides storage for 32 ID Filter-Mask pairs. See
Tabl e 2- 30 .
This space is implemented with RX block RAM.
For RX Sequential buffer mode (FIFO mode), it
provides storage for two 64-deep message RX
FIFO's. See Table 2- 37 and Table 2 -38.
It provides storage for 32 deep TX Event FIFO.
See Tabl e 2- 34 .
For RX Ma il box buff er mo de, it provides storage
for maximum 48 RX Buffers and respective ID
Masks. See Ta bl e 2 -44.
Table 2-3: CAN FD Core Register Address Map
Start
Address
0x0000 SRR Read, Write Software Reset Register
Name Access Description Notes
0x0004 MSR Read, Write Mode Select Register
0x0008 BRPR Read, Write
0x000C BTR Read, Write Arbitration Phase Bit Register
0x0010 ECR Read Error Counter Register
0x0014 ESR
0x0018 SR Read Status Register
0x001C ISR Read Interrupt Status Register
0x0020 IER Read, Write Interrupt Enable Register
0x0024 ICR Write Interrupt Clear Register
0x0028 TSR Read, Write Timestamp Register
0x002C0x0084
0x0088 DP_BRPR Read, Write Data Phase Baud Rate Prescaler Register
0x008C DP_BTR Read, Write Data Phase Bit Timing Register
0x0090 TRR Read, Write TX Buffer Ready Request Register
0x0094 IETRS Read, Write
Reserved –
Read, Write
1 to clear
Arbitration Phase Baud Rate Prescaler
Register
Error Status Register
Reserved space. Write has no effect. Read
always returns 0.
Interrupt Enable TX Buffer Ready Request
Served/Cleared Register
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
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Table 2-3: CAN FD Core Register Address Map (Cont’d)
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Chapter 2: Product Specification
Start
Address
Name Access Description Notes
0x0098 TCR Read, Write TX Buffer Cancel Request Register
0x009C IETCS Read, Write
Interrupt Enable TX Buffer Cancellation
Request Served/Cleared Register
0x00A0 TxE_FSR Read, Write TX Event FIFO Status Register.
0x00A4 TxE_WMR Read, Write TX Event FIFO Watermark Register.
0x00A80x00AC
Reserved –
Reserved space. Write has no effect. Read
always returns 0.
0x00B0 RCS0 Read, Write RX Buffer Control Status Register 0
0x00B4 RCS1 Read, Write
See RX Buffer Control Status Register 0
0x00B8 RCS2 Read, Write
0x00BC Reserved –
Reserved space. Write has no effect. Read
always returns 0.
0x00C0 IERBF0 Read, Write Interrupt Enable RX Buffer Full Register 0
0x00C4 IEBRF1 Read, Write Interrupt Enable RX Buffer Full Register 1
0x00C80x00DC
Reserved –
Reserved space. Write has no effect. Read
always returns 0.
0x00E0 AFR Read, Write Acceptance Filter (Control) Register
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
Registers present
only in RX Mailbox
buffer mode.
Otherwise reserved.
0x00E4 Reserved –
0x00E8 FSR Read, Write RX FIFO Status Register
0x00EC WMR Read, Write RX FIFO Watermark Register
0x00F00x00FF
Reserved –
Core Register Descriptions
Tab le 2 -4 shows the CAN FD core register space. The thick ruling represents the RX Mailbox
specific register bits and the gray represents the RX FIFO specific register bits. Register bits
tha t are us ed in both RX Ma ilbox a nd RX FI FO mode and dif fer in d escription a re show n with
a / separator.
Table 2-4: CAN FD Core Register Space
Start
Address
0x0000
313029282726252423222120191817161514131211109876543210
RSVD
Reserved space. Write has no effect. Read
always returns 0.
Reserved space. Write has no effect. Read
always returns 0.
Registers present
only in RX
Sequential/FIFO
buffer mode
otherwise reserved.
Name
(Reset
Val ue)
SRR (0x0)
CEN
SRST
0x0004
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RSVD RSVD
MSR (0x0)
ABR
SBR
DPEE
DAR
BRSD
SNOOP
LBACK
SLEEP
Table 2-4: CAN FD Core Register Space (Cont’d)
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Start
Address
0x0008
313029282726252423222120191817161514131211109876543210
RSVD BRP [7:0]
Chapter 2: Product Specification
Name
(Reset
Val ue)
BRPR
(0x0)
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
RSVD SJW[6:0]
RSVD REC[7:0] TEC[7:0] ECR (0x0)
RSVD
RSVD TDCV[6:0] RSVD
RXBOFLW_I [5:0] RXLRM_BI [5:0]
TXEWMFLL
TXEOFLW
RSVD
RXMNF
TS2[6:0] TS1[7:0] BTR (0x0)
RSVD
F_BERR
F_STER
F_FMER
F_CRCER
RSVD
SNOOP
RSVD
BSFR_CONFIG
PEE_CONFIG
ESTAT [1:0]
RXBOFLW/RXFWMFLL_1
RXBFL/RXFOFLW_1
TXCRS
TXRRS
RXFWMFLL
WKUP
SLP
BSOFF
ERROR
RSVD
ERRWRN
RXFOFLW
ACKER
BERR
STER
FMER
BBSY
BIDLE
NORMAL
SLEEP
LBACK
TSCNT_OFLW
RXOK
BSFRD
PEE
TXOK
ESR (0x0)
CRCER
SR (0x1)
CONFIG
ISR (0x0)
ARBLST
IER (0x0)
0x0024
0x0028
0x002C
0x0084
0x0088
0x008C
0x0090
ETXEWMFLL
ETXEOFLW
RSVD
CTXEWMFLL
CTXEOFLW
TIMESTAMP_CNT[15:0] RSVD
RSVD Reserved
RSVD
RR21
DP_SJW
[3:0]
RR20
RSVD
RR31
RR30
RR29
RR28
RR27
RR26
RR25
RR24
RR23
RR22
RR19
RR18
ERXMNF
CRXMNF
TDC_EN
RR17
ERXBOFLW/ERXFWMFLL_1
CRXBOFLW/CRXFWMFLL_1
RSVD
RR16
ERXBFL/ERXFOFLW_1
ETXCRS
ETXRRS
ERXFWMFLL
EWKUP
ESLP
EBSOFF
CRXBFL/CRXFOFLW_1
CTXCRS
CTXRRS
CRXFWMFLL
CWKUP
CSLP
CBSOFF
TDCOFF [5:0] DP_BRP [7:0]
RSVD
DP_TS2
[3:0]
RR15
RR14
RR13
RR12
RR11
RR10
RR9
EERROR
RSVD
ERXOFLW
ETSCNT_OFLW
ERXOK
CERROR
RSVD
CRXOFLW
CTSCNT_OFLW
CRXOK
RSVD DP_TS1[4:0]
RR8
RR7
RR6
RR5
RR4
EBSFRD
CBSFRD
RR3
EPEE
CPEE
RR2
ETXOK
CTXOK
RR1
EARBLST
ICR (0x0)
CARBLST
TSR (0x0)
CTS
DP_BRPR
(0x0)
DP_BTR
(0x0)
TRR (0x0)
RR0
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Table 2-4: CAN FD Core Register Space (Cont’d)
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Start
Address
313029282726252423222120191817161514131211109876543210
Chapter 2: Product Specification
Name
(Reset
Val ue)
0x0094
0x0098
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
0x00B4
0x00B8
0x00BC
IETRS
ERRS31
ERRS30
ERRS29
ERRS28
ERRS27
ERRS26
ERRS25
ERRS24
ERRS23
ERRS22
ERRS21
ERRS20
ERRS19
ERRS18
ERRS17
ERRS16
ERRS15
ERRS14
ERRS13
ERRS12
ERRS11
ERRS10
ERRS9
ERRS8
ERRS7
ERRS6
ERRS5
ERRS4
ERRS3
ERRS2
CR31
CR30
CR29
CR28
CR27
CR26
CR25
CR24
CR23
CR22
CR21
CR20
CR19
CR18
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
ECRS31
ECRS30
ECRS29
ECRS28
ECRS27
ECRS26
ECRS25
ECRS24
ECRS23
ECRS22
ECRS21
ECRS20
ECRS19
ECRS18
ECRS17
ECRS16
ECRS15
ECRS14
ECRS13
ECRS12
ECRS11
ECRS10
ECRS9
ECRS8
ECRS7
ECRS6
ECRS5
ECRS4
ECRS3
ECRS2
RSVD TXE_FL[5:0]
RSVD TXE_FWM[4:0]
RSVD Reserved
RSVD Reserved
CSB15
CSB14
CSB13
CSB12
CSB11
CSB10
CSB9
CSB8
CSB7
CSB6
CSB5
CSB4
CSB3
CSB2
CSB1
CSB0
HCB15
HCB14
HCB13
HCB12
HCB11
HCB10
CSB31
CSB30
CSB29
CSB28
CSB27
CSB26
CSB25
CSB24
CSB23
CSB22
CSB21
CSB20
CSB19
CSB18
CSB17
CSB16
HCB31
HCB30
HCB29
HCB28
HCB27
HCB26
CSB47
CSB46
CSB45
CSB44
CSB43
CSB42
CSB41
CSB40
CSB39
CSB38
CSB37
CSB36
CSB35
CSB34
CSB33
CSB32
HCB47
HCB46
HCB45
HCB44
HCB43
HCB42
RSVD Reserved
HCB9
HCB8
HCB25
HCB24
HCB41
HCB40
TXE_IRI
HCB7
HCB23
HCB39
RSVD
HCB6
HCB5
HCB22
HCB21
HCB38
HCB37
TXE_RI[4:0]
HCB4
HCB3
HCB20
HCB19
HCB36
HCB35
HCB2
HCB18
HCB34
ERRS1
ERRS0
CR1
CR0
ECRS1
ECRS0
HCB1
HCB0
HCB17
HCB16
HCB33
HCB32
(0x0)
TCR (0x 0)
IETCS
(0x0)
TxE _F SR
(0x0)
TxE _W MR
(0xF)
RCS0
(0x0)
RCS1
(0x0)
RCS2
(0x0)
0x00C0
0x00C4
0x00C8
0x00CC
0x00D0
0x00D4
0x00D8
0x00DC
0x00E0
0x00E4
0x00E8
0x00EC
0x00F0
0x00F4
IERBF
ERBF31
ERBF30
ERBF29
ERBF28
ERBF27
ERBF26
ERBF25
ERBF24
ERBF23
ERBF22
ERBF21
ERBF20
ERBF19
ERBF18
ERBF17
ERBF16
ERBF15
ERBF14
ERBF13
ERBF12
ERBF11
ERBF10
ERBF9
ERBF8
ERBF7
ERBF6
ERBF5
ERBF4
ERBF3
ERBF2
RSVD
ERBF47
ERBF46
ERBF45
ERBF44
ERBF43
ERBF42
ERBF41
ERBF40
ERBF39
ERBF38
ERBF37
ERBF36
ERBF35
ERBF34
RSVD Reserved
RSVD Reserved
RSVD Reserved
RSVD Reserved
RSVD Reserved
RSVD Reserved
UAF31
UAF30
UAF29
UAF28
UAF27
UAF26
UAF25
UAF24
UAF23
UAF22
UAF21
UAF20
UAF19
UAF18
UAF17
UAF16
UAF15
UAF14
UAF13
UAF12
UAF11
UAF10
UAF9
UAF8
UAF7
UAF6
UAF5
UAF4
UAF3
UAF2
RSVD Reserved
(1)
FL_1[6:0]
RSVD
RSVD RXFP[4:0]
RSVD Reserved
RSVD Reserved
(1)
IRI_1
RSVD
RI_1[5:0]
(1)
FL[6:0]
RSVD
RSVD
RXFWM_1[5:0]
RI[5:0] FSR (0x0)
IRI
RSVD
RXFWM[5:0]
RSVD
ERBF1
ERBF33
UAF1
(0x0)
ERBF0
IERBF
(0x0)
ERBF32
AFR (0x0)
UAF0
WMR
(0xF)
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Chapter 2: Product Specification
Send Feedback
Table 2-4: CAN FD Core Register Space (Cont’d)
Start
Address
0x00F8
0x00FC
Notes:
1. These fields are only available when the IP is configured in FIFO (Sequential) Mode and RX FIFO-1 is enabled.
313029282726252423222120191817161514131211109876543210
RSVD Reserved
RSVD Reserved
Software Reset Register (Address Offset + 0x0000)
Writing to the Software Reset register (SRR) places the core in Configuration mode. In
Configuration mode, the core drives recessive on the bus line and does not transmit or
receive messages. During power-up, the CEN and SRST bits are 0 and the CONFIG bit in the
Status register (SR) is 1. The Transfer Layer Configuration registers can be changed only
when the CEN bit in the SRR is 0. Mode Select register bits (except SLEEP and SBR) can be
changed only when the CEN bit is 0. If the CEN bit is changed during core operation, Xilinx
recommends resetting the core so that operation starts over.
Name
(Reset
Val ue)
Table 2-5: Software Reset Register
Bits Name Access
31:2 Reserved – 0 Reserved.
1CENR/W0
0SRSTWO0
Default
Value
CAN Enable.
This is the Enable bit for the core.
• 1 = The core is in Loopback, Sleep, Snoop, or Normal mode,
depending on the LBACK, SLEEP, and SNOOP bits in the MSR.
• 0 = The core is in Configuration mode.
Note:
If the CEN bit is cleared during core operation, Xilinx recommends
resetting the core so that operation starts over.
Reset.
This is the software reset bit for the core.
• 1 = Core is reset.
If a 1 is written to this bit, all core configuration registers
(including the SRR) are reset. Reads to this bit always return 0.
After performing a soft or hard reset, wait for 16 AXI4-Lite/APB
Note:
clock cycles before initiating next AXI4-Lite/APB transaction.
Mode Select Register (Address Offset + 0x0004)
Description
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Writing to the Mode Select register (MSR) enables the core to enter Snoop, Sleep,
Loopback, or Normal modes. In Normal mode, the core participates in normal bus
communication. If the SLEEP bit is set to 1, the core enters Sleep mode. If the LBACK bit is
set to 1, the core enters Loopback mode. If the SNOOP mode is set to 1, the core enters
Snoop mode and does not participate in bus communication but only receives messages.
Chapter 2: Product Specification
Send Feedback
IMPORTANT: LBACK, SLEEP, and SNOOP bits should never be set to 1 at the same time. At any given
point, the core can either be in Loopback, Sleep, or Snoop mode. When all three bits are set to 0, the
core can enter Normal mode subject to other conditions.
Table 2-6: Mode Select Register
Bits Name Access
31:16 Reserved – 0 Reserved.
15:8 Reserved – 0 Reserved.
7ABRR/W0
6SBRR/W0
5DPEER/W 0
Default
Value
Auto Bus-Off Recovery Request.
• 1 = Auto Bus-Off Recovery request.
• 0 = No such request.
If this bit is set, the node does auto Bus-Off Recovery
irrespective of the SBR bit setting in this register. This bit can be
written only when the CEN bit in SRR is 0.
Start Bus-Off Recovery Request.
• 1 = Start Bus-Off Recovery request.
• 0 = No such request.
Node stays i n Bus-Of f state until th e SBR bi t is set to 1 (pro viding
that the ABR bit in this register is not set).
This bit can be written only when node is in Bus-Off state.
This bit auto clears after node completes the Bus-Off Recovery
or leaves Bus-Off state due to hard/soft reset or CEN
deassertion.
Disable Protocol Exception Event Detection/Generation.
• 1 = Disable Protocol Exception Event detection/generation by
CAN FD receiver if “res” bit in CAN FD frame is detected as 1.
In this case, CAN FD receiver generates Form error.
• 0 = PEE detection/generation is enabled. If the CAN FD
receiver detects th e res bit as 1, it go es to Bus In teg rat ion state
(PEE_config) and waits for Bus Idle condition (11 consecutive
nominal recessive bits). The error counter remains unchanged.
This bit can be written only when the CEN bit in SRR is 0.
Description
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Disable Auto-Retransmission.
• 1 = Disable auto retransmission on the CAN bus to provide
4DARR/W0
• 0 = Auto retransmission enabled.
This bit can be written only when the CEN bit in SRR is 0.
CAN FD Bit Rate Switch Disable Override.
• 1 = Makes the core transmit CAN FD frames only in nominal
3BRSDR/W 0
• 0 = Makes the core transmit CAN FD frames as per BRS bit in
This bit can be written only when the CEN bit in SRR is 0.
single shot transmission.
bit rate (by overriding the TX Message element BRS bit
setting).
the TX Message element.
Table 2-6: Mode Select Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name Access
2 SNOOP R/W 0
1LBACKR/W 0
Default
Value
Description
SNOOP Mode Select/Request.
This is the Snoop mode request bit.
• 1 = Request core to be in Snoop mode.
• 0 = No such request.
This bit can be written only when CEN bit in SRR is 0.
Make sure that Snoop mode is programmed only after system
reset or software reset. For the core to enter Snoop mode, LBACK
and SLEEP bits in this register should be set to 0. The features of
Snoop mode are as follows:
• The core transmits recessive bits onto the CAN bus.
• The core receives messages that are transmitted by other
node s but do es not AC K. St o res re ceived message s in RX b lock
RAM based on programmed ID filtering.
• Error counters are disabled and cleared to 0. Reads to the error
counter register return zero.
Loopback Mode Select/Request.
This is the Loopback mode request bit.
• 1 = Request core to be in Loopback mode.
• 0 = No such request.
This bit can be written only when the CEN bit in SRR is 0. For the
core to enter Loopback mode, SLEEP and SNOOP bits in this
register should be set to 0.
Sleep Mode Select/Request.
This is the Sleep mode request bit.
• 1 = Request core to be in Sleep mode.
0SLEEPR/W 0
• 0 = No such request.
Th is bit is cleare d when the core wakes up fr om Sleep m ode. Fo r
the core to enter Sleep mode, LBACK and SNOOP bits in this
register should be set to 0.
Arbitration Phase (Nominal) Baud Rate Prescaler Register (Address Offset + 0x0008)
The CAN clock for the core is divided by (programmed prescaler value + 1) to generate the
quantum clock needed for sampling and synchronization.
Table 2-7: Arbitration Phase Baud Rate Prescaler Register
Bits Name Access
31:8 Reserved – 0 Reserved.
7:0 BRP[7:0] R/W 0
Default
Value
Description
Arbitration Phase (Nominal) Baud Rate Prescaler.
These bits indicate the prescaler value.
The a c tual v alue is o ne more than the value w ritten t o the re gister.
These bits can be written only when the CEN bit in SRR is 0.
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Chapter 2: Product Specification
Send Feedback
Arbitration Phase (Nominal) Bit Timing Register (Address Offset + 0x000C)
Table 2-8: Arbitration Phase Bit Register
Bits Name Access
31:23 Reserved – 0 Reserved.
22:16 SJW[6:0] R/W 0
15 Reserved – 0 Reserved.
14:8 TS2[6:0] R/W 0
7:0 TS1[7:0] R/W 0
Default
Value
Synchronization Jump Width.
Indicates the Synchronization Jump Width as specified in the
standard for Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
Time Segment 2
Indicates the Phase Segment 2 as specified in the standard for
Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1
as specified in the standard for Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
Error Count Register (Address Offset + 0x0010)
Description
The ECR is a read-only register. Writes to the ECR have no effect. The values of the error
counters in the register reflect the values of the transmit and receive error counters in the
core. The following conditions reset the Transmit and Receive Error counters:
• When 1 is written to the SRST bit in the SRR.
• When 0 is written to the CEN bit in the SRR.
• When the core enters Bus-Off state.
• During Bus-Off recovery until the core enters Error Active state (after 128 occurrences
of 11 consecutive recessive bits).
IMPORTANT: When in Bus-Off recovery, the Receive Error counter is advanced/incremented by 1 when
a sequence of 11 consecutive nominal recessive bits is seen.
Note: In SNOOP mode, error counters are disabled and cleared to 0. Reads to the Error Counter
register return 0.
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.
Send Feedback
Table 2-9: Error Counter Register
Chapter 2: Product Specification
Bits Name Access
31:16 Reserved – 0 Reserved.
15:8 REC[7:0] R 0
7:0 TEC[7:0] R 0
Default
Value
Description
Receive Error Count.
Indicates the value of Receive Error Counter.
Transmit Error Count.
Indicates the value of Transmit Error Counter.
Error Status Register (Address Offset + 0x0014)
The Error Status register (ESR) indicates the type of error that has occurred on the bus. If
more than one error occurs, all relevant error flag bits are set in this register. The ESR is a
write 1 to clear register. Writes to this register do not set any bits, but clear the bits that are
set.
Table 2-10: Error Status Register
Bits Name
31:12 Reserved 0 Reserved
11 F_BERR 0
Default
Value
Description
Bit Error in CAN FD Data Phase
• 1 = Indicates a bit error occurred in Data Phase (Fast) data rate.
• 0 = Indicates a b it error h as not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
(1)
.
Stuff Error in CAN FD Data Phase.
• 1 = Indicates stuff error occurred in Data Phase (Fast) data rate.
10 F_STER 0
9F_FMER 0
8F_CRCER 0
7:5 Reserved 0 Reserved.
• 0 = Ind icate s stu f f err o r has not occurred in Data Phase (Fast) data rate.
after the last write to this bit.
If this bit is set, writing a 1 clears it.
Form Error in CAN FD Data Phase.
• 1 = Indicates form error occurred in Data Phase (Fast) data rate.
• 0 = Indicates form error has not occurred in Data Phase (Fast) da ta rate .
after the last write to this bit.
If this bit is set, writing a 1 clears it.
CRC Error in CAN FD Data Phase.
• 1 = Indicates CRC error occurred in Data Phase (Fast) data rate.
• 0 = Indicates CRC error has not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
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Table 2-10: Error Status Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name
4ACKER 0
3BERR 0
2STER 0
Default
Value
Description
ACK Error.
Indicates an acknowledgment error.
• 1 = Indicates an acknowledgment error has occurred.
• 0 = Indicates an acknowledgment error has not occurred on the bus
after the last write to this bit.
If this bit is set, writing a 1 clears it.
Bit Error.
Indicates the received bit is not the same as the transmitted
bit during bus communication.
• 1 = Indicates a bit error has occurred.
• 0 = I ndi cat es a bit error ha s not oc cur red on t he b us after the last write
to this bit.
If this bit is set, writing a 1 clears it.
Stuff Error.
Indicates an error if there is a stuffing violation.
• 1 = Indicates a stuff error has occurred.
• 0 = Indicates a stuff error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
Form Error.
Indicates an error in one of the fixed form fields in the message frame.
1FMER 0
0CRCER 0
Notes:
1. In transmitter delay compensation phase, any error is reported as fast bit error (by the transmitter).
2. Fixed stuff bit errors are reported as form error.
3. In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.
• 1 = Indicates a form error has occurred.
• 0 = Indicates a form error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
CRC Error
Indicates a CRC error has occurred.
• 1 = Indicates a CRC error has occurred.
• 0 = Indicates a CRC error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
(3)
.
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Status Register (Address Offset + 0x0018)
Send Feedback
Table 2-11: Status Register
Chapter 2: Product Specification
Bits Name Access
31:21 Reserved – 0 Reserved.
22:16 TDCV[6:0] R 0
15:13 Reserved – 0 Reserved.
12 SNOOP R 0
11 Reserved – 0 Reserved.
10 BSFR_CONFIG R 0
9PEE_CONFIG R 0
Default
Value
Transmitter Delay Compensation Value.
This field gives the position of secondary sample point
(d efined as sum of TDCOFF a nd measured del ay for FDF to
res bit falling edge from TX to RX in CAN FD frame) in CAN
clocks. This field is for status purposes.
Snoop Mode.
• 1 = Indicates controller is in Snoop mode provided
Normal mode bit is also set in this register.
Bus-Off Recovery Mode Indicator.
• 1 = Indicates the core is in Bus-Off Recovery mode (Bus
Integration State).
When this bit is set, the BBSY and NORMAL status bits in
this register do not mean anything.
PEE Mode Indicator.
• 1 = Indicates the core is in PEE mode (Bus Integration
State).
When this bit is set, the BBSY and NORMAL status bits in
this register do not mean anything.
Description
8:7 ESTAT[1:0] R 0
6 ERRWRN R 0
5BBSY R0
Error Status.
Indicates the error status of the core.
• 00 = Indicates Configuration mode (CONFIG = 1). Error
state is undefined.
• 01 = Indicates error active state.
• 11 = Indicates error passive state.
• 10 = Indicates Bus-Off state.
Error Warning.
Indicates that either the Transmit Error counter or the
Receive Error counter has exceeded a value of 96.
• 1 = one or more error counters have a value of 96.
• 0 = neither of the error counters has a value of 96.
Indicates the CAN bus status.
• 1 = Indicates that the core is either receiving a message
or transmitting a message.
• 0 = Indicates that the core is either in Configuration
mode or the bus is idle.
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Table 2-11: Status Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name Access
4BIDLE R 0
3NORMAL R 0
2SLEEP R 0
1LBACK R 0
0CONFIG R 1
Default
Value
Description
Bus Idle.
Indicates the CAN bus status.
• 1 = Indicates no bus communication is taking place.
• 0 = In dica tes t he co re is eit her in Configuration mode or
the bus is busy.
Normal Mode.
Indicates that the core is in Normal mode.
• 1 = Indicates that the core is in Normal mode.
• 0 = Indicates that the core is not in Normal mode.
Sleep Mode.
Indicates that the core is in Sleep mode.
• 1 = Indicates that the core is in Sleep mode.
• 0 = Indicates that the core is not in Sleep mode.
Loopback Mode.
Indicates that the core is in Loopback mode.
• 1 = Indicates that the core is in Loopback mode.
• 0 = Indicates that the core is not in Loopback mode.
Configuration Mode Indicator.
Indicates that the core is in Configuration mode.
• 1 = Indicates that the core is in Configuration mode.
• 0 = Indicates that the core is not in Configuration mode.
Interrupt Status Register (Address Offset + 0x001C)
Interrupt status bits in the ISR can be cleared by writing to the Interrupt Clear register. For
all bits in the ISR, a set condition takes priority over the clear condition and the bit
continues to remain 1.
Table 2-12: Interrupt Status Register
Bits Name Access
31 TXEWMFLL R 0
30 TXEOFLW R 0
Default
Value
Description
TX Event FIFO Watermark Full Interrupt.
• 1 = Indicates that TX Event FIFO is full based on watermark
programming.
The interrupt continues to assert as long as the TX Event FIFO Fill Level
is above TX Event FIFO Full watermark. This bit can be cleared by
writing to the respective bit in the ICR.
TX Event FIFO Overflow Interrupt.
• 1 = Indicates that a message has been lost. This condition occurs
when the core has successfully transmitted a message for which an
event store is requested but the TX Event FIFO is full.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
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Table 2-12: Interrupt Status Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name Access
29:24 RXBOFLW_BI R 0
23:18 RXLRM_BI R 0
17 RXMNF R 0
Default
Value
Description
RX Buffer Index for Overflow Interrupt (Mailbox mode).
Gives RX Buffer index for which overflow event is generated. This field
is automatically cleared to default if RXBOFLW bit is cleared in this
register. In case more than one overflow event happens (before Host
could clear RXBOFLW), RXBOFLW_BI shows the overflow index for the
last event. This field has meaning only if the overflow interrupt
RXBOFLW bit is set. This field is also cleared at hard/soft reset or when
a 0 is written to the CEN bit in the SRR.
RX Buffer Index for Last Received Message (Mailbox mode).
Gives the RX Buffer index for the last received message. This field has
meaning only if the RXOK bit is set in this register. This field is cleared
at hard/soft reset or when a 0 is written to the CEN bit in the SRR.
RX Match Not Finished.
• 1 = Indicates that Match process did not finish until the start of sixth
bit in EOF field and frame was discarded.
This bit can be cleared by writing to the respective bit in the ICR.
RX Buffer Overflow Interrupt (Mailbox mode).
• 1 = Indicates that a message has been lost due to buffer overflow
condition. Buffer index is captured in RXBOFLW_BI field.
This bit can be cleared by writing to the respective bit in the ICR.
16
15
14 TXCRS R 0
RXBOFLW/
RXFWMFLL_1
RXRBF/
RXFOFLW_1
R0
R0
RX FIFO 1 Watermark Full Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that RX FIFO-1 is full based on watermark
programming.
This interrupt is only available when RX FIFO-1 is enabled.
Note:
The interrupt continues to assert as long as the RX FIFO-1 Fill Level is
above the RX FIFO-1 Full watermark.
This bit can be cleared by writing to the respective bit in the ICR.
RX Buffer Full Interrupt (Mailbox mode).
• 1 = Indicates that a receive buffer has received a message and
become full.
This bit can be cleared by writing to the respective bit in the ICR.
RX FIFO-1 Overflow Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that a message has been lost. This condition occurs
when a new message with ID matching to Receive FIFO 1 is received
and the Receive FIFO 1 is full.
This interrupt is only available when RX FIFO-1 is enabled.
Note:
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
TX Cancellation Request Served Interrupt.
• 1 = Indicates that a cancellation request was cleared.
This bit can be cleared by writing to the respective bit in the ICR.
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Table 2-12: Interrupt Status Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name Access
13 TXRRS R 0
12 RXFWMFLL R 0
11 WKUP R 0
10 SLP R 0
9BSOFFR0
Default
Value
Description
TX Buffer Ready Request Served Interrupt.
• 1 = Indicates that a Buffer Ready request was cleared.
This bit can be cleared by writing to the respective bit in the ICR.
RX FIFO-0 Watermark Full Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that RX FIFO-0 is full based on watermark
programming.
The interrupt continues to assert as long as the RX FIFO-0 Fill Level is
above RX FIFO-0 Full watermark.
This bit can be cleared by writing to the respective bit in the ICR.
Wake-Up Interrupt
• 1 = Indicates that the core entered Normal mode from Sleep mode.
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Sleep Interrupt.
• 1 = Indicates that the CAN core entered Sleep mode.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Bus-Off Interrupt.
• 1 = Indicates that the CAN core entered the Bus-Off state.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Error Interrupt.
• 1 = Indicates that an error occurred during message transmission or
8ERRORR0
7 Reserved – 0 Reserved.
6RXFOFLWR 0
5TSCNT_OFLWR 0
4RXOK(1)R0
reception.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
RX FIFO-0 Overflow Interrupt (Sequential/FIFO Mode).
• 1 = Indicates that a message has been lost. This condition occurs
when a new message with ID matching to RX FIFO-0 is received and
the RX FIFO-0 is full.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Timestamp Counter Overflow Interrupt.
• 1 = Indicates that Timestamp counter rolled over (from 0xffff to 0x0).
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
New Message Received Interrupt
• 1 = Indicates that a message was received successfully and stored
into the RX FIFO-0 or RX FIFO-1 or RX Mailbox buffer.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
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Table 2-12: Interrupt Status Register (Cont’d)
Send Feedback
Chapter 2: Product Specification
Bits Name Access
3BSFRDR0
2PEER0
1TXOK(1)R0
0ARBLSTR0
Notes:
1. In Loopback mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.
Default
Value
Description
Bus-Off Recovery Done Interrupt.
• 1 = Indicates that the core recovered from Bus-Off state.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Protocol Exception Event Interrupt.
• 1 = Indicates that the core (CAN FD receive r) has detected PEE event.
This bit can be cleared by writing to the respective bit in the ICR.
This bit is also cleared when a 0 is written to the CEN bit in the SRR.
Transmission Successful Interrupt.
• 1 = Indicates that a message was transmitted successfully.
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Arbitration Lost Interrupt.
• 1 = Indicates that arbitration was lost during message transmission.
This bit can be cleared by writing to the respective bit in the ICR. This
bit is also cleared when a 0 is written to the CEN bit in the SRR.
Interrupt Enable Register (Address Offset + 0x0020)
The Interrupt Enable register (IER) bits are used to enable interrupt generation when
respective event happens.
Table 2-13: Interrupt Enable Register
Bits Name Access
31 ETXEWMFLL R/W 0
30 ETXEOFLW R/W 0
17 ERXMNF R/W 0
Default
Value
Description
TX Event FIFO Watermark Full Interrupt Enable.
• 1 = Enables interrupt generation if TXEWMFLL bit in the ISR is set.
• 0 = Disables interrupt generation if TXEWMFLL bit in the ISR is set.
TX Event FIFO Overflow Interrupt Enable.
• 1 = Enables interrupt generation if TXEOFLW bit in the ISR is set.
• 0 = Disables interrupt generation if TXEOFLW bit in the ISR is set.
RX Match Not Finished interrupt Enable.
• 1 = Enables interrupt generation if RXMNF bit in the ISR is set.
• 0 = Disables interrupt generation if RXMNF bit in the ISR is set.
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Table 2-13: Interrupt Enable Register (Cont’d)
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Bits Name Access
16
15
14 ETXCRS R/W 0
13 ETXRRS R/W 0
ERXBOFLW/
ERXFWMFLL_1
ERXRBF/
ERXFOFLW_1
R/W 0
R/W 0
Default
Value
Description
RX Buffer Overflow interrupt Enable (Mailbox mode).
• 1 = Enables interrupt generation if RXBOFLW bit in the ISR is set.
• 0 = Disables interrupt generation if RXBOFLW bit in the ISR is set.
RX FIFO-1 Watermark Full Interrupt Enable (Sequential/FIFO Mode).
• 1 = E nab les int err upt genera tion if RXFWMFLL_1 bit in the ISR is set.
• 0 = Disables interrupt generation if RXFWMFLL_1 bit in the ISR is
set.
RX Buffer Bull Interrupt Enable (Mailbox mode).
• 1 = Enables interrupt generation if RXRBF bit in the ISR is set.
• 0 = Disables interrupt generation if RXRBF bit in the ISR is set.
RX FIFO-1 Overflow Interrupt Enable (Sequential/FIFO Mode).
• 1 = Enables interrupt generation if RFXOFLW_1 bit in the ISR is set.
• 0 = Disables interrupt generation if RFXOFLW_1 bit in the ISR is set.
TX Cancellation Request Served Interrupt Enable.
• 1 = Enables interrupt generation if TXCRS bit in the ISR is set.
• 0 = Disables interrupt generation if TXCRS bit in the ISR is set.
TX Buffer Ready Request Served Interrupt Enable.
• 1 = Enables interrupt generation if TXRRS bit in the ISR is set.
• 0 = Disables interrupt generation if TXRRS bit in the ISR is set.
RX FIFO-0 Watermark Full Interrupt Enable (Sequential/FIFO Mode).
12 ERXFWMFLL R/W 0
11 EWKUP R/W 0
10 ESLP R/W 0
9EBSOFFR/W0
8EERRORR/W0
7 Reserved – 0 Reserved
6ERFXOFLWR/W0
• 1 = Enables interrupt generation if RXFWMFLL bit in the ISR is set.
• 0 = Disables interrupt generation if RXFWMFLL bit in the ISR is set.
Wake-Up Interrupt Enable.
• 1 = Enables interrupt generation if WKUP bit in the ISR is set.
• 0 = Disables interrupt generation if WKUP bit in the ISR is set.
Sleep Interrupt Enable.
• 1 = Enables interrupt generation if SLP bit in the ISR is set.
• 0 = Disables interrupt generation if SLP bit in the ISR is set.
Bus-Off Interrupt Enable.
• 1 = Enables interrupt generation if BSOFF bit in the ISR is set.
• 0 = Disables interrupt generation if BSOFF bit in the ISR is set.
Error Interrupt Enable.
• 1 = Enables interrupt generation if ERROR bit in the ISR is set.
• 0 = Disables interrupt generation if ERROR bit in the ISR is set.
RX FIFO-0 Overflow Interrupt Enable (Sequential/FIFO Mode).
• 1 = Enables interrupt generation if RFXOFLW bit in the ISR is
• 0 = Disables interrupt generation if RFXOFLW bit in the ISR is set.
set.
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Table 2-13: Interrupt Enable Register (Cont’d)
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Bits Name Access
5ETSCNT_OFLWR/W 0
4ERXOKR/W0
3EBSFRDR/W0
2EPEER/W0
1ETXOKR/W0
0EARBLOSTR/W0
Default
Value
Timestamp Counter Overflow Interrupt Enable.
• 1 = Enables interrupt generation if TSCNT_OFLW bit in the ISR is set.
• 0 = Disables interrupt generation if TSCNT_OFLW bit in the ISR is set.
Description
New Message Received Interrupt Enable.
• 1 = Enables interrupt generation if RXOK bit in the ISR is set.
• 0 = Disables interrupt generation if RXOK bit in the ISR is set.
Bus-Off Recovery Done Interrupt Enable.
• 1 = Enables interrupt generation if BSFRD bit in the ISR is set.
• 0 = Disables interrupt generation if BSFRD bit in the ISR is set.
Protocol Exception Event Interrupt Enable.
• 1 = Enables interrupt generation if PEE bit in the ISR is set.
• 0 = Disables interrupt generation if PEE bit in the ISR is set.
Transmission Successful Interrupt Enable.
• 1 = Enables interrupt generation if TXOK bit in the ISR is set.
• 0 = Disables interrupt generation if TXOK bit in the ISR is set.
Arbitration Lost Interrupt Enable
• 1 = Enables interrupt generation if ARBLST bit in the ISR is set.
• 0 = Disables interrupt generation if ARBLST bit in the ISR is set.
Interrupt Clear Register (Address Offset + 0x0024)
The Interrupt Clear register (ICR) is used to clear interrupt status bits in the ISR register.
Table 2-14: Interrupt Clear Register
Bits Name Access
31 CTXEWMFLL W 0
30 CTXEOFLW W 0
17 CRXMNF W 0
16
CRXBOFLW/
CRXFWMFLL_1
Default
Value
W0
Description
• 1 = Clears TX Event FIFO Watermark Full interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Event FIFO Overflow interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX Match Not Finished interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Cle ars RX Buffer Overflow inte rrupt statu s bit (Mailbox mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-1 Watermark Full interrupt status bit
(Sequential/FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
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Table 2-14: Interrupt Clear Register (Cont’d)
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Bits Name Access
15
14 CTXCRS W 0
13 CTXRRS W 0
12 CRXFWMFLL W 0
11 CWKUP W 0
CRXRBF/
CRXFWMFLL_1
Default
W0
Value
Description
• 1 = Clears RX Buffer Bull Interrupt status bit (Mailbox mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-1 Overflow interrupt status bit (Sequential/
FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Cancellation Request Served Interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears TX Buffer Ready Request Served Interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-0 Watermark Full interrupt status bit
(Sequential/FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Wake-Up interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Sleep interrupt status bit.
10 CSLP W 0
9CBSOFFW0
8CERRORW0
7 Reserved – 0 Reserved.
6CRFXOFLWW0
5ETSCNT_OFLWW 0
4CRXOKW0
3CBSFRDW0
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Bus-Off interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Error interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears RX FIFO-0 Overflow interrupt status bit (Sequential/
FIFO Mode).
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Timestamp Counter Overflow Interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads always 0.
• 1 = Clears New Message Received interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Bus-Off Recovery Done interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
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Table 2-14: Interrupt Clear Register (Cont’d)
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Bits Name Access
2CPEEW0
1 CTXOK W 0 • 1 = Clears Transmission Successful interrupt status bit.
0CARBLOSTW0
Default
Value
Description
• 1 = Clears Protocol Exception Event interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
• 1 = Clears Arbitration Lost interrupt status bit.
Writing a 1 to this bit clears the respective bit in the ISR. Reads
always 0.
Timestamp Register (Address Offset + 0x0028)
A 16-bit free running counter increments once every sixteen CAN clock cycles. A timestamp
is captured after the SOF bit; that is, when the ID field starts on the CAN bus. It is stamped
in DLC field of the message element when frame is successfully received or transmitted. The
timestamp counter can be reset by software. There is no register bit to indicate counter
rollover.
Table 2-15: Timestamp Register
Bits Name Access
Default
Value
Description
Timestamp Counter Value.
31:16 TIMESTAMP_CNT[15:0] R 0
15:1 Reserved – 0 Reserved
0CTSW0
This Status field gives running value of the timestamp counter.
This field is cleared when a 0 is written to the CEN bit in the
SRR.
Clear Timestamp Counter.
Internal free running counter is cleared to 0 when CTS = 1.
This bit only needs to be written once with a 1 to clear the
counter.
The bit always reads as 0.
Data Phase Baud Rate Prescaler Register (Address Offset + 0x0088)
Table 2-16: Data Phase Baud Rate Prescaler Register
Bits Name Access
31:17 Reserved – 0 Reserved
16 TDC R/W 0
Default
Value
Transmitter Delay Compensation (TDC) Enable
• 1 = Enables TDC function as specified in the CAN FD standard.
• 0 = TDC is disabled.
This bit can be written only when CEN bit in SRR is 0.
Description
15:14 Reserved – 0 Reserved
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Table 2-16: Data Phase Baud Rate Prescaler Register (Cont’d)
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Bits Name Access
13:8 TDCOFF[5:0] R/W 0
7:0 DP_BRP[7:0] R/W 0
IMPORTANT: The following boundary conditions are imposed on sum of measured loop delay and TDC
Offset:
Measured loop delay + TDCOFF < 3 bit times in the data phase
Default
Value
Description
Transmitter Delay Compensation Offset
Thi s offs et is s peci f ied i n CAN c lock c ycles and i s adde d to th e measured
transmitter delay to place the Secondary Sample Point (SSP) at
appropriate position (for example, set this to half data bit time in terms
of CAN clock cycles to place SSP in the middle of the data bit).
This bit can be written only when CEN bit in SRR is 0.
Data Phase Baud Rate Prescaler
These bits indicate the prescaler value for Data Bit Timing as specified
in the CAN FD standard.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
Ensure that the boundary condition is respected while programming the offset and data
phase bit rate. In case this sum exceeds 127 CAN clock periods, the maximum value of 127
CAN clock periods is used by the core for transmitter delay compensation.
Note:
If loop delay is < 1 data phase bit time, then TDC/SSP method is not needed.
Data Phase Bit Timing Register (Address Offset + 0x008C)
Table 2-17: Data Phase Bit Timing Register
Bits Name Access
31:20 Reserved – 0 Reserved
19:16 DP_SJW[3:0] R/W 0
15:12 Reserved – 0 Reserved
11:8 DP_TS2[3:0] R/W 0
Default
Val ue
Data Phase Synchronization Jump Width
Indicates the Synchronization Jump Width as specified in the CAN FD
standard for Data Bit Timing.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
Data Phase Time Segment 2
Indicates the Phase Segment 2 as specified in the CAN FD standard for
Data Bit Timing.
The actual value is one more than the value written to the register.
This bit can be written only when CEN bit in SRR is 0.
Description
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