Winbond Electronics W741C204, W741C205, W741C203, W741C202, W741C201 Datasheet

Preliminary W741C20X

4-BIT MICROCONTROLLER

Publication Release Date: March 1998

- 1 - Revision A3

Table of Contents--

GENERAL DESCRIPTION..............................................................................................................................2

FEATURES......................................................................................................................................................2

PIN CONFIGURATION....................................................................................................................................3

PIN DESCRIPTION..........................................................................................................................................4

BLOCK DIAGRAM...........................................................................................................................................5

FUNCTIONAL DESCRIPTION ........................................................................................................................6

ABSOLUTE MAXIMUM RATINGS................................................................................................................27

DC CHARACTERISTICS...............................................................................................................................28

AC CHARACTERISTICS...............................................................................................................................29

PAD ASSIGNMENT & POSITIONS...............................................................................................................30

TYPICAL APPLICATION CIRCUIT................................................................................................................31

INSTRUCTION SET TABLE..........................................................................................................................32

PACKAGE DIMENSIONS..............................................................................................................................79

Preliminary W741C20X

- 2 -

GENERAL DESCRIPTION

The W741C20X is a high-performance 4-bit microcontroller (µC) that operates on very low current. The device contains a 4-bit ALU, two 8-bit timers, a divider, a serial port, and five 4-bit I/O ports (including 3 output ports for LED driving). There are also seven interrupt sources and 8-level subroutine nesting for interrupt applications. The W741C20X has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation.

The W741C20X is suitable for remote controllers, toy controllers, keyboard controllers, speech synthesis LSI controllers, and other products.

FEATURES

• Operating voltage: 2.2V to 5.5V

• Crystal or RC oscillation circuit can be selected by the code option

− Crystal/Ceramic oscillator: up to 4 MHz

− RC oscillator: up to 4 MHz

• Both in crystal or RC oscillator operation mode, high-frequency (400 KHz to 4 MHz) or low-

frequency (32.768 KHz) oscillation must be determined by the code option

• Memory

− 2048 x 16 bit program ROM (including 2K x 4 bit look-up table)

− 128 x 4 bit data RAM (including 16 working registers)

• 21 input/output pins

− Input/output ports: 4 ports/16 pins

− Serial input/output port: 1 port /4 pins (high sink current for LED driving)

− MFP output pin: 1 pin (MFP)

• Power-down mode

− Hold function: no operation (except for oscillator)

− Stop function: no operation (including oscillator)

• Seven types of interrupts

− Five internal interrupts (Divider 0, Timer 0, Timer 1, and Serial I/O)

− Two external interrupts (Port RC and

INT

pin)

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

• Built-in 14-bit clock frequency divider circuit

• Two built-in 8-bit programmable countdown timers

− Timer 0: One of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

− Timer 1: Offers auto-reload function, and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected, or falling edge of pin RC.0 can be selected (output through MFP pin)

• Built-in 18/14-bit watchdog timer selectable for system reset

Preliminary W741C20X

Publication Release Date: March 1998

- 3 - Revision A3

• Powerful instruction set: 118 instructions

• 8-level subroutine (include interrupt) nesting

• One serial transmission/receiver port specified by software

• Up to 1 µS instruction cycle (with 4 MHz operating frequency)

• Packaged in 18-pin, 20-pin, 28-pin PDIP and 20-pin, 28-pin SOP

PIN CONFIGURATION

1 2 3 4 5 6 7 8 9

RB3

RB2

RB1

RA1 RA0 XIN XOUT

RC3 RC2

RC1

RES

INT

RA3

RA2

RB0

RC0

1 2 3 4 5 6 7 8 9

RE3

RE2

RE1

RA1 RA0 XIN XOUT

RD3 RD2 RD1

RES

INT

RA3

RA2

RE0

RD0

RB0

RC3

11 12 13

RB3

RB2

RB1

RC2 RC1 RC0

MFP

W741C201

W741C202/C205

18-PDIP(300 mil)

28 SKINNY(300 mil), 28 SOP

1 2 3 4 5 6 7 8 9

RB3

RB2

RB1

RA1 RA0 XIN

XOUT

RC3 RC2 RC1

RA3

RA2

RB0

RC0

W741C203

20-PDIP(300 mil)

10 11

1 2 3 4 5 6 7 8 9

RB3

RB2

RB1

RA1 RA0

XIN XOUT

RC3 RC2 RC1

RES

INT

RA3

RA2

RB0

RC0

W741C204

20 SOP

INT

RES

Preliminary W741C20X

- 4 -

PIN DESCRIPTION

SYMBOL I/O FUNCTION

XIN I Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT O Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

RA0−RA3

I/O Input/Output port. Input/output mode specified by port mode 1 register

(PM1). When used as output port, can provide high sink current for driving LED.

RB0−RB3

I/O Input/Output port. Input/output mode specified by port mode 2 register

(PM2). When used as output port, can provide high sink current for driving LED.

RC0−RC3

I/O Input/Output port. Input/output mode specified by port mode 4 register

(PM4). Each pin has an independent interrupt capability in input mode.

RD0−RD3

I/O Input/Output port. Input/output mode specified by port mode 5 register

(PM5).

RE0/DOUT RE1/CLKO RE2/DIN RE3/CLKI

I/O

Special input/output port. This port can be configured by software to act as the output of internal port RT or the serial I/O port. When used as output port, can provide high sink current for driving LED.

MFP O Output pin only.

This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1).

INT

I External interrupt pin with pull-high resistor.

RES

System reset pin with pull-high resistor. VDD I Positive power supply (+). VSS I Negative power supply (-).

Preliminary W741C20X

Publication Release Date: March 1998

- 5 - Revision A3

BLOCK DIAGRAM

XIN XOUT

STACK

(8 Levels)

RAM

(128*4)

ALU

Timer 0

(8-bit)

Timing Generator

PORT RA

PORT RB

Modulation Frequency Pulse

RA0 to 3

RB0 to 3

RE0 to 3

MFP

VDD VSS

ROM

(2048*16)

(look_up table

2K*4)

Timer 1

(8-bit)

ACC

RES

INT

Divider 0

(14-bit)

Watchdog Timer

(4-bit)

HCF

PEFHEFIEF

Central Control

Unit

EVF SEF

PSR0

. .

MUX

SEL

+1(+2)

PORT RC

RC0 to 3

PORT RD

RD0 to 3

PM0MR0

PSR1 PSR2

PORT RT

Serial I/O

MUX

(RE0/DOUT,

RE1/CLKO, RE2/DIN, RE3/CLKI)

SEL

Preliminary W741C20X

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FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip ROM containing the program instruction words. When jump or subroutine call instructions or interrupt, or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below.

ITEM ADDRESS INTERRUPT

PRIORITY

Initial Reset 000H INT 0 (Divider) 004H 1st INT 1 (Timer 0) 008H 2nd INT 2 (Port RC) 00CH 3rd INT 3 (

INT

pin) 014H 4th

INT 4 (Serial Port Input) 018H 5th INT 5 (Serial Port Output) 01CH 6th INT 6 (Timer 1) 020H 7th JMP Instruction XXXH Subroutine Call XXXH -

Stack Register (STACK)

The stack register is organized as 11 bits x 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048 × 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. Instruction MOVC R is used to read the look-up table and transfer table data to the RAM. The organization of the program memory is shown in Figure 1.

Preliminary W741C20X

Publication Release Date: March 1998

- 7 - Revision A3

3 2 1 0

7FFH

600H

2048

address

000H

16 bits

2048 x 16-bit

ACCTABLTABH

ROM address = 600H + Offset/4

Offset

0 1 1 x x x x x x x x x

- x x x x x x x x x y y

Each element (4 bits) of the look-up table

This area can be used to store both instruction code

and look-up table

Figure 1. Program Memory Organization

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

Working Register

128

address

00H

4 bits

128 x 4-bit

7FH

0FH

Figure 2. Data Memory Organization

Preliminary W741C20X

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The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section.

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

R/W R/W R/W

0123

PAGE

Note: R/W means read/write available.

Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:

000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOVA R, CF.

Preliminary W741C20X

Publication Release Date: March 1998

- 9 - Revision A3

Clock Generator

The W741C20X provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a crystal oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the range of 20 KΩ to 1.6 MΩ must be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32 KHz to 4 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to 1 µS with a 4 MHz system clock.

XIN

XOUT

XIN

XOUT

Crystal

Resistor

32 KHz or

400K to 4MHz

Figure 3. Oscillator Configuration

Divider 0

Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC). When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider 0 can be reset by executing CLR DIVR0 instruction. If the oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at each 500 mS interval.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

Preliminary W741C20X

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Q1 Q2 Q9 Q10 Q11 Q12

Q14

Q13

Fosc

HEF.0 IEF.0

1. Reset

2. CLR EVF, #01H

EVF.0

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

...

Overflow signal

WDT

Enable /Disable

PMF.3

Fosc/1024

Fosc/16384

Mask Option

Qw1 Qw2

Qw4

Qw3

R R R R

Divider0

System Reset

1. Reset

2. CLR WDT

3. CLR DIVR0

RRRR

Figure 4. Organization of Divider and Watchdog Timer

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

0123

PMF

Note: W means write only.

Bit 0, Bit 1 & Bit 2 are reserved. Bit 3 = 0 The fundamental frequency of the watch dog timer is FOSC/1024.

= 1 The fundamental frequency of the watch dog timer is FOSC/16384.

At initial reset, bit 3 of PMF is set to "0".

Preliminary W741C20X

Publication Release Date: March 1998

- 11 - Revision A3

Timer/Counter

Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instruction. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5.

If the Timer 0 clock input is FOSC/4, then:

Desired time 0 interval = (preset value +1) × 4 × 1/FOSC

If the Timer 0 clock input is FOSC/1024, then:

Desired time 0 interval = (preset value +1) × 1024 × 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency

Fosc/4

Fosc/1024

Enable

Disable

1. Reset

2. CLR EVF, #02H

8-bit Binary

Down Counter

HEF.1 IEF.1

Hold mode release (HCF.1) Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF, #02H

EVF.1

MR0.0

(Timer 0)

1. Set MR0.3 to 1

2. MOV TM0, #I

3. Reset MR0.3 to 0

3. Set MR0.3 to 1

4. MOV TM0, #I

MOV TM0H, R

MOV TM0L, R

4. MOV TM0L, R or MOV TM0H, R

MOV TM0, #I

Figure 5. Organization of Timer 0

Preliminary W741C20X

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Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: Fosc/64, Fosc, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is Fosc. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 =

1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then: Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency

Auto-reload buffer

8 bits

MR1.1

External clock

via RC.0

1. MR1.3 = 1

2. MOV TM1, #I

Underflow

signal

EVF.7

MFP

MFP signal

MR1.2

output pin

8-bit Binary

Down Counter

circuit

Reset

Disable

Enable

Fosc/64

Fosc

MR1.0

(Timer 1)

S R

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

1. MR1.3 = 0

4. Set MR1.3 to 1

MOV TM1H, R

MOV TM1L, R

Set MR1.3 to 1

MOV TM1, #I

5. MOV TM1, #I

MOV TM1, #I

Figure 6. Organization of Timer 1

Preliminary W741C20X

Publication Release Date: March 1998

- 13 - Revision A3

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.

3rd octave 4th octave 5th octave

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

C 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51 C# 138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96

T D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14

D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15

O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36

F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34

N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72

G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19

E G# 207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20

A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84 A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22 B 246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76

Note: Central tone is A4 (440 Hz).

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows:

W W

0123

MR0

Note: W means write only.

Bit 0 = 0 The fundamental frequency of Timer 0 is FOSC/4.

= 1 The fundamental frequency of Timer 0 is FOSC/1024. Bit 1 & Bit 2 are reserved Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Preliminary W741C20X

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Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows:

WW W W

0123

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin. Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and Port RB consists of pins RB.0 to RB.3. At initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 7.

I/O PIN

RA.n(RB.n)

DATA

BUS

Buffer

Output

PM0.0 (or PM0.1)

PM1.n

(or PM2.n)

MOVA R, RA (or MOVA R, RB)

instruction

MOV RA, R (or MOV RB, R) Instruction

Enable

VDD

Input/Output Pin of the RA(RB)

Figure 7. Architecture of RA & RB Input/Output Pins

Preliminary W741C20X

Publication Release Date: March 1998

- 15 - Revision A3

Port Mode 0 Register (PM0)

The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows:

PM0 w

012 w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type. Bit 2 & Bit 3 are reserved.

Port Mode 1 Register (PM1)

The port mode 1 register is organized as 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows:

PM1 w w w

012 w

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).

Port Mode 2 Register (PM2)

The port mode 2 register is organized as 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows:

PM2 w w w

012 w

Note: W means write only.

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Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B).

Port Mode 3 register (PM3)

Port Mode 3 Register is organized as a 4-bit binary register (PM3.0 to PM3.3). PM3 can be used to determine the operating mode of the output port RE and the clock rate of the serial I/O function. The PM3 control diagram is shown in Figure 8. The bit descriptions are as follows:

0123

PM3

Note: W means write only.

Bit 0 is reserved. Bit 1 = 0 The output of the port RE is the output of the internal parallel port RT.

= 1 The port RE works as the serial input/output port. Bit 2 is reserved. Bit 3 = 0 Serial Tx rate = FOSC/2

= 1 Serial Tx rate = FOSC/256

PM3.1

MUX.

Internal parallel port RT

Port RE

Fosc/2

PM3.3

Fosc/256

Serial I/O port

Figure 8. PM3 Control Diagram

Preliminary W741C20X

Publication Release Date: March 1998

- 17 - Revision A3

Port Mode 4 Register (PM4)

The port mode 4 register is organized as 4-bit binary register (PM4.0 to PM4.3). PM4 can be used to control the input/output mode of port RC. PM4 is controlled by the MOV PM4, #I instruction. The bit descriptions are as follows:

PM4 w w w

012 w

Note: W means write only.

Bit 0 = 0 RC.0 works as output pin; Bit 0 = 1 RC.0 works as input pin Bit 1 = 0 RC.1 works as output pin; Bit 1 = 1 RC.1 works as input pin Bit 2 = 0 RC.2 works as output pin; Bit 2 = 1 RC.2 works as input pin Bit 3 = 0 RC.3 works as output pin; Bit 3 = 1 RC.3 works as input pin At initial reset, port RC is input mode (PM4 = 1111B).

Port Mode 5 Register (PM5)

The port mode 5 register is organized as 4-bit binary register (PM5.0 to PM5.3). PM5 can be used to control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit descriptions are as follows:

PM5 w w w

012 w

Note: W means write only.

Bit 0 = 0 RD.0 works as output pin; Bit 0 = 1 RD.0 works as input pin Bit 1 = 0 RD.1 works as output pin; Bit 1 = 1 RD.1 works as input pin Bit 2 = 0 RD.2 works as output pin; Bit 2 = 1 RD.2 works as input pin Bit 3 = 0 RD.3 works as output pin; Bit 3 = 1 RD.3 works as input pin

At initial reset, the port RB is input mode (PM2 = 1111B).

Input/Output Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. At initial reset, input/output ports RC and RD are both in input mode. When RC and RD are used as output ports, the CMOS type is the only ouput driving type. Each pin of port RC or RD can be specified as input or output mode independently by the PM4 and PM5 registers. The MOVA R, RC or MOVA R, RD instructions operate the input functions and the MOV RC, R or MOV RD, R operate the output functions. When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of port RC, and that can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. Before the port mode of the RC port is changed from output mode to input mode in the hold mode release and interrupt application, the output value must be preset to the same as the system status to prevent the undesired signal change being accepted.

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When the interrupt of RC port is accepted, the corresponding event flag (EVF.2) will be reset, but the content of PSR0 should not be changed except the CLR PSR0 or MOV PEF, #I instruction being executed or performing the reset function. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. The RD port is used as the I/O port only. Refer to Figure 9, Figure 10 and the instruction table for more details.

I/O PIN

RC.n(RD.n)

DATA

BUS

Buffer

Output

PM4.n

(or PM5.n)

MOVA R, RC (or MOVA R, RD) instruction

MOV RC, R (or MOV RD, R) Instruction

Enable

Vdd

Input/Output Pin of the RC(RD)

Figure 9. Architecture of RC & RD Input/Output Pins

Port Enable Flag (PEF)

The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

PEF w w w

012 w

Note: W means write only.

PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.

Port Status Register 0 (PSR0)

Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

RR R R

0123

PSR0

Note: R means read only.

Preliminary W741C20X

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Bit 0 = 1 Signal change at RC.0 Bit 1 = 1 Signal change at RC.1 Bit 2 = 1 Signal change at RC.2 Bit 3 = 1 Signal change at RC.3

Reset

CLR PSR0

HCF.2

INT 2

Reset

CLR EVF, #I

EVF.2

HEF.2

IEF.2

MOV PEF, #I

Signal

change

detector

PEF.0

DATA BUS

PEF.3

Signal

change

detector

PEF.1

Signal

change

detector

PEF.2

Signal

change

detector

DckQ

PSR0.0

DckQ

PSR0.1

DckQ

PSR0.2

DckQ

PSR0.3

DckQ

RC.3

RC.2

RC.1

RC.0

SEF.0

SEF.3

SEF.1

SEF.2

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Wake up from STOP mode

PM4.3

PM4.2

PM4.1

PM4.0

PM4.3

PM4.2

PM4.1

PM4.0

MOVA R, RC

Figure 10. Input Architecture of Ports RC

Output Port RE

Output port RE can be used as an output of the internal RT port, or as a serial input/output port. The control flow is shown in Figure 8. When bit 1 of port mode 3 register (PM3) equals to 0, port RE works as an output of internal port RT. When the MOV RE, R instruction is executed, the data in the RAM will be output to port RT through port RE. When RE works as a parallel output port, it provides a high sink current to drive LEDs. When bit 1 of PM3 equals to 1, the RE port works as a serial input/output port, and RE.0 to RE.3 are used as DOUT, CLKO, DIN, and CLKI, respectively. In this case, the DIN pin will has a built-in pull-high resistor. The serial I/O functions are controlled by the instructions SOP R and SIP R. The functions of the two instructions are described below:

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(1)When the SIP R instruction is executed, the data will be loaded from the serial input buffer to

the ACC and RAM first, and bit 1 of port status register 2 will automatically be set to "1" (BUSYI = 1). Then the CLKI pin will send out 8 clocks and the data from the DIN pin will be loaded to SIB at the rising edge of the CLKI pin. After the 8 clocks have been sent, BUSYI will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5 has been set (IEF.5 = 1), an interrupt is executed; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. Users can check the status of PSR2.1 (BUSYI) to know whether the serial input process is completed or not. If a serial input process is not completed, and the SIP R instruction is executed again, the data will be lost. The timing is shown in Figure 11.

T1 T2 T3 T4

CLKI

(RE3)

Data latch

BUSYI

(PSR2.1)

EVF5

Ins.

DIN

(RE2)

SIP R

1 2 3

5 6 7 8

Notes : 1. These clocks at the CLKI pin are internal clock and its frequency is Fosc/2.

2. When the internal signal of the data latch equals to "1," then the data in SIB will be loaded into RAM and ACC.

Figure 11. Timing of the Serial Input Function (SIP R)

(2)When the SOP R instruction is executed, the data will be loaded to the serial output buffer

(SOB) and bit 3 of port status register 2 will be set to "1" (BUSYO = 1). Then the CLKO pin will send out 8 clocks and the data in SOB will be sent out at the falling edge of the CLKO pin. After the 8 clocks have been sent, BUSYO will be reset to "0" and EVF.6 will be set to "1." At this time, if IEF.6 has been set (IEF.6 = 1), an interrupt is executed; if HEF.6 has been set (HEF.6 = 1), the hold state is terminated. Users can check the status of PSR2.3 (BUSYO) to know whether the serial output process is completed or not. If a serial output process is not completed, and the SOP R instruction is executed again, the data will be lost. The timing is shown in Figure 12.

Preliminary W741C20X

Publication Release Date: March 1998

- 21 - Revision A3

T1 T2 T3 T4

CLKO

(RE1)

Data

latch

BUSYO

(PSR2.3)

EVF6

Ins.

DOUT

(RE0)

SOP R

1 2 3

5 6 7 8

Notes : 1. These clocks at the CLKO pin are internal clock and its frequency is Fosc/2.

2. When the internal signal of the data latch equals to "1," then the data of the RAM and ACC be loaded to SOB.

Figure 12. Timing of the Serial Output Function (SOP R)

In the above description, the low nibble location of the serial input/output register is contributed to the ACC, and the high nibble is to R. The port status register 2 (PSR2) including BUSYI, and BUSYO can be read out or cleared by the MOVA R, PSR2, or CLR PSR2 instruction.

Port Status Register 2 (PSR2)

Port status register 2 is organized as 4-bit binary register (PSR2.0 to PSR2.3). PSR2 is controlled by the MOVA R, PSR2, and CLR PSR2 instructions. The bit descriptions are as follows:

0123

PSR2

Note: R means read only.

Bit 0 is reserved. Bit 1 (BUSYI): Serial port input busy flag. Bit 2 is reserved. Bit 3 (BUSYO): Serial port output busy flag.

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MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below.

(FOSC = 32.768 KHz)

R7 R6 R5 R4 R3 R2 R1 R0 FUNCTION

0 0 0 0 0 0 Low level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 0 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 High level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 1 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 2048 Hz 0 0 0 0 0 1 2048 Hz * 128 Hz 0 0 0 0 1 0 2048 Hz * 64 Hz

1 0 0 0 0 1 0 0 2048 Hz * 8 Hz

0 0 1 0 0 0 2048 Hz * 4 Hz 0 1 0 0 0 0 2048 Hz * 2 Hz 1 0 0 0 0 0 2048 Hz * 1 Hz 0 0 0 0 0 0 4096 Hz 0 0 0 0 0 1 4096 Hz * 128 Hz 0 0 0 0 1 0 4096 Hz * 64 Hz

1 1 0 0 0 1 0 0 4096 Hz * 8 Hz

0 0 1 0 0 0 4096 Hz * 4 Hz 0 1 0 0 0 0 4096 Hz * 2 Hz 1 0 0 0 0 0 4096 Hz * 1 Hz

Preliminary W741C20X

Publication Release Date: March 1998

- 23 - Revision A3

Interrupts

The W741C20X provides five internal interrupt sources (Divider 0, Timer 0, Timer 1, serial I/O) and two external interrupt sources (

INT

, port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 14. The control diagram is shown below.

SRQ

IEF.0

IEF.1

Interrupt Process

Circuit

Interrupt

Vector

Generator

004H 008H

020H

IEF.7

Initial Reset CLR EVF,#I instruction

DIS INT instruction

Initial Reset

MOV IEF,#I

Enable

EN INT

EVF.1

EVF.0

EVF.7

Disable

Divider 0

overflow signal

Timer 0

underflow signal

Timer 1

underflow signal

Figure 13. Interrupt event control diagram

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. To enable these interrupts, the instructions MOV IEF, #I or EN INT must be executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows:

w w w

123

IEF

w w

56 0

Note: W means write only.

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IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC. IEF.3 is reserved.

IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal at the

INT

pin. IEF.5 = 1 Interrupt 5 is accepted by the serial port received completely. IEF.6 = 1 Interrupt 6 is accepted by the serial port transmitted completely. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

External INT

The external interrupt

INT

pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the

falling edge of the

INT

pin will execute the hold mode release or interrupt subroutine. A low level on

the

INT

pin will release the stop mode.

Stop Mode Operation

In stop mode, all operations of the µC cease (including the operation of the oscillator). The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is

activated (by a low level on the

INT

pin or a falling signal on the RC port). When the designated

signal is accepted, the µC awakens and warms up, and then executes the next instruction.

Stop Mode Wake-up Enable Flag for Ports RC (SEF)

The stop mode wake-up flag for ports RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

SEF w w w

012 w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0 SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1 SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2 SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3

Hold Mode Operation

In hold mode, all operations of the µC cease, except for the operation of the oscillator and timer. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released in one

of five ways: by the action of timer 0, timer 1, the divider, the

INT

pin, the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.

Preliminary W741C20X

Publication Release Date: March 1998

- 25 - Revision A3

Divider 0, /INT, Timer 0, Timer 1, Serial I/O and signal Change at RC Port

In HOLD Mode?

IEF

Flag Set?

PC <- (PC+1)

IEF

Flag Set?

Yes

NoYes

Yes

YesNo

HOLD

HEF

Flag Set?

Reset EVF Flag

Execute

Interrupt Service Routine

Reset EVF Flag

Execute

Interrupt Service Routine

Interrupt

Enable?

Interrupt

Enable?

Yes

NoNo

Disable interrupt

(Note)

Note: The bit of EVF corresponding to the interrupt signal will be reset.

Figure 14. Hold Mode and Interrupt Operation Flow Chart

Preliminary W741C20X

- 26 -

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows:

012

HEF w w w w

34567

w w

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released. HEF.2 = 1 Signal change at port RC causes Hold mode to be released. HEF.3 is reserved.

HEF.4 = 1 Falling edge signal at the

INT

pin causes Hold mode to be released. HEF.5 = 1 The serial port received completely causes Hold mode to be released. HEF.6 = 1 The serial port transmitted completely causes Hold mode to be released. HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF or MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

R R R RHCF

012345

R R R

Note: R means read only.

HCF.0 = 1 Hold mode was released by overflow from the Divider 0 HCF.1 = 1 Hold mode was released by underflow from the timer 0 HCF.2 = 1 Hold mode was released by a signal change at port RC HCF.3 is reserved.

HCF.4 = 1 Hold mode was released by a falling edge signal at the

INT

pin HCF.5 = 1 Hold mode was released by underflow from the timer 1 HCF.6 = 1 Hold mode was released by the serial port received completely. HCF.7 = 1 Hold mode was released by the serial port transmitted completely.

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