Winbond Electronics W742E81A, W742C81A Datasheet

Preliminary W742E81A/W742C81A

4-BIT MICROCONTROLLER

1. GENERAL DESCRIPTION

The W742E81A/W742C81A is a high-performance 4-bit microcontroller (µC) that provides an LCD
driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual­clock operation, a 40 × 4 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving), and
one channel DTMF generator. There are also five interrupt sources and 16-levels subroutine nesting
for interrupt applications. The W742E81A/W742C81A operates on very low current and has two
power reduction modes, that is the dual-clock slow operation and STOP mode, which help to
minimize power dissipation.

2. FEATURES

•

Operating voltage: 2.4V−3.8V

•

Dual-clock operation or single-clock operation (By option)

•

Main-oscillator

− Connect to 3.58 MHz crystal or 400 KHz that can be selected by option code

− Crystal or RC oscillator can be selected by code option (W742E81A)

− Connect to 2 MHz typical RC oscillator (W742C81A)

•

Sub-oscillator

− Connect to 32768 Hz crystal only

•

Memory

− 16384 x 16 bits program flash EEPROM (including 64K x 4 bit look-up table)

− 2048 x 4 bits data RAM (including 16 nibbles x 16 pages working registers)

− 40 x 4 LCD data RAM

•

24 input/output pins

− Port for input only: 1 ports/4 pins(RC)

− Input/output ports: 3 ports/12 pins(RA, RB & RD)

− High sink current output port for LED driving: 1 port /4 pins(RE)

− Port for output only: 1 port/ 4 pins(RF)

•

Power-down mode

− Hold function: no operation (main-oscillator and sub-oscillator still operate)

− Stop function: no operation (main-oscillator and sub-oscillator are stopped)

− Dual-clock slow operation mode: system is operated by the sub-oscillator (F
stopped)

•

Five types of interrupts

− Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1)

− One external interrupts (RC Port)

OSC

=Fs and Fm is

Publication Release Date: April 2000

- 1 - Revision A1

Preliminary W742E81A/W742C81A

bit watchdog timer selectable for system reset; enable the watch dog timer or not is

•

LCD driver output

− 40 segments x 4 commons

− 1/4 duty 1/3 bias driving mode

− Clock source should be the sub-oscillator clock in the dual-clock operation mode

•

MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

•

DTMF output pin

− Output is one channel Dual Tone Multi-Frequency signal for dialling

•

Two built-in 14-bit frequency dividers

− Divider0: the clock source is the output of the main-oscillator

− Divider1: the clock source is the output of the sub-oscillator (dual-clock mode) or the Fosc/128
(single-clock mode)

•

Two built-in 8-bit programmable countdown timers

− Timer 0: one of two internal clock frequencies (F

OSC

− Timer 1: with auto-reload function and one of three internal clock frequencies (F
Fs) can be selected by MR1 register; and the specified frequency can be delivered to MFP pin

•

Built-in 18/15-

determined by code option

•

Powerful instruction set: 142 instructions

•

16-levels subroutine (include interrupt) nesting

/4 or F

OSC

/1024) can be selected

OSC, FOSC

/64 or

- 2 -

3. PIN CONFIGURATION

For W742E81A

X
O

X

D

U

I

T

R

NCNCN

N

C

C

T

N

M

E

1

1

F

S

Preliminary W742E81A/W742C81A

S

S

S

S

S

S

X
O

X

D

U

I

V

H

T

N

D

1

2

2

D

C

V

V

O

D

D

D

M

D

D

H

0

2

1

2

S

E

E

E

E

C

C

C

O

O

O

M

M

M

3

2

1

G

G

G

G

3

3

3

3

6

7

8

9

S

E

E

E

E

G

G

G

G

3

3

3

3

3

4

5

2

N
CNCNC

NC
MFP

RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC3
RD0
RD1
RD2
RD3
NC
NC

80 79 78 77 76 75 74 73 72 717069 68 67 666564 63 62

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1 2 3

4 5 6 7 8 91011 12 13 14 15 16 17 18 19

R

N
C

NCR

R

R

R

R

R

R

S

S

N

E

E

E

E

F

F

F

C

1

2

0

3

F

0

1

2

3

S

V

E

E

E

S

G

G

G

S

0

1

2

61 60 59 58 57

20 21 22 23 24

S

S

S

S

S

E

E

G

G

3

4

S

E

E

E

E

G

G

G

G

5

6

7

8

S

S

E

E

G

G

9

56 55 54 53 52

25 26 27 28 29

S

S

E

E

G

G

1

1

1

0

1

2

51

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

S

S
E
G

1
3

N

NCN

E

C

C

G

1
4

NC
NC
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25

SEG24
SEG23
SEG22
SEG21
SEG20
SEG19

SEG18

SEG17

SEG16

SEG15
NC

Publication Release Date: April 2000

- 3 - Revision A1

For W742C810

Preliminary W742E81A/W742C81A

S

S

S

S

S

S

X

X

O

X

O

X

D

U

I

T

R

NCNCN

N

C

C

T

N

M

E

1

1

F

S

D

U

I

V

H

T

N

D

1

2

2

D

C

V

V

O

D

D

D

M

D

D

H

0

2

1

2

S

E

E

E

C

C

C

O

O

M

M

2

1

G

G

G

O

3

3

3

M

7

8

9

3

E

E

E

E

G

G

G

G

3

3

3

3

3

4

5

6

NCNCN

N

C

C

NC
MFP

RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC3
RD0
RD1
RD2
RD3
RE0
NC

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

1 2 3

4 5 6 7 8 91011 12 13 14 15 16 17 18 19

R

N

N

C

C

R

R

R

R

R

R

S

S

N

N

E

E

E

F

F

F

C

C

1

2

3

F

0

1

2

3

S

V

E

E

E

S

G

G

G

S

0

1

2

61 60 59 58 57

20 21 22 23 24

S

S

S

S

S

E

E

G

G

3

4

S

E

E

E

E

G

G

G

G

5

6

7

8

S
E

G
9

56 55 54 53 52

25 26 27 28

S

S

S

E

E

E

G

G

1

1

0

1

51

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

30

29

S
E

G

G

1

1

2

3

N

NCN

N

C

C

C

NC
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14

- 4 -

O
O

RES

Preliminary W742E81A/W742C81A

4. PIN DESCRIPTION

SYMBOL I/O FUNCTION

XIN2 I Input pin for sub-oscillator.

Connected to 32.768 KHz crystal only.

XOUT2 O Output pin for sub-oscillator with internal oscillation capacitor. Connected

to 32.768 KHz crystal only.

XIN1 I Input pin for main-oscillator.

Connected to 3.58 MHz or 400 KHz crystal or RC to generate system
clock.

XOUT1 O Output pin for main-oscillator.

Connected to 3.58 MHz or 400 KHz crystal or RC to generate system
clock.

RA0−RA3

RB0−RB3

RC0−RC3

RD0−RD3

RE0−RE3
RF0−RF3

MFP

DTMF O This pin can output dual-tone multifrequency signal for dialling.

SEG0−SEG39
COM0−COM3

DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor.

DD1

V

DD2

V
VDD I Positive power supply (+).
VSS I Negative power supply (-).

I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

I 4-bit port for input only.

Each pin has an independent interrupt capability.

I/O Input/Output port.

Input/output mode specified by port mode 5 register (PM5).
Output port only. With high sink current capacity for the LED application.
Output port only.

O Output pin only.

This pin can output modulating or nonmodulating frequency, or Timer 1
specified frequency. It can be selected by bit 0 of BUZCR (BUZCR.0).

I System reset pin with pull-high resistor.
O LCD segment output pins.
O LCD common signal output pins.

The LCD alternating frequency can be selected by code option.

I Positive (+) supply voltage terminal.

Refer to Functional Description.

Publication Release Date: April 2000

- 5 - Revision A1

Preliminary W742E81A/W742C81A

Pin Description, continued

SYMBOL I/O FUNCTION

VPP I Voltage control pin for the flash EEPROM programming, erasing and verifying.

This pin has the built-in pull-low resistor.

MODE I This pin can be used as mode selection control; data read/write clock;

program/erase control or address counter control in the flash EEPROM erasing,
programming or verifying mode. This pin has the built-in pull-low resistor.

DATA I/O Data I/O pin with the built-in pull-low resistor.

5. BLOCK DIAGRAM

VPP
DATA
MODE

RAM

(2048*4)

Flash
EEROM

(16384*16)

(look_up table
64K*4)

+1(+2)

PC

STACK

(16 Levels)

Timer 0

(8 Bit)

Watch Dog Timer

(4 Bit)

SEG0~SEG39 COM0~COM3

LCD DRIVER

ACC

ALU

Central Control

Unit

PEFHEFIEF

HCF

EVF SEF

PSR0 SCR PR

MR0

DTMF

Divider 0
(14 Bit)

MR1

DTCR

Modulation
Frequency
Pulse

PM0
PM1

. . .

Timer 1

(8 Bit)

VDD1-2 DH1-2

PORT RA

PORT RB

PORT RC

PORT RD

PORT RE

PORT RF

DTMF

Generator

Divider 1

(12/14 Bit)

Timing Generator

SEL

MUX

RA0-3

RB0-3

RC0-3

RD0-3

RE0-3

RF0-3

DTMF

MFP

VDD
VSS

RES

- 6 -

XIN1

XOUT1

XIN2 XOUT2

Preliminary W742E81A/W742C81A

6. FUNCTIONAL DESCRIPTION

6.1 Program Counter (PC)

Organized as an 14-bit binary counter (PC0 to PC13), the program counter generates the addresses
of the 16384 × 16 on-chip ROM containing the program instruction words. Before the jump or
subroutine call instructions are to be executed, the destination ROM page must be determined firstly.
The confirmation of the ROM page can be done by executing the MOV ROMPR, #I or MOV ROMPR,
R instruction. When the interrupt or initial reset conditions are to be executed, the corresponding
address will be loaded into the program counter directly. The format used is shown below.

Table 1 Vector address and interrupt priority

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 0000H ­INT 0 (Divider0) 0004H 1st
INT 1 (Timer 0) 0008H 2nd
INT 2 (Port RC) 000CH 3rd
INT 3 (Divider1) 0014H 4th
INT 4 (Timer 1) 0020H 5th
JP Instruction XXXXH ­Subroutine Call XXXXH -

6.2 Stack Register (STACK)

The stack register is organized as 49 bits x 16 levels (first-in, last-out). When either a call subroutine
or an interrupt is executed, the program counter will be pushed onto the stack register automatically.
At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be
executed to pop the contents of the stack register into the program counter. (Refer to Table 8)
When the stack register is pushed over the sixteen levels, the contents of the first level will be lost. In
other words, the stack register is always sixteen levels deep.

6.3 Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; and the look-up table is arranged as
65536 x 4 bits. The program ROM is divided into eight pages; the size of each page is 2048 x 16 bits.
So the total ROM size is 16384 x 16 bits. Before the jump or subroutine call instructions are to be
executed, the destination ROM page must be determined firstly. The ROM page can be selected by
executing the MOV ROMPR,#I or MOV ROMPR, R instruction. But the branch decision instructions
(e.g. JB0, SKB0, JZ, JC, ...) must jump to the same ROM page which the branch decision instructions
are in. The whole ROM can store both instruction codes and the look-up table. Each look-up table
element is composed of 4 bits, so the look-up table can be addressed up to 65536 elements.
Instruction MOVC R is used to read the look-up table content and transfer table data to the RAM. But
before reading the addressed look-up table content, the content of the look-up table pointer (TAB)
must be determined firstly. The address of the look-up table element is allocated by the content of
TAB. The MOV TAB0 (TAB1, TAB2, TAB3), R instructions are used to allocate the address of the
wanted look-up table element. The TAB0 register stores the LSB 4 bits of the look-up table address.

Publication Release Date: April 2000

- 7 - Revision A1

Preliminary W742E81A/W742C81A

:

:

:

:

:

:

:

:

:

:

:

:

The organization of the program memory is shown in Figure 6-1

16 bits

Look-up table address:

0000H

:

0FFFH

Look-up table address:

2000H

:

2FFFH

Look-up table address:

3000H

:

3FFFH

Look-up table address:

E000H

:

EFFFH

Look-up table address:

F000H

:

FFFFH

16384 x 16 bits

Each element (4 bits) of the look-up table

Look-up table address:

1000H

:

1FFFH

1st page

2nd page

8th page

0000H

03FFH
0400H

07FFH
0800H

0BFFH
0C00H

0FFFH

3800H

3BFFH
3C00H

3FFFH

.

Figure 6-1 Program Memory Organization

6.3.1 ROM Page Register (ROMPR)

The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

Note: W means write only.

ROMPR

W

Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 ROM page preselect bits:
000 = ROM page 0 (0000H - 07FFH)

001 = ROM page 1 (0800H - 0FFFH)
010 = ROM page 2 (1000H - 17FFH)
011 = ROM page 3 (1800H - 1FFFH)
100 = ROM page 4 (2000H - 27FFH)
101 = ROM page 5 (2800H - 2FFFH)
110 = ROM page 6 (3000H - 37FFH)
111 = ROM page 7 (3800H - 3FFFH)

- 8 -

W

W

Preliminary W742E81A/W742C81A

:

:

:

6.4 Data Memory (RAM)

6.4.1 Architecture

The static data memory (RAM) used to store data is arranged as 2048 × 4 bits. The data RAM is
divided into sixteen banks; each bank has 128 × 4 bits. Executing the MOV DBKR,WR or MOV
DBKR,#I instruction can determine which data bank is used. The data memory can be addressed
directly or indirectly. But the data bank must be confirmed firstly; and the page in the data bank will
be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be
divided into eight pages. Before the data memory is addressed indirectly, the page which the data
memory is in must be confirmed. The organization of the data memory is shown in Figure 6-2.

2048

addresses

000H

(or Working Registers bank)

07FH
080H

(or Working Registers bank)

0FFH

780H
7FFH

4 bits

1st data bank

2nd data bank

3rd data bank

:
:

16th data bank

2048 * 4 bits

Figure 6-2 Data Memory Organization

1st data RAM page

2nd data RAM page

3rd data RAM page

8th data RAM page

(or 1st WR page)

(or 2nd WR page)

(or 3rd WR page)

:
:

(or 8th WR page)

00H
0FH

10H
1FH

20H
2FH

70H
7FH

:

:

:

:

The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the
working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers.
When one page is used as WR, the others can be used as the normal data memory. The WR page
can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data memory cannot
operate directly with immediate data, but the WR can do. The relationship between data memory
locations and the page register (PAGE) in indirect addressing mode is described in the next sub­section.

6.4.2 Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

Note: R/W means read/write available.

PAGE

R/W R/W R/W

Bit 3 is reserved.
Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:

000 = Page 0 (00H - 0FH)

Publication Release Date: April 2000

- 9 - Revision A1

Preliminary W742E81A/W742C81A

001 = Page 1 (10H - 1FH)
010 = Page 2 (20H - 2FH)
011 = Page 3 (30H - 3FH)
100 = Page 4 (40H - 4FH)
101 = Page 5 (50H - 5FH)
110 = Page 6 (60H - 6FH)
111 = Page 7 (70H - 7FH)

6.4.3 WR Page Register (WRP)

The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

Note: R/W means read/write available.

Bit 3, Bit 2, Bit 1, Bit 0 Working registers page preselect bits:
0000 = WR Page 0 (00H - 0FH)

0001 = WR Page 1 (10H - 1FH)
0010 = WR Page 2 (20H - 2FH)
0011 = WR Page 3 (30H - 3FH)
0100 = WR Page 4 (40H - 4FH)
0101 = WR Page 5 (50H - 5FH)
0110 = WR Page 6 (60H - 6FH)
0111 = WR Page 7 (70H - 7FH)
1000 = WR Page 8 (80H - 8FH)
1001 = WR Page 9 (90H - 9FH)
1010 = WR Page A (A0H - AFH)
1011 = WR Page B (B0H - BFH)
1100 = WR Page C (C0H - CFH)
1101 = WR Page D (D0H - DFH)
1110 = WR Page E (E0H - EFH)
1111 = WR Page F (F0H - FFH)

WRP

R/W

R/W R/W R/W

6.4.4 Data Bank Register (DBKR)

The data bank register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

Note: R/W means read/write available.

DBKR

R/W

R/W R/W R/W

- 10 -

Preliminary W742E81A/W742C81A

Bit 3, Bit 2, Bit 1, Bit 0 Data memory bank preselect bits:
0000 = Data bank 0 (000H - 07FH)
0001 = Data bank 1 (080H - 0FFH)
0010 = Data bank 2 (100H - 17FH)
0011 = Data bank 3 (180H - 1FFH)
0100 = Data bank 4 (200H - 27FH)
0101 = Data bank 5 (280H - 2FFH)
0110 = Data bank 6 (300H - 37FH)
0111 = Data bank 7 (380H - 3FFH)
1000 = Data bank 8 (400H - 47FH)
1001 = Data bank 9 (480H - 4FFH)
1010 = Data bank A (500H - 57FH)
1011 = Data bank B (580H - 5FFH)
1100 = Data bank C (600H - 67FH)
1101 = Data bank D (680H - 6FFH)
1110 = Data bank E (700H - 77FH)
1111 = Data bank F (780H - 7FFH)

6.5 Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data
between the memory, I/O ports, and registers.

6.6 Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following
functions:

•

Logic operations: ANL, XRL, ORL

•

Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

•

Shift operations: SHRC, RRC, SHLC, RLC

•

Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is
stored in the internal registers. CF can be read out by executing MOV R, CF.

6.7 Main-Oscillator

The W742E81A/W742C81A provides a crystal or RC oscillation circuit to generate the system clock
through external connections. If a crystal oscillator is used, The 3.58 MHz or 400KHz crystal must
be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and VSS if an accurate
frequency is needed.

Publication Release Date: April 2000

- 11 - Revision A1

Preliminary W742E81A/W742C81A

XIN1

Crystal

3.58 MHz
or

400 KHz

Figure 6-3 System Clock Oscillator Configuration

XOUT1

or

XIN1

XOUT1

6.8 Sub-Oscillator

The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the
32768 Hz crystal could be connected to XIN2 and XOUT2, and it would not be oscillated in STOP
mode.

6.9 Dividers

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.
When the main oscillator starts action, the Divider0 is incremented by each clock (F
overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable
flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been
set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by
executing CLR DIVR0 instruction.

If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs in dual-clock mode or
Fosc/128 in single-clock mode). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4
= 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed,
while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the
last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. Same as EVF.0, the
EVF.4 is set to 1 periodically. But there are two period time (125 mS & 500mS) that can be selected
by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; SCR.3 = 1,
the 125 mS period time is selected.

OSC

). When an

6.10 Dual-clock operation

This operation mode is selected by option code. In the dual-clock mode, the clock source of the LCD
frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the signal-clock mode,
the clock source of the LCD frequency selector will be Fm/128(Fm : main oscillator clock, See figure

So before the STOP instruction is executing, the LCD must be turned off in the signal-

6-4).

clock mode or dual-clock mode

In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). As required, the slow operation can be performed by generating the
system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow
operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If
the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the
SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual­clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the
SCR.1 is set to 1.

.

- 12 -

Preliminary W742E81A/W742C81A

When the SCR is set or reset, we must care the following cases:

1. X000B → X011B: we should not exchange the F
simultaneously. We could first exchange the F

OSC

oscillator. So it should be X000B→X001B→X011B.

2. X011B → X000B: we should not enable Fm and exchange the F
simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay subroutine
to wait the main-oscillator oscillating stably; then exchange the F
step. So it should be X011B→X001B→delay the Fm oscillating stably time→X000B. The

suggestion of the Fm oscillating stably time is 3.5 mS for 455 KHz and 0.8ms for 4 MHz.
We must remember that the X010B state is inhibitive, because it will induce the system shutdown.
The organization of the dual-clock operation mode is shown in Figure 6-4.

SCR.0

XIN1

XOUT1

SCR.1

enable/disable

Main Oscillator

STOP

Fm
Fs

Fosc

OSC

from Fm into Fs and disable Fm

from Fm into Fs, then disable the main-

OSC

from Fs into Fm

OSC

from Fs into Fm is the last

HOLD

T1

System Clock

Generator

T2
T3
T4

Divider 0

XIN2

XOUT2

Sub-Oscillator

Dual/Single Colck
Option code is 1/0

Fs or Fosc/128

SCR : System clock Control Register ( default = 00H )

Bit0Bit1Bit3

Daul clock operation mode :

- SCR.0=0, Fosc=Fm : SCR.0=1, Fosc=Fs

- Flcd=Fs, In STOP mode LCD work continue.

Figure 6-4 Organization of the dual-clock operation mode

LCD Frequency

Divider 1

0 : Fosc = Fm
1 : Fosc = Fs
0 : Fm enable
1 : Fm disable

0 : 14 bit
1 : 12 bit

Selector

SCR.3(14/12 bit)

Fosc/128

INT4
HCF.4

F

LCD

Publication Release Date: April 2000

- 13 - Revision A1

Preliminary W742E81A/W742C81A

S

RRR

R

S

6.11 WatchDog Timer (WDT) and WatchDog Timer Register(WDTR)

The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from
unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,
and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is

OSC

F

/2048. The input clock of the WDT can be switched to F
WDTR.3 to 1. The contents of the WDT can be reset by the instruction CLR WDT. In normal
operation, the application program must reset WDT before it overflows. A WDT overflow indicates
that operation is not under control and the chip will be reset. The WDT overflow period is 1 S when
the sub-system clock (Fs) is 32 KHz and WDT clock input is Fs/2048. When the corresponding option
code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0 and
watchdog timer is shown in Figure 6-5.

OSC

/16384 (or F

OSC

/2048) by setting

Fosc

Q1 Q2 Q9 Q10 Q11 Q12

Fosc/16384
Fosc/2048

Fss/16384
Fss/2048

Q1 Q2 Q9 Q10 Q11 Q12

Fss=Fs or Fosc/128

Divider0

...

WDTR.3

Divider1

...

Q13

Option code is "0"

WDTR.2

Option code is "1"

Q13

SCR.3

Q14

Disable

Enable

Q14

EVF.0

Q

R

WDT

Qw1 Qw2 Qw4Qw3

Q

R

EVF.4

HEF.0

IEF.0

1. Reset

2. CLR EVF,#01H

3. CLR DIVR0

Overflow signal

1. Reset

2. CLR WDT

HEF.4
IEF.4

Hold mode release
(HCF.0)

Divider interrupt (INT0)

System Reset

Hold mode release
(HCF.4)

Divider interrupt
(INT1)

1.

2. CLR EVF,#10H

3. CLR DIVR1

Figure 6-5 Organization of Divider0, Divider1 and WatchDog Timer

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