Winbond Electronics W741C260 Datasheet

W741C260

4-BIT MICROCONTROLLER

Table of Contents--

GENERAL DESCRIPTION.........................................................................................................................2

FEATURES.................................................................................................................................................2

PIN CONFIGURATION...............................................................................................................................3

PIN DESCRIPTION.....................................................................................................................................4

BLOCK DIAGRAM......................................................................................................................................5

FUNCTIONAL DESCRIPTION ...................................................................................................................6

ABSOLUTE MAXIMUM RATINGS.............................................................................................................34

DC CHARACTERISTICS............................................................................................................................35

AC CHARACTERISTICS............................................................................................................................36

PAD ASSIGMENT & POSITIONS..............................................................................................................37

TYPICAL APPLICATION CIRCUIT.............................................................................................................39

INSTRUCTION SET TABLE.......................................................................................................................40

PACKAGE DIMENSION.............................................................................................................................90

Publication Release Date: March 1998

- 1 - Revision A3

W741C260

GENERAL DESCRIPTION

The W741C260 is a high-performance 4-bit microcontroller (µC) with an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers, a 32 × 4 LCD driver, and five 4-bit I/O ports (including 1 output port to drive the LEDs). There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W741C260 has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation.

The W741C260 has two oscillator circuits and can work in dual-clock or single-clock operation mode. It is suitable for remote controllers, watches and clocks, speech synthesis LSI controllers, hand-held games and other products.

FEATURES

• Operating voltage: 2.2V to 5.5V (LCD drive voltage: 3.0V, or 4.5V)

• Operating frequency up to 4 MHz

• Crystal/RC oscillation circuit selectable by code option for system clock

• 32.768 KHz crystal oscillation circuit for sub-oscillator

• High-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32.768 KHz) for crystal mode;

selectable by code option

• Memory

− 2048 × 16 bit program ROM (including 2K × 4 bit look-up table)

− 128 × 4 bit data RAM (including 16 working registers)

− 32 × 4 LCD data RAM

• 21 input/output pins

− Ports for input only: 2 ports/8 pins

− Input/output ports: 2 ports/8 pins

− Port for output only: 1 port /4 pins (high sink current to drive LEDs)

− MFP output pin: 1 pin (MFP)

• Power-down mode

− Hold function: no operation (except for oscillator)

− Stop function: no operation (including main oscillator)

• Five types of interrupts

− Four internal interrupts (Divider 0, Divider 1, Timer 0, Timer 1)

− One external interrupt (Port RC)

• LCD driver output

− 32 segment × 4 common

− Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

− LCD driver output pins can be used as DC output ports; selectable by code option

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W741C260

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

• Two built-in 14-bit clock frequency divider circuit (divider 0 and divider 1)

• Two built-in 8-bit programmable countdown timers

− Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

− Timer 1: includes an auto-reload function; and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)

• Built-in 18/14-bit watchdog timer selectable for system reset

• Powerful instruction set: 118 instructions

• 8-level subroutine (include interrupt) nesting

• Up to 1 µS instruction cycle (with 4 MHz operating frequency)

• Packaged in 80-pin QFP

PIN CONFIGURATION

RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1

RD3 RE0

0 1

62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46

65 66 67 68 69 70 71 72 73 74 75 76 77RD2 78 79 80RE1

1 2 3 4 5 6 7 8 9

R R

NCN

E E

2 3

UTV

E S

NCN

M 3 2 1 0 0 1 2 3 4 5

X I

D N N

NCN

D C C

10 11 12 13 14 15 16 17 18 19

S S

X O

45 44 43 42 41

20 21 22 23 24

6 7 8 9 101

E G 3 1

S E G

G 3 2 2N 0 9 8

S E

E G

S EEGE G

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

N C

SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12

Publication Release Date: March 1998

- 3 - Revision A3

W741C260

RES

PIN DESCRIPTION

SYMBOL I/O FUNCTION

XIN1 I Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT1 O Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option. XIN2 I Input pin for sub-oscillator. Connected to a 32.768 KHz crystal. XOUT2 O Output pin for sub-oscillator. Connected to a 32.768 KHz crystal. RA0−RA3

RB0−RB3

RC0−RC3

RD0−RD3 RE0−RE3

MFP O

I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

I 4-bit port for input only.

Each pin has an independent interrupt capability.

I 4-bit port for input only.

O Output port only.

This port provides high sink current to drive LEDs.

Output pin only.

This pin can output modulating or nonmodulating frequency, or Timer 1

clock output specified by mode register 1 (MR1).

I System reset pin with pull-high resistor.

SEG0−SEG31

O LCD segment output pins.

Can also be used as DC output ports specified by code option. COM0−COM3

O LCD common signal output pins.

COM0 COM1 COM2 COM3

Static

Used Not Used Not Used Not Used

1/2 Duty

Used

Used Not Used Not Used

1/3 Duty

Used Used Used

Not Used

1/4 Duty

Used Used Used Used

The LCD alternating frequency can be selected by code option. DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor. VDD1, VDD2,

VDD3 I

Positive (+) supply voltage terminal.

Refer to Functional Description. VDD I Positive power supply (+). VSS I Negative power supply (-).

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BLOCK DIAGRAM

W741C260

(128 x 4)

(2048 x 16)

(look_up table

+1(+2)

(8 Levels)

RAM

ROM

2K x 4)

STACK

SEG0 to SEG31

ACC

ALU

Central Control

Unit

IEF

HCF

EVF

PSR0 PR MR1

. . .

COM0 to COM3

LCD DRIVER

PEFHEF

SEF

VDD1 to 3 DH1 to 2

PORT RA

PORT RB

PORT RC

PORT RD

PORT RE

SEL

MUX

RA0 to 3

RB0 to 3

RC0 to 3

RD0 to 3

RE0 to 3

MFP

Timer 0

(8-bit)

Watchdog Timer

(4-bit)

Timer 1

(8-bit)

Divider 0

(14-bit)

Modulation Frequency Pulse

XIN1 XOUT1

Timing Generator

Divider 1

(13/14-bit)

VDD VSS

RES

XIN2 XOUT2

Publication Release Date: March 1998

- 5 - Revision A3

W741C260

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip ROM containing the program instructions. When the jump or subroutine call instructions or the interrupt or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below.

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 000H INT 0 (Divider 0) 004H 1st INT 1 (Timer 0) 008H 2nd INT 2 (Port RC) 00CH 3rd INT 4 (Divider 1) 014H 4th INT 7 (Timer 1) 020H 5th JP Instruction XXXH Subroutine Call XXXH -

Stack Register (STACK)

The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048 × 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. There are two registers (TABL and TABH) to be used in look-up table addressing and they are controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is executed, the contents of the look-up table location address specified by TABH, TABL and ACC will be read and transfered to the data RAM. Refer to the instruction table for more details. The organization of the program memory is shown in Figure 1.

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000H

W741C260

16 bits

ACCTABLTABH

2048

address

600H

7FFH

- x x x x x x x x x y y

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

3 2 1 0

2048 x 16-bit

Figure 1. Program Memory Organization

This area can be used to store both instruction code and look-up table

Each element (4 bits) of the look-up table

Offset

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

00H

Working Register

0FH

128

address

7FH

128 x 4-bit

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section.

Publication Release Date: March 1998

- 7 - Revision A3

W741C260

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

PAGE

Note: R/W means read/write available.

Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:

000 = Page 0 (00H−0FH) 001 = Page 1 (10H−1FH) 010 = Page 2 (20H−2FH) 011 = Page 3 (30H−3FH) 100 = Page 4 (40H−4FH) 101 = Page 5 (50H−5FH) 110 = Page 6 (60H−6FH) 111 = Page 7 (70H−7FH)

R/WR/W R/W R/W

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. Otherwise CF can be stored or be read out by executing MOVA R, CF or MOV CF, R.

Clock Generator

The W741C260 provides two oscillation circuits, main-oscillator and sub-oscillator. The mainoscillator can select the crystal or RC oscillation circuit by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN1 and XOUT1, and a capacitor must be connected if an accurate frequency is needed. When the oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor must be connected to XIN1 and XOUT1, and the high/low frequency clock option must be selected to suit the operation frequency. The sub-oscillator must be connected to a 32.768 KHz crystal through XIN2 and XOUT2 external pins when the dual-clock operation mode is selected by option code. The connection is shown in Figure 3. One machine cycle consists of a four-state system clock sequence and can run up to 1 µS with a 4 MHz system clock.

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W741C260

XIN2

XOUT2

32 KHz or

400K to 4MHz

XIN1

Crystal Crystal

Figure 3. Oscillator Configuration

Resistor

32 KHz

XOUT1

Dual-clock operation

This operation mode is selected by code option. In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the single-clock mode, the clock source of the LCD frequency selector will be Fm or Fm/32 (Fm: main oscillator clock).

In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the system clock control register (SCR). If the SCR.0 is reset to 0, the clock source of the system clock generator is the main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is the sub-oscillator clock. In dual-clock mode, the main-oscillator can stop oscillating when SCR.1 is set to 1. But in the singleclock mode, the main-oscillator can not be stop from oscillating because the SCR would be disabled in single-clock mode. Therefore, in sigle-clock mode, the clock source of the system clock generator is the main-oscillator clock (FOSC = Fm).

When the SCR is set or reset, we must pay attention to the following:

1. X000B → X011B: Disable the main-oscillator (Fm) should not be done simultaneously with changing the system clock source (FOSC) from Fm to Fs. The FOSC should be changed first from Fm to Fs before the main-oscillator (Fm) is disabled. The correct seqence is: X000B→X001B→X011B.

2. X011B → X000B: Enabling the main-oscillator (Fm) should not be done simultaneously with changing the FOSC from Fs into Fm. The main-oscillator (Fm) should be enabled first before a delay subroutine is called to allow the main-oscillator to oscillate stably. The FOSC can now be changed from Fs into Fm. The correct sequence is therefore X011B→X001B→delay subroutine→X000B. The suggested delay for Fm is 20 mS for 455 KHz ceramic resonator and 10 mS for 4 MHz crystal.

We must remember that the X010B state is inhibitive, because it will induce a system shutdown. The organization of the dual-clock operation mode is shown below.

Publication Release Date: March 1998

- 9 - Revision A3

W741C260

XIN1

XOUT1

SCR.1

XIN2

XOUT2

Mask Option

(Single/Dual Clock)

Mask Option (High/Low Freq.)

SCR.0

Main Oscillator

enable/disable

Sub-oscillator

enable/disable

Figure 4. The Dual Clock Operation Mode Control Diagram

Fosc/32

Fosc

HOLD

System Clock

Generator

Divider 0

Mask Option (High/Low Freq.)

LCD Frequency

Selector

Mask Option (Single/Dual Clock)

Divider 1

SCR.3 (14/13 bit)

T2 T3 T4

INT4

HCF.4

LCD

Divider

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the main oscillator starts action, the divider0 is incremented by each clock (FOSC). When an overflow occurs, the divider0 event flag is set to 1 (EVF.0 = 1). The interrupt is executed if the divider0 interrupt enable flag has been set (IEF.0 = 1), and the hold state is terminated if the hold release enable flag has been set (HEF.0 = 1). The last 4-stage of the divider0 can be reset by executing a CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at each 500 mS interval.

If the sub-oscillator is enabled, the divider1 is incremented by each clock (Fs). When an overflow occurs, the divider1 event flag is set to 1 (EVF.4 = 1). The interrupt is executed if the divider1 interrupt enable flag has been set (IEF.4 = 1), and the hold state is terminated if the hold release enable flag has been set (HEF.4 = 1). There are two time periods (250 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; when SCR.3 = 1, the 250 mS period time is selected.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enabled when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, and the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

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W741C260

Fosc

Divider0

Q1 Q2 Q9 Q10 Q11 Q12

...

Fosc/16384 Fosc/1024

PMF.3

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

Q13

Enable /Disable

Q14

RRRR

EVF.0

WDT

Qw1 Qw2

R R R R

Qw3

HEF.0

IEF.0

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

Overflow signal

Qw4

1. Reset

2. CLR WDT

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

System Reset

Timer/Counter

1. Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5.

If the Timer 0 clock input is FOSC/4, then:

Desired Time 0 interval = (preset value +1) × 4 × 1/FOSC

If the Timer 0 clock input is FOSC/1024, then:

Desired Time 0 interval = (preset value +1) × 1024 × 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency

Publication Release Date: March 1998

- 11 - Revision A3

1. Reset

2. CLR EVF, #02H

3. Reset MR0.3 to 0

4. MOV TM0L, R or MOV TM0H, R

W741C260

MR0.0

Fosc/1024

Fosc/4

1. Set MR0.3 to 1

2. MOV TM0, #I

Disable

8-bit Binary

Down Counter

Enable

MOV TM0H, R

MOV TM0, #I

(Timer 0)

Figure 5. Organization of Timer 0

MOV TM0L, R

EVF.1

HEF.1 IEF.1

Hold mode release (HCF.1) Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF, #02H

3. Set MR0.3 to 1

4. MOV TM0, #I

2. Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into autoreload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then: Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency

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MOV TM1, #I

W741C260

(Timer 1)

Reset

MOV TM1L, R

8 bits

Underflow

signal

circuit

Reset

MFP signal

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

5. MOV TM1, #I

output pin

MR1.2

EVF.7

MFP

External clock

via RC.0

Fosc/64

Fosc

1. MR1.3 = 1

2. MOV TM1, #I

MR1.0

MR1.1

MOV TM1H, R

Enable

Disable

1. MR1.3 = 0

Auto-reload buffer

8-bit Binary

Down Counter

Set MR1.3 to 1

MOV TM1, #I

Figure 6. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.

3 4

Tone

frequency

C 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51 C# 138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96

T D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14

D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15

O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36

F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34

N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72

G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19

E G# 207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20

A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84 A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22 B 246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Note: Central tone is A4 (440 Hz).

Publication Release Date: March 1998

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W741C260

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows:

0123

MR0

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 0 is FOSC/4.

= 1 The internal fundamental frequency of Timer 0 is FOSC/1024. Bit 1 Reserved Bit 2 Reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.

W W

0123

WW W W

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin. Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

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W741C260

Interrupts

The W741C260 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 8. The control diagram is shown below.

Divider 0

overflow signal

Timer 0

underflow signal

Port RC

signal change

Divider 1

overflow signal

Timer 1

underflow signal

SRQ

MOV IEF, #I

EN INT

EVF.0

EVF.1

EVF.2

EVF.4

EVF.7

Initial Reset

IEF.0

IEF.1

IEF.2

IEF.4

IEF.7

Initial Reset CLR EVF, #I instruction

Disable

Interrupt Process

Circuit

Enable

Interrupt

Vector

Generator

DIS INT instruction

004H 008H 00CH 014H 020H

Figure 7. Interrupt Event Control Diagram

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. Therefore, to enable these interrupts, the instructions MOV IEF, #I or EN

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W741C260

INT must be executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows:

w w

123

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC. IEF.3 Reserved IEF.4 = 1 Interrupt 0 is accepted by overflow from the Divider 1. IEF.5 & IEF.6 are reserved. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

56 0

4 w

Stop Mode Operation

In stop mode, all operations of the µC cease (excluding the operation of sub-oscillator and divider 1 when the dual-clock operation mode is selected). The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC port). When the designated signal is accepted, the µC awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow the STOP command.

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

SEF w w w w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0. SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1. SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2. SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

012

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W741C260

Hold Mode Operation

In hold mode, all operations of the µC cease, except for the operation of the oscillator, timer, divider and LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1 or the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.

Divider 0, Divider 1,Timer 0

Timer1, Signal Change on

Port RC

In HOLD Mode?

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

HOLD

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

HEF

Flag Set?

(Note) (Note)

NoYes

YesNo

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

PC <- (PC+1)

NoNo

Figure 8. Hold Mode and Interrupt Operation Flow Chart

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Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows:

34567

HEF w w w w

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released. HEF.2 = 1 Signal change on port RC causes hold mode to be released. HEF.3 Reserved HEF.4 = 1 Overflow from the Divider 1 causes hold mode to be released. HEF.5 & HEF.6 are reserved. HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

012

Port Enable Flag (PEF)

The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

PEF w w w

Note: W means write only.

012 w

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF,#I (EVF.n = 0) or MOV HEF,#I (HEF.n = 0) instructions. When EVF or HEF have been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

012345

Note: R means read only.

R RHCF

R R R

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W741C260

HCF.0 = 1 Hold mode was released by overflow from the Divider0. HCF.1 = 1 Hold mode was released by underflow from the Timer 0. HCF.2 = 1 Hold mode was released by a signal change on port RC HCF.3 Reservsd HCF.4 = 1 Hold mode was released by overflow from the Divider 1. HCF.5 = 1 Hold mode was released by underflow from the Timer 1. HCF.6 & HCF.7 are reserved.

Event Flag (EVF)

The event flag is organized as an 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

EVF

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred. EVF.1 = 1 Underflow from Timer 0 occurred. EVF.2 = 1 Signal change on port RC occurred. EVF.3 Reserved EVF.4 = 1 Overflow from Divider 1 occurred. EVF.5 & EVF.6 are reserved. EVF.7 = 1 Underflow from Timer 1 occurred.

R R R

012345

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

0123

PMF

Note: W means write only.

Bit 0, Bit1, Bit2 Reserved Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.

= 1 The fundamental frequency of the watchdog timer is FOSC/16384.

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W741C260

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows:

PM0 w w w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type. Bit 2 = 0 RC port pull-high resistor is disabled.

= 1 RC port pull-high resistor is enabled.

Bit 3 = 0 RD port pull-high resistor is disabled.

= 1 RD port pull-high resistor is enabled.

012 w

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows:

PM1 w w w

Note: W means write only.

012 w

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows:

PM2 w w w

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin

012 w

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Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin

RES

Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin At initial reset, the port RB is input mode (PM2 = 1111B).

Reset Function

W741C260

The W741C260 is reset either by a power-on reset or by using the external of the W741C260 after the reset function is executed is described below.

Program Counter (PC) 000H TM0, TM1 Reset MR0, MR1, PM0, PAGE, PMF registers Reset PM1, PM2 registers Set (1111B) PSR0 register Reset IEF, HEF, PEF, SEF, HCF, EVF flags Reset Timer 0 input clock FOSC/4 Timer 1 input clock FOSC MFP output Low Input/output ports RA, RB Input mode Output port RE High RA & RB ports output type CMOS type RC & RD ports pull-high resistors Disable Input clock of the watchdog timer FOSC/1024 LCD display OFF Segment output mode LCD drive output

pin. The initial state

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W741C260

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. At initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 9.

Input/Output Pin of the RA(RB)

PM0.0 (or PM0.1)

Output

DATA

BUS

Buffer

Enable

MOV RA, R (or MOV RB, R) Instruction

PM1.n

(or PM2.n)

I/O PIN

RA.n(RB.n)

Enable

Figure 9. Architecture of Input/Output Pins

MOVA R, RA (or MOVA R, RB) instruction

Input Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) record the signal changing status on the port RC. PSR0 can be read out and cleared by the MOVA R, PSR0, and CLR PSR0 instructions. Refer to Figure 10 and the instruction table for more details. The RD port is used as input port only, it has no hold mode release or interrupt functions.

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W741C260

RC.0

RC.1

RC.2

RC.3

PM0.2

DATA BUS

Signal

change

detector

Signal

change

detector

Signal

change

detector

Signal

change

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

PEF.0

PEF.1

PEF.2

PEF.3

SEF.0

SEF.1

SEF.2

SEF.3

DckQ

PSR0.0

PSR0.1

PSR0.2

PSR0.3

DckQ

Reset

MOV PEF, #I

CLR PSR0

Wake up from STOP mode

EVF.2

CLR EVF, #I Reset

HEF.2

HCF.2

IEF.2

INT 2

Figure 10. Architecture of Input Ports RC

Output Port RE

When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE and it provides a high sink current to drive LEDs.

Port Status Register 0 (PSR0)

Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

0123

PSR0

Note: R means read only.

Bit 0 = 1 Signal change on RC.0 Bit 1 = 1 Signal change on RC.1 Bit 2 = 1 Signal change on RC.2 Bit 3 = 1 Signal change on RC.3

RR R R

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MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below:

(Fosc = 32.768 KHz)

R7 R6 R5 R4 R3 R2 R1 R0 FUNCTION

0 0 0 0 0 0 Low level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 0 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 High level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 1 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 2048 Hz 0 0 0 0 0 1 2048 Hz * 128 Hz 0 0 0 0 1 0 2048 Hz * 64 Hz

1 0 0 0 0 1 0 0 2048 Hz * 8 Hz

0 0 1 0 0 0 2048 Hz * 4 Hz 0 1 0 0 0 0 2048 Hz * 2 Hz 1 0 0 0 0 0 2048 Hz * 1 Hz 0 0 0 0 0 0 4096 Hz 0 0 0 0 0 1 4096 Hz * 128 Hz 0 0 0 0 1 0 4096 Hz * 64 Hz

1 1 0 0 0 1 0 0 4096 Hz * 8 Hz

0 0 1 0 0 0 4096 Hz * 4 Hz 0 1 0 0 0 0 4096 Hz * 2 Hz 1 0 0 0 0 0 4096 Hz * 1 Hz

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W741C260

LCD Controller/Driver

The W741C260 can directly drive an LCD with 32 segment output pins and 4 common output pins for a total of 32 × 4 dots. Option codes can be used to select one of five options for the LCD driving mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure

12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to segment 31) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in the figure below.

Fosc or Fosc/32

Mask Option

(Single/Dual Clock)

Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram

LCD Frequency Selection

Fw LCD Mode

Power Selection

DH1 DH2

Clock

Generator

Controller

Option Codes

Controller

LCD

CommomLCD Voltage

Driver

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

LCD Duty & Bias

Fw/64

Fw/128

LCD Drive Mode Selection

LCD

Waveform

Fw/256

Fw/512

Selector

LCD Data RAM

(32 x 4 bits)

Segment

Driver/Controller

Data Bus

LCD

MOV LCDM, #I Instruction

VDD VSS

VDD1 to 3

COM0 to 3

Figure 12. LCD Driver/Controller Circuit Diagram

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SEG0 to 31

W741C260

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY STATIC 1/2 DUTY 1/3 DUTY 1/4 DUTY

Fw/512 (64 Hz) 64 32 21 16 Fw/256 (128 Hz) 128 64 43 32 Fw/128 (256 Hz) 256 128 85 64 Fw/64 (512 Hz) 512 256 171 128

Corresponding to the 32 LCD drive output pins, there are 32 LCD data RAM segments (LCDR00 to LCDR1F). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR, ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 31 pins by a direct memory access. The relationship between the LCD data RAM and segment/common pins is shown below.

COM3 COM2 COM1 COM0

LCD data RAM Output pin bit 3 bit 2 bit 1 bit 0 LCDR00 SEG0 0/1 0/1 0/1 0/1 LCDR01 SEG1 0/1 0/1 0/1 0/1

. . .

LCDR1E SEG30 0/1 0/1 0/1 0/1 LCDR1F SEG31 0/1 0/1 0/1 0/1

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed. When the drive output pins are used as DC output ports (set by option codes, please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS output type can be selected by executing the instruction MOV LCDM, #I. The relation between the LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD data RAM segments can be used as normal data RAM to store data.

LCD DATA RAM OUTPUT PIN BIT 3 BIT 2 BIT 1 BIT 0

LCDR00 LCDR03−LCDR01

LCDR04

SEG3−SEG0

- - - - -

SEG7−SEG4

SEG3 SEG2 SEG1 SEG0

SEG7 SEG6 SEG5 SEG4

LCDR07−LCDR05

- - - - -

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W741C260

Continued

. . .

LCDR1C

SEG31−SEG28

LCDR1F−LCDR1D

The relationship between the LCD drive mode and the maximum number of drivable LCD segments is shown below.

. . .

SEG31 SEG30 SEG29 SEG28

- - - - -

. . .

LCD DRIVE MODE MAX. NUMBER OF

DRIVABLE LCD SEGMENT

CONNECTION AT

POWER INPUT

Static 32 (COM1) Connect VDD3, VDD2 to VDD1 1/2 Bias 1/2 Duty 1/2 Bias 1/3 Duty 1/3 Bias 1/3 Duty 1/3 Bias 1/4 Duty

64 (COM1−COM2) 96 (COM1−COM3) 96 (COM1−COM3) 128 (COM1−COM4)

Connect VDD3 to VDD2 Connect VDD3 to VDD2

LCD Output Mode Type Flag (LCDM)

The LCD output mode type flag is organized as an 8-bit binary register (LCDM.0 to LCDM.7). These bits are used to control the LCD output pins architecture. When LCD output pins are set to DC output mode by option codes, the architecture of these output pins (segment 0 to segment 31) can be selected as CMOS or NMOS type. It is controlled by the MOV LCDM, #I instruction. The bit descriptions are as follows:

7 6

LCDM

Note: W means write only.

5 0

w w

ww w w w

LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.

= 1 SEG0 to SEG3 work as NMOS output type.

LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.

= 1 SEG4 to SEG7 work as NMOS output type.

LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.

= 1 SEG8 to SEG11 work as NMOS output type.

LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.

= 1 SEG12 to SEG15 work as NMOS output type.

LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.

= 1 SEG16 to SEG19 work as NMOS output type.

LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.

= 1 SEG20 to SEG23 work as NMOS output type.

123

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LCDM.6 = 0 SEG24 to SEG27 work as CMOS output type.

= 1 SEG24 to SEG27 work as NMOS output type.

LCDM.7 = 0 SEG28 to SEG31 work as CMOS output type.

= 1 SEG28 to SEG31 work as NMOS output type.

The output waveforms for the five LCD driving modes are shown below.

Static Lighting System (Example)

Normal Operating Mode

W741C260

COM0

Unlit LCD driver

outputs

Lit LCD driver

outputs

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

COM0

COM1

LCD driver outputs for seg. on COM0, COM1 sides being unlit

VDD2 VDD1 VSS

LCD driver outputs for only seg. on COM0 side being lit

VDD2 VDD1 VSS

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