Winbond Electronics W741L250 Datasheet

W741L250

4-BIT MICROCONTROLLER

Table of Contents--

GENERAL DESCRIPTION..............................................................................................................................2

FEATURES......................................................................................................................................................2

PIN CONFIGURATION....................................................................................................................................3

PIN DESCRIPTION..........................................................................................................................................4

BLOCK DIAGRAM...........................................................................................................................................5

FUNCTIONAL DESCRIPTION ........................................................................................................................6

ABSOLUTE MAXIMUM RATINGS................................................................................................................31

DC CHARACTERISTICS...............................................................................................................................32

AC CHARACTERISTICS...............................................................................................................................33

PAD ASSIGNMENT & POSITIONS...............................................................................................................33

TYPICAL APPLICATION CIRCUIT................................................................................................................35

INSTRUCTION SET TABLE..........................................................................................................................36

PACKAGE DIMENSION................................................................................................................................84

Publication Release Date: March 1998

- 1 - Revision A2

W741L250

INT

GENERAL DESCRIPTION

The W741L250 is a high-performance 4-bit microcontroller (µC) that provides an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, a divider, a 24 × 4 LCD driver, and five 4-bit I/O ports (including 1 output port for high sink current). There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W741L250 operates on very low voltage and very low current and has two power reduction modes, hold mode and stop mode, which help to minimize power dissipation.

The W741L250 is suitable for handheld games, watches, clocks, speech synthesis LSI controllers, and other products.

FEATURES

• Operating voltage: 1.2V to 1.8V (LCD drive voltage: 3.0V or 4.5V)

• Operating frequency up to 1 MHz

• Crystal/RC oscillation circuit selectable by code option for system clock

• Only low-frequency clock (32.768 KHz) for crystal mode

• Memory

− 2048 × 16 bit program ROM (including 2K × 4 bit look-up table)

− 128 × 4 bit data RAM (including 16 working registers)

− 24 × 4 LCD data RAM

• 21 input/output pins

− Ports for input only: 2 ports/8 pins

− Input/output ports: 2 ports/8 pins

− Port for output only: 1 port /4 pins (high sink current)

− MFP output pin: 1 pin (MFP)

• Power-down mode

− Hold function: no operation (except for oscillator)

− Stop function: no operation (including oscillator)

• Five types of interrupts

− Three internal interrupts (Divider 0, Timer 0, Timer 1)

− Two external interrupts (Port RC and

• LCD driver output

pin)

− 24 segment × 4 common

− Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

− LCD driver output pins can be used as DC output port by code option

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W741L250

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

• Built-in 14-bit clock frequency divider circuit

• Two built-in 8-bit programmable countdown timers

− Timer 0: One of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

− Timer 1: Offers auto-reload function and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)

• Built-in 18/14-bit watchdog timer selectable for system reset

• Powerful instruction set: 116 instructions

• 8-level subroutine (include interrupt) nesting

• Up to 4 µS instruction cycle (with 1 MHz operating frequency)

• Packaged in 64-pin QFP

PIN CONFIGURATION

RA RA2

RA3 RB0

RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0

N T

0 1

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

52 53 54 55 56 57 58 59 60 61 62 63 64RD1

1 2 3 4 5 6 7 8 91011 12 13 14 15 16 17 18 19

R RR

DD E E

2 3 0 1

D N N

E S

D C C

NCNCC

G GEG

2 2 2 1

3 2 1 0 0 1 2 3 4 5

2 1 0 9

323

S S S

S EE E G

32 31 30 29 28 27 26 25 24 23 22 21 20

SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6

Publication Release Date: March 1998

- 3 - Revision A2

PIN DESCRIPTION

INT

RES

SYMBOL I/O FUNCTION

XIN I Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT O Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

RA0−RA3

RB0−RB3

RC0−RC3

RD0−RD3 RE0−RE3

MFP O

I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

I 4-bit port for input only.

Each pin has an independent interrupt capability.

I 4-bit port for input only.

O Output port only.

This port provides high sink current. Output pin only.

This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1).

I External interrupt pin with pull-high resistor.

W741L250

I System reset pin with pull-high resistor.

SEG0−SEG23

O LCD segment output pins.

Also can be used as DC output ports specified by code option.

COM0−COM3

O LCD common signal output pins.

COM0 COM1 COM2 COM3

Static

Used Not Used Not Used Not Used

1/2 Duty

Used

Used Not Used Not Used

1/3 Duty

Used Used Used

Not Used

1/4 Duty

Used Used Used Used

The LCD alternating frequency can be selected by code option.

DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor. VDD1,

VDD2, VDD3

Positive (+) supply voltage terminal.

Refer to Functional Description.

VDD I Positive power supply (+). VSS I Negative power supply (-).

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BLOCK DIAGRAM

W741L250

(look_up table 2K*4)

+1(+2)

(8 Levels)

RAM

(128*4)

ROM

(2048*16)

STACK

Timer 0

(8 Bit)

SEG0 to SEG23 COM0 to COM3

LCD DRIVER

ACC

ALU

Central Control

Unit

PEFHEFIEF

HCF

EVF SEF

PSR0

. .

Timer 1

(8 Bit)

MR1

Modulation Frequency Pulse

VDD1 to 3 DH1 to 2

PORT RA

PORT RB

PORT RD

PORT RC

PORT RE

SEL

MUX

RA0 to 3

RB0 to 3

RD0 to 3

RC0 to 3

RE0 to 3

MFP

Watchdog Timer

(4 Bit)

Divider 0

(14 Bit)

VDD VSS

Timing Generator

XIN XOUT

INT RES

Publication Release Date: March 1998

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W741L250

INT

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip ROM containing the program instruction words. When jump or subroutine call instructions or interrupt or initial reset conditions are to be executed, the address corresponding to the instruction will be loaded into the program counter. The format used is shown below.

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 000H INT 0 (Divider 0) 004H 1st INT 1 (Timer 0) 008H 2nd INT 2 (Port RC) 00CH 3rd INT 4 (

INT 7 (Timer 1) 020H 5th JP Instruction XXXH Subroutine Call XXXH -

pin) 014H 4th

Stack Register (STACK)

The stack register is organized as 11 bits × 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048 × 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements. There are two registers (TABL and TABH) to be used in look-up table addressing and they are controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is executed, the contents of the look-up table location address specified by TABH, TABL and ACC will be read and transfered to the data RAM. Refer to the instruction table for more details. The organization of the program memory is shown in Figure 1.

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000H

This area can be used to store both instruction code

W741L250

16 bits

ACCTABLTABH

2048

address

600H

7FFH

- x x x x x x x x x y y

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

3 2 1 0

2048 x 16-bit

Figure 1. Program Memory Organization

and look-up table

Each element (4 bits) of the look-up table

Offset

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

00H

Working Register

0FH

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next section.

128

address

7FH

128 x 4-bit

Figure 2. Data Memory Organization

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W741L250

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

PAGE

Note: R/W means read/write available.

Bit 3 is reserved. Bit 2, Bit 1, Bit 0 are indirect addressing mode preselect bits:

000 = Page 0 (00H−0FH) 001 = Page 1 (10H−1FH)

010 = Page 2 (20H−2FH) 011 = Page 3 (30H−3FH)

100 = Page 4 (40H−4FH) 101 = Page 5 (50H−5FH) 110 = Page 6 (60H−6FH) 111 = Page 7 (70H−7FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOVA R, CF.

R/W R/W R/W

Clock Generator

The W741L250 provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN and XOUT, and the capacitor must be connected if an accurate frequency is needed. When a crystal oscillator is used, only low-frequency clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is used, a resistor in the range of 28 KΩ to 1.6 MΩ must be connected to XIN and XOUT, as shown in Figure 3. The system clock frequency range is from 32 KHz to 2 MHz. One machine cycle consists of a four-phase system clock sequence and can run up to 4 µS with a 1 MHz system clock.

XIN

XOUT

32 KHz

Crystal

XIN

Resistor

XOUT

Figure 3. Oscillator Configuration

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W741L250

Divider 0

Divider 0 is organized as a 14-bit binary up-counter designed to generate periodic interrupts, as shown in Figure 4. When the system starts, the divider is incremented by each system clock (FOSC). When an overflow occurs, the divider event flag is set to 1 (EVF.0 = 1). Then, if the divider interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. In addition, the 4 MSB of the divider can be reset by executing the CLR DIVR0 instruction.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enable when the corresponding option code bit of the WDT is set to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset. The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

Divider0

Fosc

...

Q1 Q2 Q9 Q10 Q11 Q12

Fosc/16384 Fosc/1024

Q14

Q13

RRRR

PMF.3

Enable /Disable

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

EVF.0

WDT

Qw1 Qw2

R R R R

Qw3

HEF.0 IEF.0

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

Overflow signal

Qw4

1. Reset

2. CLR WDT

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

System Reset

Timer/Counter

1. Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L (TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting), the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1 has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting

Publication Release Date: March 1998

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W741L250

MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5.

If the Timer 0 clock input is FOSC/4:

Desired Timer 0 interval = (preset value +1) × 4 × 1/FOSC

If the Timer 0 clock input is FOSC/1024:

Desired Timer 0 interval = (preset value +1) × 1024 × 1/FOSC

Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency

1. Reset

2. CLR EVF, #02H

3. Reset MR0.3 to 0

4. MOV TM0L, R or MOV TM0H, R

MR0.0

Fosc/1024

Fosc/4

1. Set MR0.3 to 1

2. MOV TM0, #I

Disable

8-bit Binary

Down Counter

Enable

MOV TM0H, R

MOV TM0, #I

(Timer 0)

Figure 5. Organization of Timer 0

MOV TM0L, R

EVF.1

HEF.1 IEF.1

Hold mode release (HCF.1) Timer 0 interrupt (INT1)

1. Reset

2. CLR EVF, #02H

3. Set MR0.3 to 1

4. MOV TM0, #I

2. Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L, R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set (MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into autoreload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting.

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If the Timer 1 clock input is FT, then: Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value, and FOSC: Clock oscillation frequency

MOV TM1, #I

W741L250

(Timer 1)

Reset

MOV TM1L, R

8 bits

Underflow

signal

circuit

Reset

MFP signal

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

5. MOV TM1, #I

output pin

MR1.2

EVF.7

MFP

External clock

via RC.0

Fosc/64

Fosc

1. MR1.3 = 1

2. MOV TM1, #I

MR1.0

MR1.1

MOV TM1H, R

Enable

Disable

1. MR1.3 = 0

Auto-reload buffer

8-bit Binary

Down Counter

Set MR1.3 to 1

MOV TM1, #I

Figure 6. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below.

3 4 5

Tone

frequency

C 130.81 7CH 131.07 261.63 3EH 260.06 523.25 1EH 528.51 C# 138.59 75H 138.84 277.18 3AH 277.69 554.37 1CH 564.96

T D 146.83 6FH 146.28 293.66 37H 292.57 587.33 1BH 585.14

D# 155.56 68H 156.03 311.13 34H 309.13 622.25 19H 630.15

O E 164.81 62H 165.49 329.63 31H 327.68 659.26 18H 655.36

F 174.61 5DH 174.30 349.23 2EH 372.36 698.46 16H 712.34

N F# 185.00 58H 184.09 369.99 2BH 390.09 739.99 15H 744.72

G 196.00 53H 195.04 392.00 29H 420.10 783.99 14H 780.19

E G# 207.65 4EH 207.39 415.30 26H 443.81 830.61 13H 819.20

A 220.00 49H 221.40 440.00 24H 442.81 880.00 12H 862.84 A# 233.08 45H 234.05 466.16 22H 468.11 932.23 11H 910.22 B 246.94 41H 248.24 493.88 20H 496.48 987.77 10H 963.76

Note: Central tone is A4 (440 Hz).

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

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W741L250

INT

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows:

0123

MR0

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 0 is FOSC/4.

= 1 The internal fundamental frequency of Timer 0 is FOSC/1024. Bit 1 Reserved Bit 2 Reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows:

MR1

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.

W W

0123

WW W W

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.

Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

Interrupts

The W741L250 provides three internal interrupt sources (Divider 0, Timer 0, Timer 1) and two external interrupt sources (

the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF, #I instruction is invoked. The interrupts can also

, port RC). Vector addresses for each of the interrupts are located in

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W741L250

INT

be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and the interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the µC will enter hold mode again. The operation flow chart is shown in Figure 8. The control diagram is shown below.

Interrupt Event Control Diagram

Divider 0

overflow signal

Timer 0

underflow signal

Port RC

signal change

INT pin

falling edge signal

Timer 1

underflow signal

SRQ

MOV IEF, #I

EN INT

EVF.0

EVF.1

EVF.2

EVF.4

EVF.7

Initial Reset

IEF.0

IEF.1

IEF.2

IEF.4

IEF.7

Initial Reset CLR EVF, #I instruction

Disable

Enable

Interrupt Process

Circuit

Interrupt

Vector

Generator

DIS INT instruction

004H 008H 00CH 014H 020H

Figure 7. Interrupt Event Control Diagram

Stop Mode Operation

In stop mode, all operations of the µC cease (including the operation of the oscillator). The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is

activated (by a low level on the signal is accepted, the µC awakens and executes the next instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow the STOP command.

pin or a falling signal on the RC port). When the designated

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W741L250

INT

Hold Mode Operation

In hold mode, all operations of the µC cease, except for the operation of the oscillator, timer, and LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be

released in one of five ways: by the action of Timer 0, Timer 1, Divider 0, the Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.

Divider 0, Timer 0, Timer 1

INT, Signal Change on

Port RC

pin, or the RC port.

In HOLD Mode?

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

HOLD

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

HEF

Flag Set?

(Note) (Note)

NoYes

YesNo

Interrupt

Enable?

Yes

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Disable interrupt

PC <- (PC+1)

NoNo

Figure 8. Hold Mode and Interrupt Operation Flow Chart

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W741L250

INT

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows:

34567

HEF

Note: W means write only.

HEF.0 = 1 Overflow from Divider 0 causes hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released. HEF.2 = 1 Signal change at port RC causes hold mode to be released. HEF.3 Reserved

HEF.4 = 1 Falling edge signal at the HEF.5 & HEF.6 are reserved. HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

w w w w w

pin causes hold mode to be released.

012

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. Besides, these interrupts can be disable by executing DIS INT instruction. The bit descriptions are as follows:

123456 07

IEF

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC. IEF.3 Reserved

IEF.4 = 1 Interrupt 4 is accepted by a falling edge signal on the IEF.5 & IEF.6 are reserved. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

w w w ww

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pin.

Publication Release Date: March 1998

W741L250

Port Enable Flag (PEF)

The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or perform an interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

PEF w w w

Note: W means write only.

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

012

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

SEF w w w w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0. SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1. SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2. SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

012

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as an 8-bit binary register (HCF0 to HCF7). It indicates by which interrupt source the hold mode has been released, and it is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF, #I (EVF.n = 0) or MOV HEF, #I (HEF.n = 0) instructions. When EVF or HEF has been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

01234567

RHCF R R R

Note: R means read only.

- 16 -

HCF.0 = 1 Hold mode was released by overflow from Divider 0.

INT

HCF.1 = 1 Hold mode was released by underflow from Timer 0. HCF.2 = 1 Hold mode was released by a signal change on port RC. HCF.3 Reservsd

W741L250

HCF.4 = 1 Hold mode was released by a falling edge signal on the HCF.5 = 1 Hold mode was released by underflow from Timer 1. HCF.6 & HCF.7 are reserved.

pin.

Event Flag (EVF)

The event flag is organized as a 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset by the CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

EVF

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred. EVF.1 = 1 Underflow from Timer 0 occurred. EVF.2 = 1 Signal change on port RC occurred. EVF.3 Reserved

EVF.4 = 1 Falling edge signal on the EVF.5 & EVF.6 are reserved. EVF.7 = 1 Underflow from Timer 1 occurred.

R R R RR

pin occurred.

012345

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

0123

PMF

Note: W means write only.

Bit 0, Bit1, Bit2 Reserved Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.

= 1 The fundamental frequency of the watchdog timer is FOSC/16384.

Publication Release Date: March 1998

- 17 - Revision A2

W741L250

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows:

PM0 w w w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type. Bit 2 = 0 RC port pull-high resistor is disabled.

Bit 2 = 1 RC port pull-high resistor is enabled. Bit 3 = 0 RD port pull-high resistor is disabled.

Bit 3 = 1 RD port pull-high resistor is enabled.

012

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows:

PM1 w w w

012 w

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin. Bit 0 = 1 RA.0 works as input pin. Bit 1 = 0 RA.1 works as output pin. Bit 1 = 1 RA.1 works as input pin. Bit 2 = 0 RA.2 works as output pin. Bit 2 = 1 RA.2 works as input pin. Bit 3 = 0 RA.3 works as output pin. Bit 3 = 1 RA.3 works as input pin.

After initial reset, port RA is in input mode (PM1 = 1111B).

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W741L250

RES

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows:

PM2 w w w

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin. Bit 0 = 1 RB.0 works as input pin. Bit 1 = 0 RB.1 works as output pin. Bit 1 = 1 RB.1 works as input pin. Bit 2 = 0 RB.2 works as output pin. Bit 2 = 1 RB.2 works as input pin. Bit 3 = 0 RB.3 works as output pin. Bit 3 = 1 RB.3 works as input pin. After initial reset, port RB is in input mode (PM2 = 1111B).

012 w

Reset Function

The W741L250 is reset either by a power-on reset or by using the external of the W741L250 after the reset function is executed is described below.

Program Counter (PC) 000H TM0, TM1 Reset MR0, MR1, PM0, PAGE, PMF registers Reset PM1, PM2 registers Set (1111B) PSR0 register Reset IEF, HEF, HCF, PEF, EVF, SEF flags Reset Timer 0 input clock FOSC/4 Timer 1 input clock FOSC MFP output Low Input/output ports RA, RB Input mode Output port RE High RA & RB ports output type CMOS type RC & RD ports pull-high resistors Disabled Input clock of the watchdog timer FOSC/1024 LCD display OFF Segment output mode LCD drive output

pin. The initial state

Publication Release Date: March 1998

- 19 - Revision A2

External INT

INT

W741L250

The external interrupt falling edge of the the

pin will release the stop mode.

pin contains a pull-up resistor. When the HEF.4 or IEF.4 flag is set, the

pin will execute the hold mode release or interrupt subroutine. A low level on

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. After initial reset, input/output ports RA and RB are both in input mode. When RA and RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R operate the output functions. For more details, refer to the instruction table and Figure 9.

Input/Output Pin of the RA(RB)

PM0.0 (or PM0.1)

Output

DATA

BUS

Buffer

Enable

MOV RA, R (or MOV RB, R) Instruction

PM1.n (or PM2.n)

I/O PIN

RA.n(RB.n)

Enable

Figure 9. Architecture of Input/Output Pins

MOVA R, RA (or MOVA R, RB)

instruction

Input Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register (PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change on the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up the port. PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 10 and the instruction table for more details. The RD port is used as input port only, it has no hold mode release, wake-up stop mode or interrupt functions.

- 20 -

W741L250

RC.0

RC.1

RC.2

RC.3

PM0.2

DATA BUS

Signal

change

detector

Signal

change

detector

Signal

change

detector

Signal

change

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

Falling

edge

detector

PEF.0

PEF.1

PEF.2

PEF.3

SEF.0

SEF.1

SEF.2

SEF.3

DckQ

PSR0.0

PSR0.1

PSR0.2

PSR0.3

EVF.2

DckQ

CLR EVF, #I

Reset

Reset MOV PEF, #I CLR PSR0

Wake up from STOP mode

HEF.2

HCF.2

IEF.2

INT 2

Figure 10. Architecture of Input Ports RC

Output Port RE

When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE. Port RE (RE.0 to RE.3) also provides high sink current output.

Port Status Register 0 (PSR0)

Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

0123

PSR0

Note: R means read only.

Bit 0 = 1 Signal change on RC.0. Bit 1 = 1 Signal change on RC.1. Bit 2 = 1 Signal change on RC.2. Bit 3 = 1 Signal change on RC.3.

RR R R

Publication Release Date: March 1998

- 21 - Revision A2

W741L250

MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown as below:

(FOSC = 32.768 KHz)

R7 R6 R5 R4 R3 R2 R1 R0 FUNCTION

0 0 0 0 0 0 Low level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 0 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 High level 0 0 0 0 0 1 128 Hz 0 0 0 0 1 0 64 Hz

0 1 0 0 0 1 0 0 8 Hz

0 0 1 0 0 0 4 Hz 0 1 0 0 0 0 2 Hz 1 0 0 0 0 0 1 Hz 0 0 0 0 0 0 2048 Hz 0 0 0 0 0 1 2048 Hz * 128 Hz 0 0 0 0 1 0 2048 Hz * 64 Hz

1 0 0 0 0 1 0 0 2048 Hz * 8 Hz

0 0 1 0 0 0 2048 Hz * 4 Hz 0 1 0 0 0 0 2048 Hz * 2 Hz 1 0 0 0 0 0 2048 Hz * 1 Hz 0 0 0 0 0 0 4096 Hz 0 0 0 0 0 1 4096 Hz * 128 Hz

1 1 0 0 0 0 1 0 4096 Hz * 64 Hz

0 0 0 1 0 0 4096 Hz * 8 Hz 0 0 1 0 0 0 4096 Hz * 4 Hz 0 1 0 0 0 0 4096 Hz * 2 Hz 1 0 0 0 0 0 4096 Hz * 1 Hz

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W741L250

LCD Controller/Driver

The W741L250 can directly drive an LCD with 24 segment output pins and 4 common output pins for a total of 24 × 4 dots. Option codes can be used to select one of five options for the LCD driving mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure

12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to segment 23) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in the figure below.

Timing

Generator

Low frequency clock

LCD Frequency Selection

Fw LCD Mode

DH1 DH2

Clock

Generator

Controller

Fosc

Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram

DD1 to 3

Q1 Q2 Q3 Q4 Q5 Q6

High frequency clock

Option Codes

Controller

LCD

CommonLCD Voltage

Driver

COM0 to 3

Divider 0

Q14

...

Fosc/32

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

Fw/64

Fw/128

Fw/256

Fw/512

LCD Drive Mode Selection

LCD Duty & Bias

LCD

Waveform

Selector

Data Bus

LCD Data RAM

(24 x 4 bits)

Segment

Driver/Controller

SEG0 to 23

MOV LCDM, #I Instruction

LCD

Figure 12. LCD Driver/Controller Circuit Diagram

Publication Release Date: March 1998

- 23 - Revision A2

W741L250

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY STATIC 1/2 DUTY 1/3 DUTY 1/4 DUTY

Fw/512 (64 Hz) 64 32 21 16 Fw/256 (128 Hz) 128 64 43 32 Fw/128 (256 Hz) 256 128 85 64 Fw/64 (512 Hz) 512 256 171 128

Corresponding to the 24 LCD drive output pins, there are 24 LCD data RAM segments (LCDR00 to LCDR17). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR, ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," the LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 23 pins by a direct memory access. The relationship between the LCD data RAM and segment/common pins is shown below.

COM3 COM2 COM1 COM0

LCD data RAM Output pin bit 3 bit 2 bit 1 bit 0 LCDR00 SEG0 0/1 0/1 0/1 0/1 LCDR01 SEG1 0/1 0/1 0/1 0/1

. . .

LCDR16 SEG22 0/1 0/1 0/1 0/1 LCDR17 SEG23 0/1 0/1 0/1 0/1

. . .

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed. When the drive output pins are used as DC output ports (set by option codes, please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS output type can be selected by executing the instruction MOV LCDM, #I. The relation between the LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD data RAM segments can be used as normal data RAM to store data.

LCD DATA RAM OUTPUT PIN BIT 3 BIT 2 BIT 1 BIT 0

LCDR00 LCDR03−LCDR01

LCDR04 LCDR07−LCDR05

. . .

LCDR14 LCDR17−LCDR15

SEG3−SEG0

- - - - -

SEG7−SEG4

- - - - -

. . .

SEG23−SEG20

- - - - -

SEG3 SEG2 SEG1 SEG0

SEG7 SEG6 SEG5 SEG4

. . .

SEG23 SEG22 SEG21 SEG20

- 24 -

W741L250

The relationship between the LCD drive mode and the maximum number of drivable LCD segments is shown below.

LCD DRIVE MODE MAX. NUMBER OF

DRIVABLE LCD SEGMENTS

Static 24 (COM1) Connect VDD3, VDD2 to VDD1 1/2 bias 1/2 duty 1/2 bias 1/3 duty 1/3 bias 1/3 duty 1/3 bias 1/4 duty

48 (COM1−COM2) 72 (COM1−COM3) 72 (COM1−COM3) 96 (COM1−COM4)

CONNECTION AT

POWER INPUT

Connect VDD3 to VDD2 Connect VDD3 to VDD2

LCD Output Mode Type Flag (LCDM)

The LCD output mode type flag is organized as a 6-bit binary register (LCDM.0 to LCDM.5). These bits are used to control the LCD output pin architecture. When the LCD output pins are set to DC output mode by option codes, the architecture of these output pins (segment 0 to segment 23) can be selected as CMOS or NMOS type by the MOV LCDM, #I instruction. The bit descriptions are as follows:

5 0

LCDM

Note: W means write only.

LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.

= 1 SEG0 to SEG3 work as NMOS output type.

w w

123

ww w

LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.

= 1 SEG4 to SEG7 work as NMOS output type.

LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.

= 1 SEG8 to SEG11 work as NMOS output type.

LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.

= 1 SEG12 to SEG15 work as NMOS output type.

LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.

= 1 SEG16 to SEG19 work as NMOS output type.

LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.

= 1 SEG20 to SEG23 work as NMOS output type.

- 25 - Revision A2

Publication Release Date: March 1998

The output waveforms for the five LCD driving modes are shown below.

Static Lighting System (Example)

Normal Operating Mode

W741L250

COM0

Unlit LCD driver

outputs

Lit LCD driver

outputs

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

COM0

COM1

LCD driver outputs for seg. on COM0, COM1 sides being unlit

VDD2 VDD1 VSS

LCD driver outputs for only seg. on COM0 side being lit

LCD driver outputs for only seg. on COM1 side being lit

LCD driver outputs for seg. on COM0, COM1 sides being lit

VDD2 VDD1 VSS

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