Winbond Electronics W742C810 Datasheet

Preliminary W742C810

4-BIT MICROCONTROLLER

Table of Contents-

1. GENERAL DESCRIPTION..........................................................................................................................3

2. FEATURES..................................................................................................................................................3

3. PIN CONFIGURATION................................................................................................................................4

4. PIN DESCRIPTION......................................................................................................................................5

4.1 Pad List..................................................................................................................................................6

5. BLOCK DIAGRAM.......................................................................................................................................8

6. FUNCTIONAL DESCRIPTION ....................................................................................................................9

6.1 Program Counter (PC)...........................................................................................................................9

6.2 Stack Register (STACK)........................................................................................................................9

6.3 Program Memory (ROM).......................................................................................................................9

6.3.1 ROM Page Register (ROMPR)................................................................................................10

6.4 Data Memory (RAM)............................................................................................................................10

6.4.1 Architecture ..............................................................................................................................10

6.4.2 Page Register (PAGE).............................................................................................................11

6.4.3 WR Page Register (WRP).......................................................................................................12

6.4.4 Data Bank Register (DBKR).....................................................................................................12

6.5 Accumulator (ACC)..............................................................................................................................13

6.6 Arithmetic and Logic Unit (ALU)...........................................................................................................13

6.7 Main Oscillator......................................................................................................................................13

6.8 Sub-Oscillator.......................................................................................................................................13

6.9 Dividers................................................................................................................................................13

6.10 Dual-clock operation...........................................................................................................................14

6.11 Watchdog Timer (WDT).....................................................................................................................15

6.12 Timer/Counter....................................................................................................................................15

6.12.1 Timer 0 (TM0).........................................................................................................................15

6.12.2 Timer 1 (TM1).........................................................................................................................16

6.12.3 Mode Register 0 (MR0)..........................................................................................................17

6.12.4 Mode Register 1 (MR1)..........................................................................................................17

6.13 Interrupts............................................................................................................................................18

6.14 Stop Mode Operation.........................................................................................................................19

6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF).............................................................19

Publication Release Date: May 1999

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Preliminary W742C810

6.15 Hold Mode Operation.........................................................................................................................19

6.15.1 Hold Mode Release Enable Flag (HEF).................................................................................20

6.15.2 Interrupt Enable Flag (IEF) .....................................................................................................21

6.15.3 Port Enable Flag (PEF)..........................................................................................................21

6.15.4 Hold Mode Release Condition Flag (HCF).............................................................................22

6.15.5 Event Flag (EVF)....................................................................................................................22

6.16 Reset Function...................................................................................................................................23

6.17 Input/Output Ports RA, RB & RD .......................................................................................................23

6.17.1 Port Mode 0 Register (PM0)...................................................................................................24

6.17.2 Port Mode 1 Register (PM1)...................................................................................................24

6.17.3 Port Mode 2 Register (PM2)...................................................................................................25

6.17.4 Port Mode 5 Register (PM5)...................................................................................................25

6.18 Input Ports RC....................................................................................................................................25

6.18.1 Port Status Register 0 (PSR0) ...............................................................................................26

6.19 Output Port RE & RF .........................................................................................................................27

6.20 DTMF Output Pin (DTMF)..................................................................................................................27

6.20.1 DTMF register.........................................................................................................................28

6.20.2 Dual Tone Control Register (DTCR).......................................................................................28

6.21 MFP Output Pin (MFP).......................................................................................................................28

6.22 LCD Controller/Driver.........................................................................................................................30

6.22.1 LCD RAM addressing method................................................................................................31

6.22.2 The output waveforms for the LCD driving mode...................................................................31

7. ABSOLUTE MAXIMUM RATINGS............................................................................................................33

8. DC CHARACTERISTICS...........................................................................................................................33

9. AC CHARACTERISTICS...........................................................................................................................34

10. INSTRUCTION SET TABLE....................................................................................................................35

11. PACKAGE DIMENSIONS........................................................................................................................41

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Preliminary W742C810

1. GENERAL DESCRIPTION

The W742C810 is a high-performance 4-bit microcontroller (µC) that provides an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual-clock operation, a 40 × 4 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving), and one channel DTMF generator. There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W742C810 operates on very low current and has one power reduction mode, that is the dual-clock slow operation, which helps to minimize power dissipation.

2. FEATURES

• Operating voltage: 2.4V−3.6V

• Dual-clock operation

• Main oscillator

− Connect to 3.58 MHz crystal only

• Sub-oscillator

− Connect to 32768 Hz crystal only

• Memory

− 8192 x 16 bit program ROM (including 32K x 4 bit look-up table)

− 1024 x 4 bit data RAM (including 16 nibbles x 16 pages working registers)

− 40 x 4 LCD data RAM

• 24 input/output pins

− Port for input only: 1 ports/4 pins

− Input/output ports: 3 ports/12 pins

− High sink current output port for LED driving: 1 port /4 pins

− Port for output only: 1 port/ 4 pins

• Power-down mode

− Hold function: no operation (main oscillator and sub-oscillator still operate)

− Stop function: no operation (only main oscillator stops but sub-oscillator still operates)

− Dual-clock slow mode: system is operated by the sub-oscillator (FOSC = Fs and Fm is stopped)

• Five types of interrupts

− Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1)

− One external interrupt (RC Port)

• LCD driver output

− 40 segments x 4 commons

− 1/4 duty 1/3 bias driving mode

− Clock source should be the sub-oscillator clock in the dual-clock operation mode

• MFP output pin

− Output is software selectable as modulating or nonmodulating frequency

− Works as frequency output specified by Timer 1

Publication Release Date: May 1999

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Preliminary W742C810

CNCNCNC

• DTMF output pin

− Output is one channel Dual Tone Multi-frequency signal for dialling

• Two built-in 14-bit frequency dividers

− Divider0: the clock source is the output of the main oscillator

− Divider1: the clock source is the output of the sub-oscillator

• Two built-in 8-bit programmable countdown timers

− Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

− Timer 1: with auto-reload function, and one of three internal clock frequencies (FOSC, FOSC/64 or Fs) can be selected by MR1 register; the specified frequency can be delivered to MFP pin

• Built-in 18/15-bit watchdog timer selectable for system reset; enable the watch dog timer or not is

determined by code option

• Powerful instruction set: 131 instructions

• 8-level subroutine (include interrupt) nesting

3. PIN CONFIGURATION

NC MFP RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3

RD0 RD1 RD2 RD3 RE0

80 79 78 77 76 75 74 73 72 717069 68 67 666564 63 62

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

1 2 3

4 5 6 7 8 91011 12 13 14 15 16 17 18 19

N C

NCNCN

61 60 59 58 57

20 21 22 23 24

G 3 7

S E G 9

56 55 54 53 52

25 26 27 28

NCNCN

N C

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 SEG18 34 33 32 31

NC SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19

SEG17 SEG16 SEG15 SEG14

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Preliminary W742C810

RES

4. PIN DESCRIPTION

SYMBOL I/O FUNCTION

XIN2 I Input pin for sub-oscillator.

Connected to 32.768 Khz crystal only.

XOUT2 O Output pin for sub-oscillator with internal oscillation capacitor. Connected

to 32.768 Khz crystal only.

XIN1 I Input pin for main-oscillator.

Connected to 3.58MHz crystal to generate system clock.

XOUT1 O Output pin for main-oscillator.

Connected to 3.58MHz crystal to generate system clock.

RA0-RA3 I/O Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

RB0-RB3 I/O Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

RC0-RC3 I 4-bit port for input only.

Each pin has an independent interrupt capability.

RD0-RD3 I/O Input/Output port

Input/Output mode specified by port mode 5 register (PM5)

RE0-RE3 O Output port only. With high sink current capacity for the LED application.

RF0-RF3 O Output port only.

Output pin only.

MFP O

DTMF O This pin can output dual-tone multifrequency signal for dialling.

SEG0-

SEG39 COM0-

COM3

DH1, DH2 I Connection terminals for voltage doubler (halver) capacitor.

VDD1 VDD2 I

VDD I Positive power supply (+). VSS I Negative power supply (-).

O LCD segment output pins.

O LCD common signal output pins.

This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1).

I System reset pin with pull-high resistor.

Positive (+) supply voltage terminal. Refer to Functional Description.

Publication Release Date: May 1999

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Preliminary W742C810

4.1 Pad List

** Shrink factor: 1.000000; Date: 1997/12/31; Time: 14:46:10 ** Window: (xl = -1410.00, yl = -1595.00), (xh = 1410.00, yh = 1595.00) ** Windows size: width = 2820.00, length = 3190.00

PAD NO. PAD NAME PIN NAME X Y

1 RE1 5 -1302.45 1336.70 2 RE2 6 -1302.45 1205.53 3 RE3 7 -1302.45 1075.53 4 RF0 8 -1302.45 944.00 5 RF1 9 -1302.45 817.58 6 RF2 10 -1302.45 693.58 7 RF3 11 -1302.45 569.58 8 VSS 12 -1302.45 407.95

9 SEG<0> 13 -1302.45 283.95 10 SEG<1> 14 -1302.45 159.95 11 SEG<2> 15 -1302.45 35.95 12 SEG<3> 16 -1302.45 -88.05 13 SEG<4> 17 -1302.45 -212.05 14 SEG<5> 18 -1302.45 -336.05 15 SEG<6> 19 -1302.45 -460.05 16 SEG<7> 20 -1302.45 -584.05 17 SEG<8> 21 -1302.45 -708.05 18 SEG<9> 22 -1302.45 -832.05 19 SEG<10> 23 -1302.45 -956.38 20 SEG<11> 24 -1302.45 -1086.40 21 SEG<12> 25 -1302.45 -1216.40 22 SEG<13> 26 -1302.45 -1350.40 23 SEG<14> 31 -1302.45 -1486.30 24 SEG<15> 32 -1025.28 -1489.60 25 SEG<16> 33 -895.28 -1489.60 26 SEG<17> 34 -765.28 -1489.60 27 SEG<18> 35 -635.28 -1489.60 28 SEG<19> 36 -505.28 -1489.60 29 SEG<20> 37 -375.28 -1489.60 30 SEG<21> 38 -251.28 -1489.60

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Preliminary W742C810

Pad List, continued

PAD NO. PAD NAME PIN NAME X Y

31 SEG<22> 39 -127.28 -1489.60 32 SEG<23> 40 -3.28 -1489.60 33 SEG<24> 41 120.73 -1489.60 34 SEG<25> 42 244.73 -1489.60 35 SEG<26> 43 368.73 -1489.60 36 SEG<27> 44 498.73 -1489.60 37 SEG<28> 45 628.73 -1489.60 38 SEG<29> 46 758.73 -1489.60 39 SEG<30> 47 888.73 -1489.60 40 SEG<31> 48 1018.73 -1489.60 41 SEG<32> 49 1301.23 -1486.30 42 SEG<33> 55 1301.23 -1356.30 43 SEG<34> 56 1301.23 -1222.30 44 SEG<35> 57 1301.23 -1100.30 45 SEG<36> 58 1301.23 -970.30 46 SEG<37> 59 1301.23 -840.30 47 SEG<38> 60 1301.23 -716.30 48 SEG<39> 61 1301.23 -592.30 50 COM<2> 63 1301.23 -319.90 51 COM<1> 64 1301.23 -179.10 52 COM<0> 65 1301.23 -38.30 53 VDD2 66 1301.23 118.90 54 VDD1 67 1301.23 263.55 55 DH2 6 1301.23 411.73 56 DH1 69 1301.23 535.73 57 XOUT2 70 1301.23 659.73 58 XIN2 71 1301.23 783.73 59 VDD 72 1301.23 907.73 60 XOUT1 73 1301.23 1075.50 61 XIN1 74 1301.23 1205.50 62 DTMF 75 1301.23 1336.68 63 RES 76 1301.23 1466.70 64 MFP 82 1024.38 1470.00 65 RA0 83 894.38 1470.00

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Preliminary W742C810

Pad List, ontinued

PAD NO. PAD NAME PIN NAME X Y

66 RA1 84 764.38 1470.00 67 RA2 85 634.38 1470.00 68 RA3 86 504.38 1470.00 69 RB0 87 374.38 1470.00 70 RB1 88 250.38 1470.00 71 RB2 89 126.38 1470.00 72 RB3 90 2.38 1470.00 73 RC0 91 -121.63 1470.00 74 RC1 92 -245.63 1470.00 75 RC2 93 -369.63 1470.00 76 RC3 94 -499.63 1470.00 77 RD0 95 -629.63 1470.00 78 RD1 96 -759.63 1470.00 79 RD2 97 -889.63 1470.00 80 RD3 98 -1019.63 1470.00 81 RE0 99 -1302.45 1466.70

5. BLOCK DIAGRAM

RAM

(1024*4)

ROM

(8192*16)

(look_up table 32K*4)

+1(+2)

STACK (8 Levels)

Timer 0

(8 Bit)

Watch Dog Timer

(4 Bit)

SEG0~SEG39 COM0~COM4

LCD DRIVER

ACC

ALU

Central Control

Unit

PEFHEFIEF

HCF

EVF SEF

PSR0 SCR PR

MR0 MR1

PM0

. . .

Divider 0

(14 Bit)

Modulation Frequency Pulse

XIN2 XOUT2

Timer 1

(8 Bit)

VDD1~VDD2,DH1~2

PORT RA

PORT RB

PORT RC

PORT RD

PORT RE

PORT RF RF0-3

DTMF

Generator

SEL

MUL

Divider 1

(12/14 Bit)

Timing Generator

XIN1

XOUT1

RA0-3

RB0-3

RC0-3

RD0-3

RE0-3

DTMF

MFP

VDD VSS

RES

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Preliminary W742C810

6. FUNCTIONAL DESCRIPTION

6.1 Program Counter (PC)

Organized as a 13-bit binary counter (PC0 to PC12), the program counter generates the addresses of the 8192 × 16 on-chip ROM containing the program instruction words. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined first. The confirmation of the ROM page can be done by executing the MOV ROMPR, #I or MOV ROMPR, R instruction. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. The format used is shown below.

Table 1 Vector address and interrupt priority

ITEM ADDRESS INTERRUPT PRIORITY

Initial Reset 0000H INT 0 (Divider0) 0004H 1st INT 1 (Timer 0) 0008H 2nd INT 2 (Port RC) 000CH 3rd INT 3 (Divider1) 0014H 4th INT 4 (Timer 1) 0020H 5th JP Instruction XXXXH Subroutine Call XXXXH -

6.2 Stack Register (STACK)

The stack register is organized as 13 bits x 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.

6.3 Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 32768 ×4 bits. The program ROM is divided into four pages; the size of each page is 2048 × 16 bits. Total ROM size is therefore 8192 × 16 bits. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined first. The ROM page can be selected by executing the MOV ROMPR, #I or MOV ROMPR, R instruction. However, the branch decision instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump to the same ROM page which the branch decision instructions are located in. The whole ROM range can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 32768 elements. Instruction MOVC R is used to read the look-up table content and transfer table data to the RAM. But before reading the addressed look-up table content, the content of the look-up table pointer (TAB) must be determined first. The address of the look-up table element is allocated by the content of TAB. The MOV TAB0 (TAB1, TAB2, TAB3), R instructions are used to allocate the address of the wanted look-up table element. The TAB0 register stores the LSB 4 bits of the look-up table address. The organization of the program memory is shown in Figure 6-1.

Publication Release Date: May 1999

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1st page

2nd page

3rd page

4th page

0000H

03FFH 0400H

07FFH 0800H

0BFFH 0C00H

0FFFH 1000H

13FFH 1400H

17FFH 1800H

1BFFH 1C00H

1FFFH

16 bits

Look-up Table address:

0000H

0FFFH

Look-up Table address:

2000H

2FFFH

Look-up Table address:

3000H

3FFFH

Look-up Table address:

4000H

4FFFH

Look-up Table address:

5000H

5FFFH

Look-up Table address:

6000H

6FFFH

Look-up Table address:

7000H

7FFFH

8192 * 16 bits

Preliminary W742C810

Each element (4 bits) of the look-up table

Look-up Table address:

1000H

1FFFH

Figure 6-1 Program Memory Organization

6.3.1 ROM Page Register (ROMPR)

The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

ROMPR

Note: R/W means read/write available.

R/W

Bit 3 & Bit 2 is reserved. Bit 1, Bit 0 ROM page preselect bits:

00 = ROM page 0 (0000H - 07FFH) 01 = ROM page 1 (0800H - 0FFFH) 10 = ROM page 2 (1000H - 17FFH) 11 = ROM page 3 (1800H - 1FFFH)

6.4 Data Memory (RAM)

6.4.1 Architecture

The static data memory (RAM) used to store data is arranged as 1024 × 4 bits. The data RAM is divided into eight banks; each bank has 128 × 4 bits. Executing the MOV DBKR,WR or MOV DBKR,#I instruction can determine which data bank is used. The data memory can be addressed

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Preliminary W742C810

(or Working Registers bank)

directly or indirectly. However, the data bank must be confirmed first; the page in the data bank will be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be divided into eight pages. Before the data memory is addressed indirectly, the page which the data memory is located in must be confirmed. The organization of the data memory is shown in Figure 6-

4 bits

1st data bank

2nd data bank

: : :

8th data bank

1024 * 4 bits

Figure 6-2 Data Memory Organization

1st data RAM page

(or 1st WR page)

2nd data RAM page

(or 2nd WR page)

3rd data RAM page

(or 3rd WR page)

: :

8th data RAM page

(or 8th WR page)

00H 0FH

10H 1FH

20H 2FH

70H 7FH

1024

address

000H 07FH

080H 0FFH

380H 3FFH

The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the working registers (WR). This is also divided into sixteen pages. Each page contains 16 working registers. When one page is used as WR, the others can be used as the normal data memory. The WR page can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data memory cannot operate directly with immediate data, but the WR can do so. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next sub-section.

6.4.2 Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

Note: R/W means read/write available.

Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits in one data bank:

PAGE

000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH)

0123

R/W R/W R/W

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6.4.3 WR Page Register (WRP)

The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

WRP

Note: R/W means read/write available.

Bit 3, Bit 2, Bit 1, Bit 0 Working registers page preselect bits: 0000 = WR Page 0 (00H - 0FH)

0001 = WR Page 1 (10H - 1FH) 0010 = WR Page 2 (20H - 2FH) 0011 = WR Page 3 (30H - 3FH) 0100 = WR Page 4 (40H - 4FH) 0101 = WR Page 5 (50H - 5FH) 0110 = WR Page 6 (60H - 6FH) 0111 = WR Page 7 (70H - 7FH) 1000 = WR Page 8 (80H - 8FH) 1001 = WR Page 9 (90H - 9FH) 1010 = WR Page A (A0H - AFH) 1011 = WR Page B (B0H - BFH) 1100 = WR Page C (C0H - CFH) 1101 = WR Page D (D0H - DFH) 1110 = WR Page E (E0H - EFH) 1111 = WR Page F (F0H - FFH)

R/WR/W R/W R/W

6.4.4 Data Bank Register (DBKR)

The data bank register is organized as a 4-bit binary register. The bit descriptions are as follows:

0123

DBKR

Note: R/W means read/write available.

Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Data memory bank preselect bits:

000 = Data bank 0 (000H - 07FH) 001 = Data bank 1 (080H - 0FFH) 010 = Data bank 2 (100H - 17FH) 011 = Data bank 3 (180H - 1FFH) 100 = Data bank 4 (200H - 27FH) 101 = Data bank 5 (280H - 2FFH) 110 = Data bank 6 (300H - 37FH) 111 = Data bank 7 (380H - 3FFH)

R/W R/W R/W

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Preliminary W742C810

6.5 Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.

6.6 Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions:

• Logic operations: ANL, XRL, ORL

• Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

• Shift operations: SHRC, RRC, SHLC, RLC

• Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOV R, CF.

6.7 Main Oscillator

The W742C810 provides a crystal oscillation circuit to generate the system clock through external connections. The 3.58 MHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and VSS if an accurate frequency is needed.

XIN1

Crystal

3.58MHz

Figure 6-3 System clock oscillator Configuration

XOUT1

6.8 Sub-Oscillator

The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, only the 32768 Hz crystal can be connected to XIN2 and XOUT2, and a capacitor must be connected to XIN2 and VSS if an accurate frequency is needed. The sub-oscillator will be oscillatory continuously in STOP mode.

6.9 Dividers

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the main oscillator starts action, the Divider0 is incremented by each clock (FOSC). When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider0 can be reset by executing CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at the period of 500 mS.

If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. The last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. The same as with EVF.0, the EVF.4 is set to 1 periodically. However, there

Publication Release Date: May 1999

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