Winbond Electronics W6694CD Datasheet
Preliminary W6694
PASSIVE USB-ISDN S/T-CONTROLLER
W6694
USB Bus ISDN S/T-Controller
Data Sheet
The information described in this document is the exclusive intellectual property of Winbond
Electronics Corp and shall not be reproduced without permission from Winbond.
Winbond is providing this document only for reference purposes for W6694-based system design.
Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to
change without notice.
Publication Release Date: October 2000
- 1 - Revision A1
Preliminary W6694
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................4
2. FEATURES ...................................................................................................................................4
ISDN..............................................................................................................................................4
USB...............................................................................................................................................4
Other Features ............................................................................................................................... 4
3. PIN CONFIGURATION..................................................................................................................5
4. PIN DESCRIPTION .......................................................................................................................6
5. SYSTEM DIAGRAM AND APPLICATIONS ................................................................................... 8
6. BLOCK DIAGRAM ........................................................................................................................9
7. FUNCTIONAL DESCRIPTIONS ....................................................................................................9
7.1 USB Descriptions.....................................................................................................................9
7.1.1 Control-IN Transactions (Endpoint 0) ............................................................................ 10
7.1.2 Control-OUT Transactions (Endpoint 0) ........................................................................ 13
7.1.3 Bulk-OUT Transaction (Endpoint 1)..............................................................................13
7.1.4 Bulk-IN Transaction (Endpoint 2)..................................................................................14
7.1.5 Interrupt-IN Transaction (Endpoint 3)............................................................................14
7.1.6 Isochronous-OUT Transaction (Endpoint 4).................................................................. 14
7.1.7 Isochronous-IN Transaction (Endpoint 5)......................................................................16
7.1.8 Suspend and Resume ..................................................................................................17
7.2 Configuration EEPROM ......................................................................................................... 17
8. REGISTER DESCRIPTIONS.......................................................................................................18
8.1 Interrupt Registers..................................................................................................................18
8.1.1 Interrupt Status Register ISTA Read_clear...............................................................18
8.1.2 Layer 1 Command/Indication Register CIR Read .......................................................18
8.1.3 Monitor Channel Interrupt Status MOIR Read_clear ................................................. 19
8.1.4 PIO Input Change Register PICR Read_clear..........................................................19
8.2 Chip and FIFO Control Registers............................................................................................ 19
8.2.1 Interrupt Mask Register IMASK Read/Write Address 00h.......................................... 19
8.2.2 Command Register 1 CMDR1 Write Address 01h....................................................20
8.2.3 Command Register 2 CMDR2 Write Address 02h.................................................... 21
8.2.4 Control Register CTL Read/Write Address 03h......................................................21
8.2.5 Layer 1 Command/Indication Register CIX Read/Write Address 04h ......................... 22
8.2.6 U-layer1 Ready Code L1_RC Read/Write Address 05h.............................................22
8.3 GCI Mode Registers...............................................................................................................22
8.3.1 GCI Mode Command Register GCR Read/Write Address 06h.................................22
8.3.2 Monitor Channel Control Register MOCR Read/Write Address 07h........................... 23
8.3.3 Monitor Channel Receive Register MOR Read Address 08h ....................................24
- 2 -
Preliminary W6694
8.3.4 Monitor Channel Transmit Register MOX Read/Write Address 09h...........................24
8.4 Programmable IO Registers................................................................................................... 24
8.4.1 PIO Input Enable Register PIE Read/Write Address 0Ah .........................................24
8.4.2 PIO Output Register 1 PO1 Read/Write Address 0Bh.............................................24
8.4.3 PIO Output Register 2 PO2 Read/Write Address 0Ch.............................................25
8.4.4 PIO Data Register PDATA Read Address 0Dh........................................................ 25
8.5 B Channel Switch Registers ................................................................................................... 25
8.5.1 Layer1 B1 Receiver Select Register L1B1RS Read/Write Address 0Eh...................... 25
8.5.2 Layer1 B2 Receiver Select Register L1B2RS Read/Write Address 0Fh ...................... 26
8.5.3 USB B1 Receiver Select Register USBB1RS Read/Write Address 10h...................... 26
8.5.4 USB B2 Receiver Select Register USBB2RS Read/Write Address 11h...................... 26
8.5.5 PCM1 Receiver Select Register PCM1RS Read/Write Address 12h..........................26
8.5.6 PCM2 Receiver Select Register PCM2RS Read/Write Address 13h..........................27
9. ELECTRICAL CHARACTERISTICS............................................................................................ 27
9.1 Absolute Maximum Rating ..................................................................................................... 27
9.2 Power Supply......................................................................................................................... 28
9.3 DC Characteristics ................................................................................................................. 28
9.4 Preliminary Switching Characteristics.....................................................................................30
9.4.1 PCM Interface Timing...................................................................................................30
9.4.2 Serial EEPROM Timing ................................................................................................ 31
10. ORDERING INFORMATION ...................................................................................................... 32
11. PACKAGE INFORMATION ...................................................................................................... 33
48L LQFP (7 x 7 x 1.4 mm footprint 2.0 mm)............................................................................... 33
Publication Release Date: October 2000
- 3 - Revision A1
Preliminary W6694
1. GENERAL DESCRIPTION
The Winbond's single chip USB bus ISDN S/T interface controller W6694 is an all-in-one device
suitable for ISDN Internet access. The integrated USB and ISDN design provides low cost, pure
passive solution for USB-IDSN application.
W6694 also provides two PCM CODEC interfaces for the ability to access ISDN through voice
channel.
2. FEATURES
ISDN
•
Full duplex 2B+D S/T-interface transceiver compatible with ITU-T I.430 Recommendation
− Four wire operation
− Received clock recovery
− Layer 1 activation/deactivation procedure
− D channel access control
•
Transparent data transmission of 2B+D channels
•
Test functions
USB
•
USB Specification version 1.0/1.1 compliant
•
Full-speed, bus-powered USB device
•
Integrated transceiver, PLL, SIE, SIL and voltage regulator
•
Built-in fully automatic enumeration procedure
•
Support suspend mode
− Suspend current requirement
− Wake-up by ISDN (remote) and PC (host)
Other Features
• GCI bus interface (slave mode) for connecting to ISDN U transceiver chip.
•
PCM port provides two 64K clear channels to connect to PCM CODEC chips.
•
B channel data switching function for selective connection between ISDN/GCI interface, USB and
PCM.
•
EEPROM interface for retrieving customized USB device identification data.
•
IO pins with LED current drive capability.
• Reset pin for whole-chip reset.
- 4 -
3. PIN CONFIGURATION
V
S
N
S
C
U
36 35 34 33 32 31 30 29 28 27 26 25
VDDU
D+
D-
VDD3
UCLK1
UCLK2
VDD3I
VSS1
SR1
SR2
VDD1
SX1
37
38
39
40
41
42
43
44
45
46
47
48
1 2
Preliminary W6694
I
I
I
I
I
S
O
O
O
U
P
S
P
3
P
7
6
5 6
4
O
P
P
4
5
7
I
I
O
O
P
P
2
3
8
9
I
O
O
P
P
1
0
10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
VDD23
VSS23
TEST2
TEST1
EPDO
EPDI
EPSK
EPCS
PRXD
PTXD
VDD22
VSS22
G
G
G
S
X
2
X
X
T
T
A
A
L
L
2
1
V
V
D
S
D
S
2
2
1
1
C
C
I
I
D
F
C
S
C
L
G
C
C
I
I
D
D
D
U
P
P
F
C
K
1
P
F
B
C
C
K
K
2
FIG.3.1 W6694 Pin Out
Publication Release Date: October 2000
- 5 - Revision A1
Preliminary W6694
4. PIN DESCRIPTION
Table 4.1 W6694 Pin Descriptions
SYMBOL PIN NO. I/O FUNCTION
USB Bus
D+ 38 I/O USB D+ data line.
D- 39 I/O USB D- data line.
UCLK1 41 I 24 MHz crystal/oscillator clock input.
UCLK2 42 O 24 MHz crystal clock output. Left unconnected if use
oscillator.
ISDN Signals and External Crystal
SR1 45 I S/T bus receiver input (-). This is normal polarity. Reverse
polarity is also OK.
SR2 46 I S/T bus receiver input (+).
SX1 48 O S/T bus transmitter output(+).
SX2 1 O S/T bus transmitter output(-).
XTAL1 2 I Crystal or Oscillator clock input. The clock frequency: 7.68
MHz ±100 PPM.
XTAL2 3 O Crystal clock output. Left unconnected when using
oscillator.
GCI Bus
GCIDCL 6 I GCI bus data clock 1.536 MHz.
GCIFSC 7 I GCI bus frame synchronization clock.
GCIDD 8 I GCI bus data downstream. (input)
GCIDU 9 O GCI bus data upstream. (output)
PCM Bus
PFCK1 10 O PCM port 1 frame synchronization signal with 8 KHz
repetition rate and 8 bit pulse width
PFCK2 11 O PCM port 2 frame synchronization signal with 8 KHz
repetition rate and 8 bit pulse width
PBCK 12 O PCM bit clock of 1.536 MHz.
PTXD 15 O PCM data output.
PRXD 16 I PCM data input.
- 6 -
Preliminary W6694
4. Pin Description, continued
SYMBOL PIN NO. I/O FUNCTION
External Serial EEPROM Interface
EPCS 17 O Serial EEPROM chip select.
EPSK 18 O Serial EEPROM data clock.
EPDI 19 I Serial EEPROM data input
EPDO 20 O Serial EEPROM data output
Power and Ground
VDD1,VSS1 47, 44 I ISDN S/T analog power (5V), Ground
VDD21, VSS21
VDD22, VSS22
VDD23, VSS23
VDDU, VSSU 37, 36 I USB core power (5V), Ground
VDD3 40 O Regulator output (3.3V)
VDD3I 43 I Regulator input (3.3V)
5, 4
14, 13
24, 23
I Digital power (5V), Ground
IO Pins
IOP0
IOP1
IOP2
IOP3
IOP4
IOP5
IOP6
IOP7
Others
RESET
TEST1, TEST2
SUSP 34 O USB suspended. Active HIGH
NC 35 No connection. Internal pull-up is provided.
26
27
28
29
30
31
32
33
25 I External reset. Cause internal circuit reset. Internal 10k
21, 22 I Test mode enable. Connected to HIGH for normal
I/O
IO pin capable of driving LED.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ohm pull-up is provided.
operation.
NC
Publication Release Date: October 2000
- 7 - Revision A1
5. SYSTEM DIAGRAM AND APPLICATIONS
Typical applications include:
§ USB passive TA for data only service
§ USB passive TA with one data plus one voice
VDD
ATACH1
SW DPDT
JP2
1
2
3
4
HEADER 4
VDD
12
12
CB1
+
1uF
CB2
0.1uF
3
1
4
3.3V
2
6
5
12
12
CB3
0.1uF
R5
1.5K
CB5
CB4
0.1uF
0.1uF
3.3V
VDD
USBDP
USBDN
3.3V
24MXI
USBDN
USBDP
24MXO
+
GND
SR1
SR2
VDD
SX1
C6
22UF
R4
22
R6
22
U1
37
VDDU
38
D+
39
D-
40
VDD3
41
UCLK1
42
UCLK2
43
VDD3I
44
VSS1
45
SR1
46
SR2
47
VDD1
48
SX1
J1
JP1
1
IOP4
IOP5
IOP6
IOP7
GND
SUSPEND
IOP3
NC
IOP3
IOP4
IOP5
IOP6
IOP7
VSSU
SUSPEND
SX2
XTAL1
XTAL2
VSS21
VDD21
GCIDCL
GCIFSC
GCIDD
GCIDU
1234567891011
SX2
GND
VDD
768MXO
VDD
768MXI
GND
GND
IOP2
IOP2
PFCK1
IOP1
IOP0
2627282930313233343536
IOP0
IOP1
PFCK2
PBCK
12
RESET1
TR_RST
B_GND
BUS_P
USB1
C
5
2
1
DD+
USBCONN
1
2
3
4
1N4148
D1
R1
10K
RESETN
C3
+
1uF
VDD
USB_PUSB_P+
GND
RESETN
25
VDD
24
VDD23
GND
23
RESET#
VSS23
VDD
22
TEST2#
VDD
21
TEST1#
EPDO
20
EPDO
EPDI
19
EPDI
EPSK
18
EPSK
EPCS
17
EPCS
VDD
16
PRXD
15
PTXD
VDD
14
VDD22
GND
13
VSS22
W6694-QFP48
EPCS VDD
EPSK
EPDO
EPDI GND
Preliminary W6694
24MXI
R2
24MXO
150
768MXI
R3
768MXO
220
IOP0
D2
LED
U2
1
8
CS
VCC
2
7
SK
NC
3
DI
NC
4 5
DO GND
NMC9346
DIP8
6
R15
560
C1
10pF
1 2
Y1
24MHz
1 2
1 2
GND
C2
10pF
C4
33pF
1 2
Y2
7.68MHz
1 2
1 2
GND
C5
33pF
IOP1
IOP2
IOP3
IOP4
IOP5
IOP6
D3
D4
D5
LED
LED
LED
R16
R17
R18
560
R19
560
560
560
IOP7
D9
LEDD8LEDD7LEDD6LED
R20
R21
R22
560
560
560
R7
SX1
18
D10
D11
1N4148
1N4148
D12
1N4148
D16
D17
1N4148
1N4148
R9
SX2
18
R10
SR1 SR1A
1.8K
D18
D19
1N4148
1N4148
1N4148
VDD
D20
D21
1N4148
GND
R13
SR2 SR2A
1.8K
D13
1N4148
FB1
SX1C
SX1A
D15
1N4148
VDD
VDD
SX2A
D14
1N4148
R11
8.2K
VDD
R14
8.2K
U3
SX1C
1
1
2
2
3
3
4
4
SR1C
5
5
6
6
SR1A
8
8
SX1A
9 10
9 10
UT28615
SX2C
18
18
17
17
16
16
15
15
SR2C
14
14
13
13
SR2A
11
11
SX2A
Fig. 5.1 USB Passive TA Orcad Schematic
1 2
FERRI BEAD
JP3
JUMPER
1 2
R8
100
FB2
FERRI BEAD
SX2C
1 2
FB3
SR1C
1 2
FERRI BEAD
JP4
JUMPER
1 2
R12
100
FB4
SR2C
1 2
FERRI BEAD
ISDN1
1
2
3
4
5
6
7
8
ISDN CONNECTOR
15.20X12.00
W6694 WITH USB & ISDN INTERFACE
Monday, May 29, 2000
Size Document Number
Date: Sheet of
W6694 DEMO BOARD-DATA ONLY
D:\..\W6694_DEMO\W6694_DEMO.DSN\W6694.SCH
1
1
- 8 -
6. BLOCK DIAGRAM
Interface
B
B
B
Bus
Preliminary W6694
S/T
Interface
GCI
PCM
Codec
Interface
GCI
Control
PCM
Port
Control
Serial
Interfac
FIG 6.1 W6694 Block Diagram
7. FUNCTIONAL DESCRIPTIONS
7.1 USB Descriptions
TAble 7.1 W6694 all USB Endpoints
e
Buffer
B
Channel
Switch
EEPROM
Control
IO Port
Control
USB
Bus
Serial
EEPROM
IO Port
END
POINT
0 Control
1 Bulk OUT 8 8, single port x 1
2 Bulk IN 8 8, single port x 1
3 Interrupt
4 Isoch. OUT (1+3) +
5 Isoch. IN 1+ (1+7) + (1+15) +
* Direction: IN – device to host, OUT – host to device
- 9 - Revision A1
TYPE DIRECTION* MAX. PACKET SIZE
(BYTES)
IN/OUT 8/8 8, single port x 2
IN 5 5, single port x 1
(1+18) = 23
(1+15) = 41
Publication Release Date: October 2000
INTERNAL BUFFER TYPE AND
SIZE
(BYTES)
96, dual port x 1
96, dual port x 1
Preliminary W6694
USB standard requests are supported by W6694, and W6694 will respond to requests according to
USB specification revesion 1.1. These includes “CLEAR_FEATURE, GET_CONFIGURATION,
GET_DESCRIPTOR, GET_INTERFACE, GET_STATUS, SET_ADDRESS, SET_CONFIGURATION,
SET_DESCRIPTOR, SET_FEATURE, SET_INTERFACE”. The “SYNC_FRAME” request is not
supported.
7.1.1 Control-IN Transactions (Endpoint 0)
7.1.1.1 Get Device Descriptor
OFFSET
0 bLength 1 12
1 bDescriptorType 1 01
2 bcdUSB 2 0110
4 bDeviceClass 1 FF
5 bDeviceSubClass 1 00
6 bDeviceProtocol 1 00
7 bMaxPacketSize 1 08
8 idVendor 2 1046 Yes *
10 idProduct 2 6694 Yes *
12 bcdDevice 2 0100 Yes *
14 iManufacturer 1 00
15 iProduct 1 01
16 iSerialNumber 1 00
17 bNumConfiguration 1 01
Refer to EEPROM session for its layout of contents.
* Note:
7.1.1.2 Get Configuration Descriptor
OFFSET
0 bLength 1 09
1 bDescriptorType 1 02
2 wTotalLength 2 003E 62
4 bNumInterface 1 01
5 bConfigurationValue 1 01
6 iConfiguration 1 00
7 bmAttributes 1 A0 Bus Powered,
8 MaxPower 1 32 100 mA
FIELD SIZE
FIELD SIZE
Configuration Descriptor
DEFAULT VALUE
(HEX)
VALUE (HEX) REMARK
UPDATED BY EEPROM
Remote Wakeup
- 10 -
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