Winbond Electronics W51300 Datasheet

W51300

FLASH VR CONTROLLER

GENERAL DESCRIPTION

The W51300 is a voice recorder IC which contains A/D and D/A converters to digitize and reproduce voice signals. An anti-alias/smoothing filter, AGC circuit, MIC preamplifier, and speaker power amplifier are used to smooth the input voice and set the output voice to a certain volume while minimizing the number of extra components needed. The recording time depends on the size of the external memory.

The external memory is a nonvolatile flash EPROM that stores the voice data while power is switched off. This external memory provides a great advantage in cartridge or greeting card applications. A maximum of 16 Mbit of memory can be cascaded. In addition, the W51300's flexible segmentation, selective recording/erasing, forward and backward move functions, and MCU interface provide flexibility to meet the needs of a wide variety of applications.

FEATURES

• Modified ADM algorithm with 24 KHz sampling frequency when ROSC = 620 KΩ

• Operates with Winbond serial flash EPROM

• Built-in A/D, D/A, MIC preamplifier, AGC circuit, anti-alias/smoothing filter, speaker power amplifier,

and LED indicator

• 8 input trigger pins (L_REC, E_PLAY, L_PLAY, FWD, BWD, STOP, ERASE, RESET) debounced

to ensure noise-free operations

• Single/multi-voice segment operation, normal/CPU mode selected by pin option (SMODE, CPU)

• Cascadable for longer duration by directly cascading serial flash EPROMs (maximum 16 Mbits)

• Maximum 63 voice segments available in multi-segment operation

• Provides selective record, erase, and playback functions

• Provides low power detection circuit at 3.0V

• Provides both speaker direct drive and speaker current output (5 mA)

• Low power consumption:

− Operating: 15 mA (typ.)

− Standby: 0.01 µA (typ.)

Publication Release Date: April 1997

- 1 - Revision A2

PIN CONFIGURATION

W51300

BWD

STOP

EOP

CLK

ADDR

DATA

CTRL

MODE

BUSY

LED VSSD VSSA

SPK-

SPK+

VCCA

AUD

10 11

12 13

2 3 4 5 6 7 8 9

14 15

31 30

29 28 27 26 25 24 23 22 21 20

19 18 17

FWD

ERASE

E_PLAY L_PLAY L_REC

RESET EXTCLK TEST SMODE CPU VCCD AGC MIC MICREF

OSC

VCCA

PIN DESCRIPTION

NO. PIN I/O DESCRIPTION

1 BWD I/O Message backward control pin in normal mode

Output clock signal (to MCU) in CPU mode

2 STOP I Stop playback control pin in normal mode

Input clock signal (from MCU) in CPU mode 3 EOP I End of page process signal (from flash EPROM) 4 CLK O Data clock pin for flash EPROM 5 ADDR O Address clock pin for flash EPROM 6 DATA I/O Bidirectional data pin for flash EPROM 7 CTRL O Control signal for flash EPROM 8 MODE O Mode control pin for flash EPROM

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Pin Description, continued

NO. PIN I/O DESCRIPTION

9 BUSY O Output busy signal, HIGH during playback

10 LED O Blink (Flash (volume-controlled) during playback

Flash Blink (3 Hz) when during low battery is low, segment full, or memory full

ON during recording, erasing, and memory formatting 11 VSSD - Digital negative power supply 12 VSSA - Analog negative power supply 13 SPK- O Speaker voltage output 14 SPK+ O Speaker voltage output + 15 VCCA - Analog positive power supply 16 AUD O Speaker current output (maximum 5 mA when VCC = 4.5V) 17 VCCA - Analog positive power supply + 18 OSC I Oscillation frequency control pin

W51300

19 MICREF I Microphone reference 20 MIC I Microphone input 21 AGC 22 VCCD - Digital positive power supply 23 CPU I Normal/CPU mode select pin: low for normal, high for CPU 24 SMODE I Multi/single segment select pin: low for multi, high for single 25 TEST I External test pin for testing 26 EXTCLK I External clock pin for testing 27 RESET I Reset control pin 28 L_REC I Level record control pin 29 L_PLAY I Level playback control pin 30 E_PLAY I Edge playback control pin 31 ERASE I Message erase control pin in normal mode

32 FWD I/O Message forward control pin in normal mode

Automatic gain control input

Input level signal (from MCU) in CPU mode

Output level signal (to MCU) in CPU mode

Publication Release Date: April 1997

- 3 - Revision A2

BLOCK DIAGRAM

W51300

MIC

MICREF

AGC

SMODE

CPU

EXTCLK

TEST

Amp

VCCD

Anti-alias/ Smoothing Filter

AGC

ADM

Modulator

Logic/Timing Controller

MCU Interface

VSSD

VCCA

VSSA

ERASE

STOP

FWD

BWD

RESET

L_REC

Power Amp

AUD Amp

Flash EEPROM

Interface

L_PLAY

E_PLAY

BUSY

LEDOSC

SPK+

SPK-

AUD

CLK DATA ADDR MODE CTRL EOP

FUNCTIONAL DESCRIPTION

1. Single/Multi-segment Operation

The W51300 is typically used for either single or multi-segment operations. Single or multi-segment operating mode is selected by pin option.

Single Segment

The SMODE pin should be connected to VCC. In this mode, only one voice segment can be recorded. The storage duration can be extended by cascading serial flash EPROMs; up to 16 Mbits of memory can be cascaded.

Multi-segment

The SMODE pin should be connected to VSS or left floating. In this mode, a maximum of 63 voice segments can be recorded into flash EPROMs; up to 16 Mbits of memory can be cascaded. Messages can easily be accessed by using the FWD, BWD, and PLAY pins.

2. Selective Record

When the system is operated in multi-segment mode, voice segments can be recorded selectively. Users can insert a voice segment between any two existing voice segments. For instance, suppose there are already five voice segments, 1, 2, 3, 4, and 5, and the CAP (current address/message pointer) is at 3. Then a newly recorded voice segment will be assigned the number 4, and the original segments 4 and 5 will be changed to 5 and 6, respectively. If the maximum number of voice segments (63) or the end of memory space has been reached, a press of L_REC will be invalid and the LED will flash at 3 Hz for 2 seconds to indicate the invalid action.

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