Winbond Electronics W49F201T-55B, W49F201T-55, W49F201T-45B, W49F201T-45, W49F201S-55B Datasheet

...

Preliminary W49F201

128K × 16 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K × 16 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

• Single 5-volt operations:

− 5-volt Read/Erase/Program

• Fast Program operation:

− Word-by-Word programming: 50 µS (max.)

• Fast Erase operation: 60 mS (typ.)

• Fast Read access time: 45/55 nS

• Endurance: 1K/10K cycles (typ.)

• Ten-year data retention

• Hardware data protection

• Sector configuration

− One 8K words boot block with lockout

protection

− Two 8K words parameter blocks

− One 104K words (208K bytes) Main Memory

Array Blocks

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic program and erase timing with

internal VPP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• JEDEC standard word-wide pinouts

• Available packages: 44-pin SOP, 48-pin TSOP

Publication Release Date: June 1999

- 1 - Revision A1

Preliminary W49F201

PIN CONFIGURATIONS

A2 A1 A0

GND

OE DQ0 DQ8 DQ1 DQ9 DQ2

DQ10

DQ3

DQ11

A15

A14

A13

A12

A11

A10

A8 NC NC

RESET

NC NC NC NC

10 11 12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

22 23 24

44-pin

SOP

48-pin TSOP

BLOCK DIAGRAM

RESET

A10

A11

A12

38 37

A13

A14

A15 A16

GND

32 31

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

A16

NC GND

46 45

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

29 28

OE GND

27 26

CE OE

CONTROL

OUTPUT BUFFER

RESET

MAIN MEMORY

A16

. .

DECODER

104K WORDS

PARAMETER BLOCK2 8K WORDS

PARAMETER BLOCK1 8K WORDS

BOOT BLOCK 8K WORDS

PIN DESCRIPTION

SYMBOL PIN NAME

RESET A0−A16

DQ0−DQ15

VDD Power Supply

GND Ground

NC No Connection

Reset Address Inputs

Data Inputs/Outputs Chip Enable Output Enable Write Enable

DQ0

. .

DQ15

1FFFF

06000 05FFF

04000 03FFF

02000 01FFF

00000

- 2 -

Preliminary W49F201

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data to the output pins. The data bus is in high impedance state when either CE or OE is high. Refer

to the timing waveforms for further details.

Reset Operation

The RESET input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts

the device and all outputs are at high impedance state. The device also resets the internal state machine to read array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to assure data integrity. As the high state re-asserted

to the RESET pin, the device will return to read or standby mode, it depends on the control signals. The system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be

reprogrammed even though the boot block lockout function is enabled.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method.

There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the lockout feature will temporary be inactivated and the boot block can be erased/programmed. Once

the RESET pin returns to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 8K-words block, users can perform

software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be

Publication Release Date: June 1999

- 3 - Revision A1

Preliminary W49F201

completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function will erase all the sectors except the boot mode.

Sector Erase Operation

The three sectors, main memory and two parameters blocks, can be erased individually by initiating a six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle while the 30(hex) data input command is latched at the rising edge of WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

When the boot block lockout feature is inactivated, the boot block and the main memory block will be erased together. Once the boot block is locked, only the main memory block will be erased by the execution of sector erase operation.

Program Operation

The W49F201 is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will internally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 µS max. TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F201 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When the W49F201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed.

- 4 -

Preliminary W49F201

CEOEWE

RESET

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49F201 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from address 0001(hex) outputs the device code, 00AE(hex). The product ID operation can be terminated by a three-word command sequence or an alternative one-word command sequence (see Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, high, and raising A9 to 12 volts.

TABLE OF OPERATING MODES

Operating Mode Selection

(VHH = 12V ±5 %)

MODE PINS

ADDRESS DQ.

Read VIL VIL VIH VIH AIN Dout Erase/Program VIL VIH VIL VIH AIN Din Standby VIH X X VIH X High Z Erase/Program X VIL X VIH X High Z/DOUT Inhibit X X VIH VIH X High Z/DOUT Output Disable X VIH X VIH X High Z Product ID VIL VIL VIH VIH A0 = VIL;

A1−A15 = VIL; A9 = VHH

VIL VIL VIH VIH A0 = VIH;

A1−A15 = VIL; A9 = VHH

Reset X X X VIL X High Z

Manufacturer Code 00DA (Hex)

Device Code 00AE (Hex)

Publication Release Date: June 1999

- 5 - Revision A1

TABLE OF COMMAND DEFINITION

Preliminary W49F201

COMMAND

DESCRIPTION

Read 1 Chip Erase 6 Main Memory Erase 6 Word Program 4 Boot Block Lockout 6 Product ID Entry 3 Product ID Exit Product ID Exit

Notes:

1. Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex)

2. Either one of the two Product ID Exit commands can be used.

3. SA: Sector Address SA = 03XXXh for Parameter Block1 SA = 05XXXh for Parameter Block2 SA = 1FXXXh

- for Main Memory Block when Boot Block lockout feature is activated

- for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

AIN D

OUT

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30 5555 AA 2AAA 55 5555 A0 AIN D 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 5555 AA 2AAA 55 5555 90

(1) (1)

5555 AA 2AAA 55 5555 F0

XXXX F0

- 6 -

Preliminary W49F201

Command Flow

Command Codes for Word Program

WORD SEQUENCE ADDRESS DATA

0 Write 5555H AAH 1 Write 2AAAH 55H 2 Write 5555H A0H 3 Write Programmed-address Programmed-data

Pause 50 µS

Word Program Flow Chart

Word Program

Load data AA

address 5555

Load data 55

address 2AAA

Load data A0

address 5555

Load data Din

programmed-

address

Pause 50 S

Notes for software program code: Data Format: DQ15−DQ8: Don't Care; DQ7-DQ0 (Hex) Address Format: A14−A0 (Hex)

*It is not allowed to assert read command during the 4-word command sequence(program). To assert the read command during the 4-word command sequence will abort programming procedure.

Exit

Publication Release Date: June 1999

- 7 - Revision A1

+ 16 hidden pages