Winbond Electronics W49F102Q45, W49F102Q40, W49F102P40, W49F102P45 Datasheet

W49F102

64K × 16 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K × 16 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not
required. The unique cell architecture of the W49F102 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.

FEATURES

• Single 5-volt operations:

− 5-volt Read

− 5-volt Erase

− 5-volt Program

• Fast Program operation:

− Word-by-Word programming: 50 µS (max.)

• Fast Erase operation: 100 mS (typ.)

• Fast Read access time: 40/45 nS

• Endurance: 10K cycles (typ.)

• Ten-year data retention

• Hardware data protection

• 8K word Boot Block with Lockout protection

• Low power consumption

− Active current: 25 mA (typ.)

− Standby current: 20 µA (typ.)

• Automatic program and erase timing with

internal VPP generation

• End of program or erase detection

− Toggle bit

− Data polling

• Latched address and data

• TTL compatible I/O

• JEDEC standard word-wide pinouts

• Available packages: 40-pin TSOP and 44-pin

PLCC

Publication Release Date: October 2000

- 1 - Revision A3

W49F102

CE

OE

WE

PIN CONFIGURATIONS

A9
A10
A11
A12
A13
A14
A15
NC
WE
V
NC
CE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8

DQ12
DQ11
DQ10

DD

DQ9
DQ8

Vss

DQ7

DQ6
DQ5
DQ4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

D
Q

13

6

7
8
9
10

11
12
13

NC

14
15
16
17

18

D

Q
3

40-pin
TSOP

D

C

Q

Q

E

15

14

5

3

4

/

D

N

W

N

D

C

E

C

441

43

2

V

/

D

44-pin
PLCC

23

20

22

24

21

19

D
Q
2

N

D
Q
1

A

/

D
Q
0

A1A

C

O

0

E

BLOCK DIAGRAM

V

DD

V

40

Vss

39

A8

38

A7

37

A6

36

A5

35

A4

34

A3

33

A2

32

A1
A0

31
30

OE

29

DQ0

28

DQ1

27

DQ2

26

DQ3

25

DQ4
DQ5

24

DQ6

23

DQ7

22

Vss

21

A

A

1

1

N

4

5

C

4041

42

39

A13

38

A12

37

A11

36

A10

35

A9

34

Vss

33

NC

32

A8

31

A7

30

A6

29

27

2625

A
3

2

A5

28

A
4

PIN DESCRIPTION

SS

CE
OE
WE

A0

.
.

A15

CONTROL

DECODER

OUTPUT
BUFFER

MAIN

MEMORY

(56K Words)

BootBlock

(8K Words)

DQ0

.
.

DQ15

SYMBOL PIN NAME

A0 - A15

Address Inputs

DQ0 - DQ15 Data Inputs/Outputs

Chip Enable
Output Enable
Write Enable

VDD Power Supply

Vss Ground

NC No Connection

- 2 -

W49F102

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F102 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the
chip is de-selected and only standby power will be consumed. OE is the output control and is used
to gate data from the output pins. The data bus is in high impedance state when either CE or OE

is high. Refer to the timing waveforms for further details.

Boot Block Operation

There is one 8K-word boot block in this device, which can be used to store boot code. It is located in
the first 8K words of the memory with the address range from 0000 hex to 1FFF hex.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout); other memory
locations can be changed by the regular programming method. Once the boot block programming
lockout feature is activated, the chip erase function will only affect the main memory.

In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex".
If the output data is "FF hex," the boot block programming lockout feature is activated; if the output
data is "FE hex," the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. If the boot block programming lockout is activated, only the data in the main
memory will be erased to FF(hex), and the data in the boot block will not be erased (remains same as
before the chip erase operation). The entire memory array (main memory and boot block) will be
erased to FF(hex). by the chip erase operation if the boot block programming lockout feature is not
activated. The device will automatically return to normal read mode after the erase operation
completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Main Memory Erase Operation

The main memory erase mode can be initiated by a six-word command sequence. After the command
loading cycle, the device enters the internal main-memory erase mode, which is automatically timed
and will be completed in a fast 100 mS (typical). The host system is not required to provide any control
or timing during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Publication Release Date: October 2000

- 3 - Revision A3

W49F102

WE

Program Operation

The W49F102 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot block
from "0" to "1" is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word­program command is entered. The internal program timer will automatically time-out (50 µS max. ­TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F102 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation.

This prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ7 & DQ15)- Write Status Detection

The W49F102 includes a data polling feature to indicate the end of a program or erase cycle.
When the W49F102 is in the internal program or erase cycle, any attempt to read DQ7 or DQ15 of the
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 or DQ15 will show the true data. Note that DQ7 or DQ15 will show logical "0" during the
erase cycle, and become logical "1" or true data when the erase cycle has been completed.

Toggle Bit (DQ6 & DQ14)- Write Status Detection

In addition to data polling, the W49F102 provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 or
DQ14 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling
between 0's and 1's will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the
product ID. A read from address 0000H outputs the manufacturer code (00DAh). A read from address
0001H outputs the device code (002Fh). The product ID operation can be terminated by a three-word
command sequence or an alternate one-word command sequence (see Command Definition table).

In the hardware access mode, access to the product ID is activated by forcing CE and OE low,

high, and raising A9 to 12 volts.

- 4 -

TABLE OF OPERATING MODES

CE OE WE

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

5555

2AAA

5555

Operating Mode Selection

(VHH = 12V ± 5%)

MODE PINS

W49F102

ADDRESS DQ.

Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby VIH X X X High Z
Write Inhibit X VIL X X High Z/DOUT
X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
Product ID VIL VIL VIH

VIL VIL VIH

A0 = VIL; A1−A15 = VIL;
A9 = VHH

A0 = VIH; A1−A15 = VIL;
A9 = VHH

Manufacturer Code 00DA
(Hex)

Device Code
002F (Hex)

TABLE OF COMMAND DEFINITION

Command No. of 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Description Cycles

Read 1

Chip Erase 6

Main Memory Erase 6

Word Program 4

Boot Block Lockout 6

Product ID Entry 3

Product ID Exit

Product ID Exit

(1)

3

(1)

1

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

A

D

OUT

AA

AA

AA

AA

IN

55

55

55

55

80

80

A0

80

AA

AA
A

IN

DIN

AA

55

55

55

AA

55

90

AA

XXXX F0

55

F0

10

30

40

Note: Address Format: A14−A0 (Hex); Data Format: DQ15−DQ8 (Don't Care); DQ7-DQ0 (Hex)
Either one of the two Product ID Exit commands can be used.

Publication Release Date: October 2000

- 5 - Revision A3

Command Codes for Word Program

Command Flow

WORD SEQUENCE ADDRESS DATA

0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-Address Programmed-Data

Word Program Flow Chart

Word Program

Load data AA

to

address 5555

W49F102

Notes for software program code:
Data Format: DQ15−DQ0 (Hex); XX = Don't Care
Address Format: A14−A0 (Hex)

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Load data Din

to

programmed-

address

Pause 50 S

µ

Exit

- 6 -

Command Codes for Chip Erase

55H

10H

BYTE SEQUENCE ADDRESS DATA

1 Write 5555H AAH
2 Write 2AAAH
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H

Chip Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

W49F102

Notes for chip erase:
Data Format: DQ15-DQ8: Don't Care; DQ7−DQ0 (Hex)

Address Format: A14−A0 (Hex)

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 1 Sec.

Exit

Publication Release Date: October 2000

- 7 - Revision A3