Winbond Electronics W49F020Q-90B, W49F020Q-90, W49F020Q-70B, W49F020Q-70, W49F020P-90B Datasheet
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Preliminary W49F020
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not
required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.
FEATURES
• Single 5-volt operations:
− 5-volt Read
− 5-volt Erase
− 5-volt Program
• Fast Program operation:
− Byte-by-Byte programming: 50 µS (max.)
• Fast Erase operation: 100 mS (typ.)
• Fast Read access time: 70/90 nS
• Endurance: 1K/10K cycles (typ.)
• Twenty-year data retention
•
Hardware data protection
• One 8K byte Boot Block with Lockout
protection
• Low power consumption
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
•
Automatic program and erase timing with
internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• JEDEC standard byte-wide pinouts
• Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
Publication Release Date: October 1999
- 1 - Revision A1
Preliminary W49F020
1
2
3
4
6
789
10
11
12
131415
16
32
3130292827
17
V
A13
DD
5
12
13
18
17
A13
DQ7
E
2
3
6
8
9
11
13
DQ2
DQ3
V
A13
DD
CONTROL
OUTPUT
BUFFER
DECODER
MAIM MEMORY
248K BYTES
BOOT BLOCK
8K BYTES
CE
OE
WE
PIN CONFIGURATIONS
NC
A16
A15
A12
5
A7
A6
A5
32-pin
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A11
A9
A8
5
A14
A17
WE
NC
10
A16
A15
12
A12
A7
14
A6
15
A5
16 A3
A4
DIP
A
A
V
/
A
A
N
1
1
D
W
1
2
5
6
7
8
9
10
11
D
D
Q
Q
1
2
C
6
32-pin
PLCC
161514
G
D
N
Q
D
3
32-pin
TSOP
1
D
7
3031321234
2019
D
D
D
Q
Q
Q
4
5
6
BLOCK DIAGRAM
WE
A17
A14
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20
DQ6
19
DQ5
18
DQ4
DQ3
V
V
CE
OE
WE
A0
DD
SS
.
.
A17
29
A14
28
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
PIN DESCRIPTION
SYMBOL PIN NAME
A0−A17
32
OE
A10
31
30
CE
DQ7
29
DQ6
28
DQ5
27
DQ4
26
25
GND
24
23
DQ1
22
DQ0
21
20
A0
A1
19
A2
18
17
DQ0−DQ7
VDD Power Supply
GND Ground
NC No Connection
W49F020
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
DQ0
.
.
DQ7
3FFFF
02000
01FFF
00000
- 2 -
Preliminary W49F020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F020 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is
de-selected and only standby power will be consumed. OE is the output control and is used to gate data
from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the
timing waveforms for further details.
Boot Block Operation
There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block
locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the
specific code, please see Command Codes for Boot Block Lockout Enable.
When the boot block is enabled, data for the designated block cannot be erased or programmed
(programming lockout); other memory locations can be changed by the regular programming method.
When the boot block programming lockout feature is activated, the chip erase function cannot erase the
boot block any longer.
In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform
software command sequence to check it. First, enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the
output data is "0," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
in a fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the main memory blocks
will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the
chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function erase the main memory block but not the boot block. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.
Program Operation
The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data
"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot
block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. -
Publication Release Date: October 1999
- 3 - Revision A1
Preliminary W49F020
WE
TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits
can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ7 of the
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).
In the hardware access mode, access to the product ID will be activated by forcing CE and OE low,
high, and raising A9 to 12 volts.
- 4 -
Preliminary W49F020
CE OE WE
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 5%)
MODE PINS
Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby V
IH
X X X High Z
Write Inhibit X VIL X X High Z/DOUT
X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
Product ID VIL VIL VIH
A0 = VIL; A1−A17 = VIL;
A9 = VHH
VIL VIL VIH
A0 = VIL; A1−A17 = VIL;
A9 = VHH
ADDRESS DQ.
Manufacturer Code DA (Hex)
Device Code 8C (Hex)
TABLE OF COMMAND DEFINITION
COMMAND
DESCRIPTION
Read 1
Chip Erase 6
Byte Program 4
Boot Block Lockout 6
Product ID Entry 3
Product ID Exit
Product ID Exit
Notes:
1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
(1)
3
(1)
1
AIN D
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
5555 AA 2AAA 55 5555 A0 AIN DIN
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
5555 AA 2AAA 55 5555 90
5555 AA 2AAA 55 5555 F0
XXXX F0
OUT
Publication Release Date: October 1999
- 5 - Revision A1
Preliminary W49F020
Command Codes for Byte Program
WORD SEQUENCE ADDRESS DATA
0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-Address Programmed-Data
Byte Program Flow Chart
Byte Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Notes for software program code:
Data Format: DQ7−DQ0 (Hex
Address Format: A14−A0 (Hex)
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Pause 50 S
µ
Exit
- 6 -
Command Codes for Chip Erase
BYTE SEQUENCE ADDRESS DATA
1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 10H
Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Preliminary W49F020
Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 1 Sec.
Exit
Publication Release Date: October 1999
- 7 - Revision A1
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