Winbond Electronics W49F020Q-90B, W49F020Q-90, W49F020Q-70B, W49F020Q-70, W49F020P-90B Datasheet
...
Preliminary W49F020
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not
required. The unique cell architecture of the W49F020 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.
FEATURES
• Single 5-volt operations:
− 5-volt Read
− 5-volt Erase
− 5-volt Program
• Fast Program operation:
− Byte-by-Byte programming: 50 µS (max.)
• Fast Erase operation: 100 mS (typ.)
• Fast Read access time: 70/90 nS
• Endurance: 1K/10K cycles (typ.)
• Twenty-year data retention
•
Hardware data protection
• One 8K byte Boot Block with Lockout
protection
• Low power consumption
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
•
Automatic program and erase timing with
internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Latched address and data
• TTL compatible I/O
• JEDEC standard byte-wide pinouts
• Available packages: 32-pin DIP and 32-pin
TSOP and 32-pin-PLCC
Publication Release Date: October 1999
- 1 - Revision A1
Preliminary W49F020
1
2
3
4
6
789
10
11
12
131415
16
32
3130292827
17
V
A13
DD
5
12
13
18
17
A13
DQ7
E
2
3
6
8
9
11
13
DQ2
DQ3
V
A13
DD
CONTROL
OUTPUT
BUFFER
DECODER
MAIM MEMORY
248K BYTES
BOOT BLOCK
8K BYTES
CE
OE
WE
PIN CONFIGURATIONS
NC
A16
A15
A12
5
A7
A6
A5
32-pin
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A11
A9
A8
5
A14
A17
WE
NC
10
A16
A15
12
A12
A7
14
A6
15
A5
16 A3
A4
DIP
A
A
V
/
A
A
N
1
1
D
W
1
2
5
6
7
8
9
10
11
D
D
Q
Q
1
2
C
6
32-pin
PLCC
161514
G
D
N
Q
D
3
32-pin
TSOP
1
D
7
3031321234
2019
D
D
D
Q
Q
Q
4
5
6
BLOCK DIAGRAM
WE
A17
A14
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
DQ7
20
DQ6
19
DQ5
18
DQ4
DQ3
V
V
CE
OE
WE
A0
DD
SS
.
.
A17
29
A14
28
27
A8
26
A9
25
A11
24
OE
23
A10
22
CE
21
PIN DESCRIPTION
SYMBOL PIN NAME
A0−A17
32
OE
A10
31
30
CE
DQ7
29
DQ6
28
DQ5
27
DQ4
26
25
GND
24
23
DQ1
22
DQ0
21
20
A0
A1
19
A2
18
17
DQ0−DQ7
VDD Power Supply
GND Ground
NC No Connection
W49F020
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
DQ0
.
.
DQ7
3FFFF
02000
01FFF
00000
- 2 -
Preliminary W49F020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F020 is controlled by CE and OE, both of which have to be low for the
host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is
de-selected and only standby power will be consumed. OE is the output control and is used to gate data
from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the
timing waveforms for further details.
Boot Block Operation
There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block
locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the
specific code, please see Command Codes for Boot Block Lockout Enable.
When the boot block is enabled, data for the designated block cannot be erased or programmed
(programming lockout); other memory locations can be changed by the regular programming method.
When the boot block programming lockout feature is activated, the chip erase function cannot erase the
boot block any longer.
In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform
software command sequence to check it. First, enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the
output data is "0," the lockout feature is inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
in a fast 100 mS (typical). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the main memory blocks
will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the
chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function erase the main memory block but not the boot block. The device will
automatically return to normal read mode after the erase operation completed. Data polling and/or
Toggle Bits can be used to detect end of erase cycle.
Program Operation
The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data
"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot
block from "0" to "1") is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. -
Publication Release Date: October 1999
- 3 - Revision A1
Preliminary W49F020
WE
TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits
can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F020 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F020 features a data polling function which used to indicate the end of a program or erase
cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ7 of the
last word loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and
become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F020 provides another method for determining the end of a program
cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce
alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's
will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In software
access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product
ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address
0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a
three-word command sequence or an alternated one-word command sequence (see Command
Definition table).
In the hardware access mode, access to the product ID will be activated by forcing CE and OE low,
high, and raising A9 to 12 volts.
- 4 -
Preliminary W49F020
CE OE WE
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V ± 5%)
MODE PINS
Read VIL VIL VIH AIN Dout
Write VIL VIH VIL AIN Din
Standby V
IH
X X X High Z
Write Inhibit X VIL X X High Z/DOUT
X X VIH X High Z/DOUT
Output Disable X VIH X X High Z
Product ID VIL VIL VIH
A0 = VIL; A1−A17 = VIL;
A9 = VHH
VIL VIL VIH
A0 = VIL; A1−A17 = VIL;
A9 = VHH
ADDRESS DQ.
Manufacturer Code DA (Hex)
Device Code 8C (Hex)
TABLE OF COMMAND DEFINITION
COMMAND
DESCRIPTION
Read 1
Chip Erase 6
Byte Program 4
Boot Block Lockout 6
Product ID Entry 3
Product ID Exit
Product ID Exit
Notes:
1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex)
2. Either one of the two Product ID Exit commands can be used.
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
(1)
3
(1)
1
AIN D
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10
5555 AA 2AAA 55 5555 A0 AIN DIN
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40
5555 AA 2AAA 55 5555 90
5555 AA 2AAA 55 5555 F0
XXXX F0
OUT
Publication Release Date: October 1999
- 5 - Revision A1
Preliminary W49F020
Command Codes for Byte Program
WORD SEQUENCE ADDRESS DATA
0 Write 5555H AAH
1 Write 2AAAH 55H
2 Write 5555H A0H
3 Write Programmed-Address Programmed-Data
Byte Program Flow Chart
Byte Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Notes for software program code:
Data Format: DQ7−DQ0 (Hex
Address Format: A14−A0 (Hex)
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Pause 50 S
µ
Exit
- 6 -
Command Codes for Chip Erase
BYTE SEQUENCE ADDRESS DATA
1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 10H
Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Preliminary W49F020
Notes for chip erase:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 1 Sec.
Exit
Publication Release Date: October 1999
- 7 - Revision A1
Preliminary W49F020
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE
SEQUENCE
1 Write 5555 AA 5555H AAH
2 Write 2AAA 55 2AAAH 55H
3 Write 5555 90 5555H F0H
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
ALTERNATE PRODUCT (6)
IDENTIFICATION/BOOT BLOCK
LOCKOUT DETECTION ENTRY
IDENTIFICATION/BOOT BLOCK LOCKOUT
SOFTWARE PRODUCT
DETECTION EXIT (7)
ADDRESS DATA ADDRESS DATA
Pause 10 µS Pause 10 µS
Product
Identification
Entry (1)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 90
to
address 5555
Pause 10 S
µ
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Read address = 00000
data = DA
Read address = 00001
data =8C
Read address = 00002
data in DQ0 = "1"/"0"
(2)
(2)
(4)
Product
Identification Exit(7)
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data F0
to
address 5555
Pause 10 S
Normal Mode
µ
(5)
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)
(2) A1−A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification and boot block lockout detection mode if power down.
(4) If the output data in DQ0= " 1," the boot block programming lockout feature is activated; if the output data in DQ0= " 0," the lockout feature is
inactivated and the block can be programmed.
(5) The device returns to standard operation mode.
(6) Optional 1-word cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
- 8 -
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET
1 Write 5555H AAH
2 Write 2AAAH 55H
3 Write 5555H 80H
4 Write 5555H AAH
5 Write 2AAAH 55H
6 Write 5555H 40H
ADDRESS DATA
Pause 1 Sec.
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Preliminary W49F020
Notes for boot block lockout enable:
Data Format: DQ7−DQ0 (Hex)
Address Format: A14−A0 (Hex)
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40
to
address 5555
Pause 1 Sec.
Exit
Publication Release Date: October 1999
- 9 - Revision A1
Preliminary W49F020
CE
CE
CE
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage to Vss Potential -0.5 to +7.0 V
Operating Temperature 0 to +70
Storage Temperature -65 to +150
D.C. Voltage on Any Pin to Ground Potential except OE
Transient Voltage (<20 nS ) on Any Pin to Ground Potential -1.0 to VDD +1.0 V
Voltage on OE Pin to Ground Potential
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
-0.5 to VDD +1.0 V
-0.5 to 12.5 V
°C
C
°
PARAMETER SYM.
Power Supply
Current
Standby VDD
Current (TTL input)
Standby VDD Current
(CMOS input)
Input Leakage
Current
Output Leakage
Current
Input Low Voltage V
Input High Voltage VIH - 2.0 - VDD +0.5 V
Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V
Output High Voltage VOH IOH = -0.4 mA 2.4 - - V
CC
I
all DQs open
Address inputs = VIL/VIH, at f = 5 MHz
ISB1
Other inputs = VIL/VIH
ISB2
Other inputs = VDD -0.3V/GND
ILI VIN = GND to VDD - - 10
ILO V
OUT
IL
TEST CONDITIONS LIMITS UNIT
MIN. TYP. MAX.
= OE = VIL, WE = VIH,
= VIH, all DQs open
= VDD -0.3V, all DQs open
= GND to VDD - - 10
- -0.3 - 0.8 V
- 25 50 mA
- 2 3 mA
- 20 100
µA
µA
µA
- 10 -
Preliminary W49F020
Power-up Timing
PARAMETER SYMBOL TYPICAL UNIT
Power-up to Read Operation TPU. READ 100
Power-up to Write Operation TPU. WRITE 5 mS
CAPACITANCE
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX. UNIT
I/O Pin Capacitance CI/O VI/O = 0V 12 pf
Input Capacitance CIN VIN = 0V 6 pf
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise/Fall Time < 5 nS
Input/Output Timing Level 1.5V/1.5V
Output Load 1 TTL Gate and CL = 100 pF for 90nS
CL = 30 pF for 70nS
µS
AC Test Load and Waveform
+5V
1.8K
Ω
D
OUT
30 pF for 70nS
100 pF for 90nS
(Including Jig and
Scope)
Input
3V
0V
1.5V
Test Point Test Point
Publication Release Date: October 1999
- 11 - Revision A1
Output
1.5V
1.3K
Ω
Preliminary W49F020
AC Characteristics, continued
Read Cycle Timing Parameters
(VCC = 5.0V ±10%, VCC = 0V, TA = 0 to 70° C)
PARAMETER SYM. W49F020-70 W49F020-90 UNIT
MIN. MAX. MIN. MAX.
Read Cycle Time TRC
Chip Enable Access Time TCE
Address Access Time TAA
Output Enable Access Time T
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change TOH 0 - 0 - nS
OE
TCLZ
TOLZ
TCHZ
TOHZ
70 - 90 - nS
- 70 - 90 nS
- 70 - 90 nS
- 35 - 40 nS
0 - 0 - nS
0 - 0 - nS
- 25 - 25 nS
- 25 - 25 nS
Write Cycle Timing Parameters
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Address Setup Time T
Address Hold Time TAH 50 - - nS
WE and CE Setup Time
WE and CE Hold Time
High Setup Time
OE
High Hold Time
OE
CE Pulse Width
WE Pulse Width
WE High Width
Data Setup Time TDS 50 - - nS
Data Hold Time TDH 0 - - nS
Byte programming Time T
Erase Cycle Time TEC - 0.1 1 S
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
AS
TCS 0 - - nS
TCH 0 - - nS
TOES 0 - - nS
TOEH 0 - - nS
TCP 100 - - nS
TWP 100 - - nS
TWPH 100 - - nS
BP
0 - - nS
- 10 50
µS
- 12 -
Preliminary W49F020
OE
CE
OE
CE
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER SYM. W49F020-70 W49F020-90 UNIT
to Data Polling Output Delay
to Data Polling Output Delay
to Toggle Bit Output Delay
to Toggle Bit Output Delay
TOEP TCEP TOET TCET -
TIMING WAVEFORMS
Read Cycle Timing Diagram
MIN. MAX. MIN. MAX.
35 - 40
70 - 90
35 - 40
70 - 90
nS
nS
nS
nS
T
RC
Address A17-0
T
CE
OE
V
WE
DQ7-0
IH
High-Z
CE
T
OE
T
T
OLZ
T
CLZ
Data Valid
T
OH
AA
T
Data Valid
T
CHZ
OHZ
High-Z
Publication Release Date: October 1999
- 13 - Revision A1
Timing Waveforms, continued
WE
CE
Controlled Command Write Cycle Timing Diagram
Preliminary W49F020
Address A17-0
WE
DQ7-0
T
AS
CE
OE
T
CS
T
OES
T
AH
Controlled Command Write Cycle Timing Diagram
AS
T
Address A17-0
CE
T
T
CH
T
OEH
T
WP
T
DS
Data Valid
T
WPH
T
DH
AH
TCP
TCPH
T
OES
OE
WE
DQ7-0
High Z
- 14 -
TDS
Data Valid
TOEH
TDH
Timing Waveforms, continued
DATA
Program Cycle Timing Diagram
Address A17-0
5555
Byte Program Cycle
55552AAA
Address
Preliminary W49F020
DQ7-0
CE
OE
WE
Polling Timing Diagram
Address A17-0
WE
CE
OE
DQ7
WP
T
Byte 0
AA
T
WPH
Byte 1
A055
Byte 2
Byte 3
Data-In
TBP
Internal Write Start
T
CEP
T
OEH
T
OEP
X
X
TECTBP or
X
T
OES
X
Publication Release Date: October 1999
- 15 - Revision A1
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A17-0
WE
CE
OE
DQ6
Preliminary W49F020
T
OEH
T
BP orTEC
T
OES
Boot Block Lockout Enable Timing Diagram
Six byte code for Boot Block
Lockout Feature Enable
Address A17-0
DQ7-0
CE
OE
WE
5555 2AAA
XXAA
TWP
T
WPH
SB0
5555
XX55 XX80
SB2
SB1
5555 2AAA
XXAA
XX55 XX40
SB3
SB4
5555
SB5
T
EC
- 16 -
Timing Waveforms, continued
Chip Erase Timing Diagram
Address A17-0
5555 2AAA
Six-byte code for 5V-only software
chip erase
5555
5555 2AAA
Preliminary W49F020
5555
DQ7-0
CE
OE
WE
XXAA
T
SB0
WP
XX55 XX80
T
WPH
SB1
SB2
SB3
XXAA
XX55
SB4
XX10
SB5
T
EC
Internal Erase starts
Publication Release Date: October 1999
- 17 - Revision A1
ORDERING INFORMATION
ACCESS
S)
Preliminary W49F020
PART NO.
TIME
(n
W49F020-70 70 50 100 (CMOS) 32-pin DIP 1K
W49F020-90 90 50 100 (CMOS) 32-pin DIP 1K
W29F020Q-70 70 50 100 (CMOS)
W29F020Q-90 90 50 100 (CMOS)
W29F020P-70 70 50 100 (CMOS) 32-pin PLCC 1K
W29F020P-90 90 50 100 (CMOS) 32-pin PLCC 1K
W49F020-70B 70 50 100 (CMOS) 32-pin DIP 10K
W49F020-90B 90 50 100 (CMOS) 32-pin DIP 10K
W29F020Q-70B 70 50 100 (CMOS)
W29F020Q-90B 90 50 100 (CMOS)
W29F020P-70B 70 50 100 (CMOS) 32-pin PLCC 10K
W29F020P-90B 90 50 100 (CMOS) 32-pin PLCC 10K
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
3. There are two kinds of boot block in this device. The part number shown in the Ordering Information table is only for Bottom Boot
Block part, which is in the lower address range. For the requirement of the higher address range boot block, the Top Boot Block,
please contact Winbond FAE for details.
POWER
SUPPLY
CURRENT
MAX.
(mA)
STANDBY
VDD
CURRENT
MAX.
(µA)
PACKAGE CYCLE
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
32-pin TSOP (8 mm × 20 mm)
1K
1K
10K
10K
- 18 -
PACKAGE DIMENSIONS
32-pin P-DIP
Preliminary W49F020
32
1E
1
2
A
A
L
32-pin PLCC
5
13
14
L
θ
Seating Plane
Dimension in inches
Symbol
Min. Nom. Max. Max.Nom.Min.
A
0.010
A
1
0.155
0.150
2
A
0.016
0.018
B
0.050 1.27
B1
c
0.010
D
S
B
1
e
1
B
17
16
1A
Base Plane
Seating Plane
E
e
A
a
c
Symbol
H
E
E
1
324
30
29
D
HD
21
G D
0.008
1.650 1.660 41.91 42.16
D
0.6000.590
E
0.545
E
0.550
1
e
1
0.120
0.130
L
0 15
a
0.6500.630 16.00 16.51
e
A
S
Notes:
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
2.Dimension E1 does not include interlead flash.
3.Dimensions D & E1 include mold mismatch and
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
5.Controlling dimension: Inches
6.General appearance spec. should be based on
final visual inspection spec.
Dimension in Inches Dimension in mm
Min. Nom. Max. Max.Nom.Min.
A
0.020
A
1
A
2
b
b
c
D
E
e
G
G
H
HE
L
y
θ
0.028
1
0.016
0.018
0.008
0.010
0.547
0.550
0.447
0.450
0.050
0.490
0.51
D
0.390
0.410
E
0.585
0.590
D
0.485
0.49
0.075
0.090
°
0
Dimension in mm
0.210 5.33
0.25
0.160
3.81
0.41
0.022
0.0540.048
0.014
0.20
15.24
0.610
14.99
13.9713.84
0.555
0.110
2.29 2.54 2.790.090 0.100
0.140
3.05
0.670
0.085
.
0.140
0.50
0.66 0.81
0.41
0.20
13.89
11.35
1.12 1.420.044 0.056
12.45
9.91
14.86
12.32
1.91 2.29
°
10
0
°
2.802.67 2.93
0.71
0.46
0.25
13.97
11.43
1.27
12.9
10.41
14.99
12.45
0.1150.105 0.110
0.0320.026
0.022
0.014
0.553
0.453
0.530
0.430
0.595
0.495
0.095
0.004
3.94
4.06
0.46
0.56
1.371.22
0.25
0.36
15.49
14.10
3.30
3.56
150
17.02
2.16
3.56
0.56
0.35
14.05
11.51
13.46
10.92
15.11
12.57
2.41
0.10
°
10
Notes:
20
2A
A
e
b
1b
E
G
A1
y
c
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based on final
visual inspection sepc.
Publication Release Date: October 1999
- 19 - Revision A1
Package Dimensions, continued
32-pin TSOP
M
e
0.10(0.004)
b
θ
L
L
1
Preliminary W49F020
H
D
D
c
E
A
A
2
A
1
Y
Dimension in Inches
Symbol
Min. Nom.
__
A
0.002
A
1
2
A
0.007 0.008
b
c
0.005 0.006
0.720 0.724
D
0.311 0.315
E
0.780 0.787
H
D
__
e
0.016 0.020
L
__
L
1
0.000 0.004
Y
1
θ
Note:
Controlling dimension: Millimeters
Max.
__
0.047
__ __
0.006
0.0410.0390.037
0.009
0.007
0.728
0.319
0.795
__
0.020
0.024
__
0.031
__
3
18.30
19.80
5
Dimension in mm
Min. Nom.
__
__
0.05
0.95
0.17
0.20 0.23
0.12
0.15 0.17
18.40 18.50
7.90
8.00 8.10
20.00 20.20
__
0.50
0.40
0.50 0.60
__
0.80
__
0.00
1
3
Max.
1.20
0.15
1.051.00
__
__
0.10
5
- 20 -
Preliminary W49F020
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Oct. 1999 - Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Publication Release Date: October 1999
- 21 - Revision A1
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