White Electronic Designs EDI8L32256C17AI, EDI8L32256C17AC, EDI8L32256C15AC, EDI8L32256C25AI, EDI8L32256C25AC Datasheet
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Features
256Kx32 bit CMOS Static
DSP Memory Solution
• Texas Instruments TMS320C3x, TMS320C4x
• Analog SHARC
• Motorola DSP96002
Random Access Memory Array
• Fast Access Times: 15, 17, 20 and 25ns
• Individual Byte Enables
• User Configurable Organization
with Minimal Additional Logic
• Master Output Enable and Write Control
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
Surface Mount Package
• 68 Lead PLCC, No. 99, JEDEC MO-47AE
• Small Footprint, 0.990 Sq. In.
• Multiple Ground Pins for Maximum
Noise Immunity
Single +5V (±5%) Supply Operation
TM
DSP
EDI8L32256C
256Kx32 SRAM Module
256Kx32, 5V Static Ram
The EDI8L32256C is a high speed, 5V, 8 megabit SRAM.
The device is available with access times of 15, 17, 20 and
25ns, allowing the creation of a no wait state DSP memory
solution.
The device can be configured as a 256Kx32 and used to
create a single chip external data memory solution for
Texas Instruments' TMS320C30/31, TMS 320C32 or
TMS320C4x, Motorola's DSP96002 and Analog Device's
TM
SHARC
Alternatively the device's chip enables can be used to
configure it as a 512Kx16. A 512Kx48 program memory
array for Analog's SHARCTM DSP is created using three
devices. If this memory is too deep, two 256Kx24s
(EDI8L24256C) can be used to create a 256Kx48 array or
two 128Kx24s (EDI8L24128C) can be used to create a
128Kx48 array.
The device provides a 32% space savings when compared
to two monolithic 256Kx16, 44 pin SOJs.
The device provides a memory upgrade of the
EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32).
For more memory the device can be upgraded to the
EDI8L32512C (512Kx32).
DSP.
Pin Configurations and Block Diagram
9 DQ16
8NC
7A17
6 BS3\
5 BS2\
4 BS1\
3 BSØ\
2E1\
1VCC
68 NC
67 EØ\
66 G\
65 W\
64 A16
63 A15
62 A14
61 DQ15
DQ17
10
DQ18
11
DQ19
12
VSS
13
DQ20
14
DQ21
15
DQ22
16
DQ23
17
VCC
18
DQ24
19
DQ25
20
DQ26
21
DQ27
22
VSS
23
DQ28
24
DQ29
25
DQ30
26
A6 28
A5 29
A4 30
A3 31
A2 32
A1 33
DQ31 27
Note: For memory upgrade information refer to page 8, Figure 8 "EDI MCM-L
upgrade path".
AØ 34
• One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 •
A9 40
A13 36
A12 37
A11 38
A10 39
VCC 35
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A8 41
A7 42
DQØ 43
Electronic Designs Incorporated
http://www.electronic-designs.com
EDI8L32256C Rev. 4 3/98 ECO#9662
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
VCC
DQ7
DQ6
DQ5
DQ4
VSS
DQ3
DQ2
DQ1
NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds.
Pin Names
AØ-A17 Address Inputs
EØ-E1 Chip Enables (One per Word)
BSØ-BS3 Byte Selects (One per Byte)
W Master Write Enable
G Master Output Enable
DQØ-DQ31 Common Data Input/Output
VCC Power (+5V±5%)
VSS Ground
NC No Connection
AØ-A17
18
G
W
EØ
E1
BSØ
BS1
BS2
BS3
1
256Kx32
Memory
Array
DQØ-DQ7
DQ8-DQ15
DQ16-DQ23
DQ24-DQ31
Absolute Maximum Ratings*
Recommended DC Operating Conditions
Voltage on any pin relative to VSS -0.5V to 7.0V
Operating Temperature TA (Ambient)
Commercial 0°C to + 70°C
Industrial -40°C to +85°C
Storage Temperature -55°C to +125°C
Parameter Sym Min Typ Max Units
Supply Voltage VCC 4.75 5.0 5.25 V
Supply Voltage VSS 0 0 0 V
Input High Voltage VIH 2.2 -- VCC+0.5 V
Input Low Voltage VIL -0.3 -- 0.8 V
Power Dissipation 3.1 Watts
Output Current. 20 mA
Junction Temperature, TJ 175°C
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
AC Test Conditions
Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 1.5V
Output Load Figure 1
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
Figure 1 Figure 2
Q
255
VCC
480
Q
30 pF
255
VCC
480
5 pF
DC Electrical Characteristics
Parameter Sym Conditions Min Max Units
Operating Power Supply Current ICC1 W= VIL, II/O = 0mA, 575 480 mA
Min Cycle
Standby (TTL) Supply Current ICC2 E ≥ VIH, VIN ≤ VIL or 120 120 mA
VIN ≥ VIH, f=ØMHz
Full StandbySupply Current ICC3 E ≥ VCC-0.2V 20 20 mA
VIN ≥ VCC-0.2V or
VIN ≤ 0.2V
Input Leakage Current ILI VIN = 0V to VCC
Output Leakage Current ILO V I/O = 0V to VCC ±10 µA
Output High Volltage VOH IOH = -4.0mA 2.4 V
Output Low Voltage VOL IOL = 8.0mA 0.4 V
15/17 20/25
10 µA
±
E W G BSØ-3 Mode Output Power
H X X X Standby High Z
L H H X Output Disable High Z ICC1
L X X H Output Disable High Z ICC1
L H L L Read DOUT ICC1
L L X L Write DIN ICC1
X Means Don't Care
EDI8L32256C
256Kx32 SRAM Module
CapacitanceTruth Table
(f=1.0MHz, VIN=VCC or VSS)
ICC2,ICC3,
EDI8L32256C Rev. 4 3/98 ECO#9662
Parameter Sym Max Unit
Address Lines CA 20 pF
Data Lines CD/Q 10 pF
Write & Output Enable Lines W, G 6 pF
Chip Enable Lines/Byte Select E, BS 9 pF
2
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