Wavetek 5100, 5110 Service manual

INSTRUCTION

MANUAL

MODELS 5100 AND 5110

0.001

HZ-2

MHz

PROGRAMMABLE FREQUENCY

SYNTHESIZERS

O

1981

Wavetek

THIS DOCUMENT CONTAINS INFORMATION PRO-

PRIETARY TO WAVETEK AND IS PROVIDED SOLELY FOR INSTRUMENT OPERATION AND MAINTENANCE. THE INFORMATION IN THIS DOCUMENT MAY NOT DUPLICATED IN ANY MANNER WITHOUT THE PRIOR

APPROVAL IN WRITING FROM WAVETEK.

BE

WAVETEK SAN

9045 Balboa Ave., San Diego, CA 92123 P.

0.

Box 85265, San Diego, CA 921 38

61

91279-2200

Tel

DIEGO, I NC.

TWX

91 01335-2007 Manual Part

Manual Revision: 4188

Number:

00-800-1

51

0

*

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WARRANTY

Wavetek warrants that all products manufactured by Wavetek conform to published Wavetek specifications and are free from defects in materials and workmanship for a period of one and within the service conditions for which they were furnished.

The obligation of Wavetek arising from a Warranty claim shall be limited to repairing, or at its option, replacing without charge, any product which in Wavetek's sole opinion proves to be defective within the scope of the Warranty. In the event Wavetek is not able to modify,

repair or replace non-conforming defective parts or components to a condition as warrantied within a reasonable time after receipt thereof, Buyers shall be credited for their value at the original purchase price.

Wavetek must be notified in writing of the defect or nonconformity within the Warranty period and the affected product returned to Wavetek's factory or to an authorized service center within

For product warranties requiring return to Wavetek, products must be returned to a service facility designated by Wavetek. Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Wavetek for warranty service. Except for products

returned to Buyer from another country, Wavetek shall pay for return of products to Buyer. Wavetek shall have no responsibility hereunder for any defect or damage caused by

improper storage, improper installation, unauthorized modification, misuse, neglect,

inadequate maintenance, accident or for any product which has been repaired or altered by anyone other than Wavetek or its authorized representative and not in accordance with instructions furnished by Wavetek.

(1)

year from the date of delivery when used under normal operating conditions

(30)

days after discovery of such defect or nonconformity.

Exclusion of Other Warranties

The Warranty described above is Buyer's sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Wavetek specifically disclaims the implied warranties of merchantability and fitness for a particular pur-

pose. No statement, representation, agreement, or understanding, oral or written, made

by an agent, distributor, representative, or employee of Wavetek, which is not contained

in the foregoing Warranty will be binding upon Wavetek, unless made in writing and executed by an authorized Wavetek employee. Under no circumstances shall Wavetek

be liable for any direct, indirect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.

SECTION 1 GENERAL DESCRIPTION

.

1 1 MODELS 5100 and 51 10 1-1

1.2 SPECIFICATIONS

1.2.1 Frequency

1.2.2 Frequency References

1.2.3 Output Amplitudes 1-1

1.2.4 Output Level Control

1.2.5 Spectral Purity

1.2.6 Remote Mode Selection (Model 51 00) 1-2

1.2.7 Switching Charactoristics

1.2.8 GPlB 1-2

....................................................

1.2.9 General

1.2.1 0 Options

1.2.1 1 Accessories 1-2

SECTION 2 INSTALLATION

2.1 INSPECTION

2.2 POWER REQUIREMENTS

2.3 INSTALLATION

2.3.1 Model 51 00

2.3.2 Model5110 2-2

2.4 INITIAL CONFORMANCE TEST PROCEDURE 2-2

SECTION 3 OPERATION

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1-1 1-1 1-1

1-2 1-2

1-2

2-1 2-1 2-1 2-2

3.1 INTRODUCTION

............................................

3.2 POWER SWITCH AND INDICATOR

3.3 SYSTEM CLOCKS 3-1

3.3.1 Internal Reference

3.3.2 External Reference (REF IN Signal) 3-1

3.3.3 Phase-Locking to an External 1 MHz Standard 3-1

3.3.4 Phase-Locking Two or More Instruments 3-3

3.4 OUTPUT SIGNALS 3-3

3.4.1 Model 5100 Main Outputs

3.4.2 Model 51 10 Main Outputs

3.4.3 Models 51 00 and 51 10 Reference Output Signals

3.5 REMOTE SWITCH AND INDICATOR (Model 51 00 Only)

3.6 LOCAL MODE OPERATION (Model 5100 Only)

3.6.1 Local Frequency Control

3.6.2 Local Attenuation and Level Control

3.7

REMOTE MODE OPERATION (Models 51 00 and 51 10)

3.7.1 Programming Lines

3.7.2 Remote-Local Mode Transitions (Model 51 00 Only) 3-9

SECTION 4 CIRCUIT DESCRIPTION

4.1 SlNUSOlD GENERATION 4-1

4.2 FUNCTIONALBLOCKTHEORY 4-1

4.3 PROGRAMMING

............................................

3-1

.............................

...........................................

(8

MHz Crystal Oscillator) 3-1

...........................

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...................................

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........................................

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................................

...................

..................

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...............

............

....................

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3-1

3-3 3-3 3-3 3-3 3-3 3-4 3-4 3-5 3-5

4-1

.

iii

SECTION 5 OPTIONS

CONTENTS

(Continued)

5.1 GENERAL

5.2 OPTION 001.

........................

HIGH STABILITY REFERENCE OSCILLATOR

5.3 OPTION 002. REMOTE ATTENUATION

5.4

OPTION 004, 10 VOLT P-P OUTPUT (Model 51

5.5 OPTION 006, TEMPERATURE COMPENSATED CRYSTAL OSCl LLATOR 5-1

5.6 OPTION 013, UPPER FREQUENCY RANGE EXTENSION

5.7 OPTION 020. TTL OUTPUT

SECTION 6 CONFORMANCE TESTS

6.1 INTRODUCTION

6.2 POWER SUPPLY

...........................................

6.3 CLOCKGENERATOR

6.4 FRONT PANEL DATA (Model 5100 Only)

6.5 SAMPLEGENERATOR

DC

6.6

OFFSET

..............................................

6.7 FRONT PANEL FREQUENCY (Model 51 00 Only)

6.8 REMOTE MODE

................................

6.9 INTERNAL OSCILLATOR

6.1

0

STANDARD ATTENUATOR (Model 51 00 Only)

6.11 PROGRAMMABLE ATTENUATOR (Option 002 Units Only)

SECTION 7 TROUBLESHOOTING

......

..

.........................

10 Only)

...............................

................................

....

.........

..........

5-1 5-1 5-1 5-1

......

5-1 5-1

6-1 6-1

.......................................

.......................

.....................................

6-2 6-2 6-2 6-2

................

..

.......

..................................

..................

.........

6-5 6-6 6-6 6-7 6-7

7.1 INTRODUCTION

..........................................

7.2 TROUBLESHOOTING CHART INSTRUCTIONS 7-1

7.3

PART DESIGNATION AND IC SOCKET NUMBERING 7-1

SECTION

APPENDIX A

STANDARD CIRCUITRY PARTS AND SCHEMATICS

8

8.1 DRAWINGS

8.2 ORDERING PARTS

8.3 ERRATA

OPTION 013. 3

A.l GENERAL A.2 OPERATION

.........................................

.................................................

MHz

FREQUENCY RANGE

................................................

..............................................

APPENDIX B OPTION 020. TTL OUTPUT

B.l GENERAL B-1

................................................

B.2 OPERATION AND CIRCUIT DESCRIPTION

...................

.............

......................

7-1

8-1

8-1 8-1

A-I A-I

B-1

LlST OF ILLUSTRATIONS

Installing Rack Mount Bracket on Model 5100

Instrument Front and Rear Panels Attenuator Response Curves 3-4 Standard Program Line Circuitry 3-5

Rear Panel Programming Connector Zero Phase Line Circuitry

...............................................

Remote.Programming Chart

Loading Timing Diagram

Direct Digital Synthesis Sine Wave Generation

Motherboard Assembly Waveform at Point DC Waveform for FPD

................................................

.................................................

..................................................

A1

...............................................

..................................................

.....................................................

Sample Waveform Generator

DIP Pin Numbering

Basic Timing Signals 7-5 Accumulator Signals

.....................................................

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LlST OF TABLES

7-1 Troubleshooting Chart A-1 Output Signal Characteristics (Option 01 3)

..................................................

.................................

2-1 3-2

3-6 3-6 3-8 3-10 4-1 4-2 6-3 6-4 6-4 6-5 7-2

7-8

7-2 A-1

DRAWINGS

SECTION

5

8

TITLE

Option 001 Assembly and Parts List Option 002 Remote Attenuator Schematic

Option 002 Remote Attenuator Assembly Option 002 Remote Attenuator Parts List

Options 004 and 006 Parts Lists

Final Assembly Final Assembly Parts List

Chassis Assembly Chassis Parts List

Mainboard Schematic Mainboard Assembly Mainboard Assembly Parts List

Attenuator Schematic (Local) Attenuator Assembly and Parts List (Local)

DRAWING

Front Panel Assembly Front Panel Parts List

Final Assembly Final Assembly Parts List

Chassis Assembly Chassis Parts List

Mainboard Schematic Mainboard Assembly Mainboard Assembly Parts List

Front Panel Parts List

Scanner Schematic Scanner Assembly and Parts List

10 Bit DA Converter Schematic 10 Bit DA Converter Assembly 10 Bit DA Converter Parts List

Regulator Assembly and Parts List

APPENDIX A

TITLE

Rear Panel Assembly Rear Panel Parts List

Bottom Cover Assembly and Parts List Side Frame Assembly and Parts List

Option 013 Final Assembly Option 013 Final Assembly Parts List

Option 01 3 Chassis Assembly Option 013 Chassis Parts List

Option 013 Mainboard Schematic Option 013 Mainboard Assembly Option 013 Mainboard Parts List

Front Panel Assembly Front Panel Parts List

Option 013 Final Assembly Option 013 Final Assembly Parts List

DRAWING

APPENDIX

Option 013 Chassis Assembly Option 013 Chassis Parts List

Option 013 Mainboard Schematic Option 013 Mainboard Assembly Option 013 Mainboard Parts List

B

Option 020 Final Assembly and Parts List Option 020 Schematic, Assembly and Parts List

SAFETY FIRST

Protect yourself.

Don't touch the outputs of the instrument or any exposed test wiring carrying the output signals. This instrument can generate hazardous voltages-and currents.

Don't bypass the power cord's ground lead with two-wire extension cords or plug adaptors.

Don't disconnect the green and yellow safety-earth-ground wire that connects the ground lug of the power receptacle to the chassis ground terminal (marked with

Don't hold your eyes extremely close to an rf output for a long time. The normally nonhazardous low-power rf energy generated by the instrument could possibly cause eye injury.

Don't plug in the power cord until directed to by the installation instructions. Don't repair the instrument unless you are a qualified electronics technician and know

how to work with hazardous voltages. Pay attention to the

or death.

Pay attention to the CAUTION statements. They point out situations that can cause equipment damage.

WARNING

statements. They point out situations that can cause injury

Follow these precautions:

@or&.

viii

GENERAL DESCRIPTION

MODELS 51 00 AND 51 10

1.1

Models 51 00 and 51 10 Programmable Frequency Synthesizers provide spectrally pure output frequencies in

0.001 Hz steps from DC to

2

MHz. Model 51 00 may be programmed locally and remotely. Model 51 10 may only be programmed remotely.

A patented* direct digital synthesis technique is used to generate the output frequency directly from an internal crystal reference, which may be phase locked to an external 1 MHz standard, if desired.

In addition to excellent short term stability, digital synthesis also provides other improvements in

perf0.t-mance. Digital operation means inherent programmability and very fast switching. In binary word format, these models maintain

switching between any two frequencies

ing transient) with a programming delay of only 1.5

amplitude and phase continuity in

(i.e., no switch-

ps before switching. Thus, linear frequency sweeping or frequency hopping (including FSK signaling) are easily programmed.

Excellent spectral purity is also possible with digital synthesis since output distortion is determined entirely by the number of bits per sample and the linearity of the DIA converter. Another feature of digital synthesis is the ability to precisely control the phase of the output frequency. The phase may be asynchronously reset to zero at any time for as long as desired (or as little as 125 ns). Hence, for example, sinusoidal bursts are easily produced with each burst beginning at exactly zero phase.

1.2 SPECIFICATIONS

1.2.1 Frequency Range

Resolution Control

0.001 Hz to 2,000,000.000 Hz.

0.001 Hz to

3,000,000.000 Hz (Option 01 3).

0.001 Hz throughout entire range.

Local (Model 5100 Only):

Ten 10-position rotary

switches.

Remote:

*U.S.

Patent

31 bits in binary or 37 bits in BCD format.

3,735,269

1.2.2 Frequency References Model 5100

Internal (8 MHz Crystal):

Standard: TCXO (Same as Option 006 for Model 51 10). Option 001

External, Rear Panel REF Trigger Conditioned Input,

:

High Stability (Oven Controlled).

IN

(TTL Level, Schmitt-

1

TTL Load):

1 MHz Reference: Phase locks to standard or optional

internal reference.

8

MHz Reference: Replaces internal 8 MHz crystal

reference.

Model 5110

Internal (8 MHz Crystal):

Option 001 : High Stability (Oven Controlled). Option 006: TCXO.

External, Rear Panel REF IN (TTL Level, SchmittTrigger Conditioned Input, 1 TTL Load):

1 MHz Reference: Phase locks to optional internal reference.

8

MHz Reference: Replaces internal 8 MHz crystal reference. Required for units without an internal reference.

1.2.3 Output Amplitudes Model 51 00

Fixed Output:

panel

(1 VOLT

Variable Output:

1 Vp-p no load, 0.5 Vp-p into 509. Front

P-P),

rear panel (FXD OUT).

10 Vp-p no load (max), 5 Vp-p into 50R (max). Front panel (OUTPUT), rear panel (VAR OUT).

Model 5110

Fixed Output:

Front panel (OUTPUT

Option 004:

1 Vrms no load, 0.5 Vrms into 50R.

50R), rear panel (FXD OUT).

Replaces 1 Vrms (no load) signal at fixed

output with 10 Vp-p signal.

Models 51 00 and 51 10

Frequency Response (Full Output):

No Load: dc to 500 kHz, + 0.25 dB; 500 kHz to 2 MHz

(3

MHz with Option 01 3), 2 0.5 dB.

5052 Load: dc to 500 kHz, & 0.25 dB; 500 kHz to 2 MHz

(3 MHz with Option 01

Reference Output:

pulse at

TTL

levels. Capable of driving 30

3), + 0.5 to - 2.5 dB.

1 MHz square wave or 8 MHz

TTL

Rear panel (REF OUT).

loads.

1.2.4 Output Level Control

Model 51 00 only

0 to 85 dB attenuation in 1 dB steps (front panel pushbutton) plus

Option 002 (Models

Remote program control (7 bits) of 85 dB attenuation in 1

dB

Attenuator Response to 60 dB (Includes Option 002)

To 500 kHz: + 0.5 dB. >500 kHz: See figure 3-2.

1.2.5 Spectral Purity Spurious Components

Standard:

-

50 dB to 2 MHz.

Option 01

3 MHz.

Harmonic Components (at 1 Vrms)

Standard:

-

45 dB to 2 MHz.

Option 013:

Phase Noise

30 kHz band excluding 1 Hz centered on carrier.

Standard: Options 004 or 013:

RMS Fractional Deviation

10 msec averaging:

with Option 01 3).

1 sec averaging:

Option 01 3).

1.2.6

Via front panel pushbutton or one control bit. Front panel

lamp indicates remote mode.

1.2.7 Switching Characteristics Programming Delay

Update Rate

Zero Phase Reset

1.2.8 GPlB

Remote Mode Selection (Model 51

1.5~~ for BINARY-WORD mode with phase and ampli-

tude continuity maintained.

ps for BCD-WORD mode with output reset to zero

20 phase during delay. 20

ps minimum for four BCD or BINARY bytes with

output reset to zero phase during programming. 625 ns for BINARY-WORD mode. 18 ps for BCD-

WORD and BYTE modes. Output signal may be asynchronously reset to zero

phase via one control bit. There is a delay of approximately 800 nsec to the output. This line may also be used as a load acknowledge output.

Model 1488A-12 provides the following IEEE 488-1 978 functions:

0 to 10 dB front panel continuous control.

51

00 and 51 10)

steps from 0 to

-

70 dB to 100 kHz; - 60 dB to 500 kHz;

3:

-

45 dB, 500 kHz to 2 MHz; - 40 dB to

-

55 dB to 100 kHz; - 50 dB to 500 kHz;

-

40 dB, 500 kHz to 3MHz.

-

50 dB to 2 MHz.

5 x 10

AH1, L1 (listen only), DT1. Programs

85

dB.

-

40 dB, 2 MHz to 3 MHz.

5 x 1 0-7, dc to 2 MHz (3 MHz

-

91

dc to 2 MHz (3 MHz with

00)

frequency (phase continuous) and amplitude (with option 002) as well as all ZERO PHASE modes.

1.2.9 General Environment

Operating Temperature: Storage Temperature:

Dimensions

43.2 cm (1 7 in.) wide; 8.9 cm (3% in.) high; 33 cm (1

3

in.) deep.

Weight

9.6 kg (21 Ib) net; 11.4 kg (25 Ib) shipping.

Power

1 151230V + 1O0/o1 50 to 60 Hz, 65 watts.

1.2.1 0 Options 001:

8

MHz, High Stability Crystal Reference

(Oven Controlled)*

Temperature Stability: Aging Rate:

002: Remote Programmable Attenuator

Range: Programming Delay:

004: 10 Vp-p Output

Model 51 10 only. Not available with Option 01 3.

006: 8 MHz, Temperature Compensated Crystal Reference

(Standard on Model 51 00.)

Temperature Stability: Aging Rate:

01 3: Frequency Range Extension

Original order only. Not available with Option 004.

Frequency Range: Frequency resolution:

51 00 Local).

Variable Output (Model 5100 Only):

mum no load, 0.5 Vrms maximum into 50R load. 50R source impedance.

Variable Output Signal (Model

table

020: Rear Panel

Provides a VAR OUT BNC on Model 51 00. See paragraph 1.2.1 for range and resolution specifications.

GPlB

Use Model 1488A-12 adapter.

1.2.1 1 Accessories Rack Adapters

Programming

**Specifications apply after a

0 to 85 dB in steps of 1 dB.

A-1

.

TTL

*.

+

2 x 10- glday.

+.

5 x 1 0-6/year.

TTL

Output

compatable square wave. Replaces

~onnedor

0" to + 50°C.

-

20"

to + 70°C.

+

1 x 1 0-8, 0" to + 55°C.

Typically less than 5ms.

&

1 x 1 0-6, 0" to + 55°C.

0.001 Hz to 3 MHz.

0.001 Hz (Remote and Model

1

Vrms maxi-

5100

Only):

72

hour warm-up period.

See

I

1

(

1

I

2.1 INSPECTION

This instrument was carefully inspected and tested prior to shipment. It was operated for at least 100 hours to reduce the probability of early failure. The instrument should be inspected for physical damage incurred in transit. When receiving a shipment from a carrier, inspect the shipping carton in the presenceof the carrier. If rough handling is evident take exception on the delivery receipt before accepting the shipment.

2.2

POWER REQUIREMENTS

This instrument will operate on 115 Vac

50-60 Hz or 230

Vac

(

2

10%) 50-60 Hz, selectable via

(1

10%)

a rear panel switch. The instrument is equipped with a three-wire power cable which connects the chassis to earth ground when plugged into If a two-contact outlet is used in conjunction with a

a

three-contact outlet.

threeprong and two-prong adaptor, the pigtail of the adapter should be connected to earth ground.

If no carton damage is obvious, but physical damage is discovered when the carton is opened, preserve the carton and packing materials, notify the carrier immediately and have them perform

a

written inspec-

tion of the carton and the contents. It is recommended that the initial conformance test pro-

cedure be performed on receipt as described in paragraph

2.4.

2.3

INSTALLATION

WARNING

Rack mount brackets are to prevent the instrument from sliding when mounted in rack. They are not intended to support the

weight of the instrument and should never

be used for lifting or carrying.

a

RACK

MOUNT'

BRACKET

THESE

EDGES

Figure 2-1. Installing Rack Mount Bracket on Model 5100

51

2.3.1 Model

Model

51

assembled for bench

00

00 Frequency Synthesizer was factory

use.Toconvert the instrument for mounting into a standard 19 inch wide rack, the following procedure should be followed. (Refer to figure 2-1

.)

1 . Unplug instrument from ac power source.

2.

Stand instrument on one side.

3.

Align rack mount bracket with raised edge of instrument as shown.

4.

Holes on rack mount bracket should correspond to pem nut holes just underneath black trim strip. Use a pointed object to pierce the black trim strip at the pem nut holes.

5.

Use lock washers and metal screws provided to secure rack mount bracket.

6.

Repeat for other side bracket.

Instrument is now ready for rack installation.

2.3.2

Model 51 10

Model 51 10 Frequency Synthesizer is ready for installation into a standard 19 inch wide rack.

2.4

INITIAL CONFORMANCE TEST PROCEDURE

To verify that the instrument is operational, the following procedure is recommended. If trouble is suspected, then refer to the troubleshooting section in this manual.

Phase lock the unit and a frequency counter to a com-

mon frequency reference.

A 1 MHz output signal from the REF OUT connector may be used as a reference input to the counter, or a

1

MHz output from the counter may be used to phase lock the unit. For details, refer to paragraph

3.3.3.

Connect the OUTPUT jack of the unit to the counter and verify that the counter is triggered. Program a frequency of 1

,I 1 1 ,111 -000 Hz and verify on the counter. (A count

of

,+

1 from the true value is acceptable.) Repeat this

procedure for 1,222,222.000 Hz, etc.

.

3.1 INTRODUCTION

Figure 3-1 shows the front and rear panels of the instrument with controls and connectors identified. Model 5100 may be controlled locally with the front panel switches or remotely via the rear panel programming connector. Model 51 10 is controlled only via the rear panel programming connector. Frequency is programmable on all units, while attenuation is programmable on Option 002 equipped units only.

3.2 POWER SWITCH AND INDICATOR

The front panel POWER switch controls ac line power

to the unit. The green POWER indicator verifies the presence of the 5 V supply for the digital logic circuitry.

NOTE

For units equipped with' the high-stability

proportional-oven crystal (Option

be

must least drift performance of the crystal are to be

realized.

3.3 SYSTEM CLOCKS

For the instrument to function, it must have a system clock derived from either an internal or external reference. In addition, the internal reference may be phase-locked to an external 1 MHz input signal, and two or more instruments may be phase-locked together.

3.3.1 Internal Reference

The Model 51 00 contains either the standard or optional

(Option 001) internal

The standard Model 51 10 is not supplied with an inter-

nal reference oscillator, but may contain either Option 001 or 006,

To enable any internal crystal reference oscillator, the

lnput Reference Selector Jumper, located inside the unit on the main board (figure 5-1) must be in the INT position. If no external signal is connected to the REF IN jack, the internal crystal frequency may be adjusted as described in paragraph

Procedure.

maintained

72

hours prior to use if full accuracy and

8

MHz reference oscillators.

(POWER

(8

MHz Crystal Oscillator)

8

MHz crystal reference oscillator.

6.7

of the Conformance Test

001),

power

indicator on) at

3.3.2 External Reference (REF IN Signal)

Any internal 8 MHz crystal reference installed in the unit

1

may be either phase-locked to an external reference signal, or completely replaced by an external

8

MHz signal, which becomes the system clock. An external 8 MHz reference signal is required for Model 51 10 units without an optional internal reference oscillator. For external the INPUT REFERENCE SELECTOR JUMPER located inside the unit on the main board (drawing 002-004-31 00) must be in the EXT position. The rear panel BNC jack labeled REF IN accepts either the 1 or 8 MHz external

reference input signals.

The absolute maximum voltage limits of the external

reference input signal are 51 00, and the signal source is one standard TTL load. A TTL Schmitt-trigger circuit conditions the input signal to be

a

hysteresis output signal with a positive-going threshold

of

+

-

0.6V minimum. The input signal waveform must cross

both thresholds for 50 ns, minimum, once per cycle.

If the REF IN signal is to be the system clock, the input frequency must be between dc and 8.1 MHz. The deviation of the output signal frequency is directly proportional to the deviation of the system clock from tion at frequencies below

rate; the internal low pass filterwhich removes sampling

components from the output signal is designed for an

8

MHz sampling rate and becomes ineffective as the sampling rate is lowered. To maintain full harmonic and spurious distortion specifications, an external low pass filter is required to eliminate these components.

3.3.3 Phase-Locking to an External 1 MHz Standard

For phase-locking to an external standard, the instrument must be equipped with an internal crystal reference. The lnput Reference Selector Jumper shown on

main board assembly drawing 02-004-31 00 in section

8

must be in the INT position, enabling the internal crystal reference as the system clock. If a 1 MHz signal is connected to the rear panel REF IN jack, the internal reference will phase-lock to this signal. The pull-in range

+

5.0 V peak for the Model 51 10. Burden on

2 V maximum and a negative-going threshold of

8

MHz reference input operation,

&

5.5 V peak for the Model

8

MHz. Opera-

8

MHz implies a lower sampling

MHz

1. MHz Frequency Switch

2. KHz Frequency Switches

3.

Hz Frequency Switches

4.

mHz Frequency Switches

5.

1

VOLT P-P Signal Jack

6.

OUTPUT Signal Jack*

7.

LEVEL Control

8.

Attenuator Switches

9.

REMOTE Mode Indicator

10. REMOTE Switch

11. POWER Indicator*

12. POWER Switch*

3-2

1. Output Signal Jack REFerence OUTput*

2.

3.

High Stability Crystal FREQ. ADJUST*

4.

Ext REFerence INput*

5.

PROGRAMrning INput Jack* 10. FiXeD Amplitude OUTput Signal Jack*

1. All items included on Model 5100.

2.

*Deno.tes Items included on the Model 5110.

Figure 3-1.

Instrument

6.

Fuse Holder*

7.

Line Selector Switch*

8.

Line Cord*

9.

Standard Crystal FREQ. ADJUST*

NOTE

~r6nt and Rear Panels

(

of the phase-locked loop is k 2 Hz. The input signal

waveform must enter the limits of logical

"0" and logical

"1 " (each for a duration of at least 50 ns) once per cycle.

As a check of proper phase-lock operation, follow paragraph 6.8 of the Conformance Test Procedure.

Failure to lock could be due to an excessive difference

between the internal and external reference frequencies.

3.3.4 Phase-Locking Two or More Instruments

.

(51 00 and 51 10)

To phase-lock two or more instruments, use the 8 MHz

reference output from a master instrument as an external 8 MHz clock input to the slave

instrument(s). All slave instrument phase-locked loops are bypassed because they are driven directly by the single crystal reference of the master instrument, which itself may be phaselocked to an external

1 MHz signal, or driven by an 8 MHz

input signal.

The

lnput Reference Selector Jumper located inside the

unit on the main board (assembly drawing

02-004-31 00)

must be in the INT position for the master unit, and EXT

for the slave

3.4 OUTPUT SIGNALS

unit(s).

Main output and reference signals are available from Models

variable (Model

51 00 and 51 10. The main outputs are fixed and

51 00 only) amplitude sine waves, at the

programmed frequency. Reference frequency outputs

1 MHz square or 8 MHz pulse signals derived from

are the system clock.

3.4.1

Model 51 00 Main Outputs

Main output signals available from the Model 51 00 are

fixed amplitude

(I Vp-p) and variable amplitude (1 OVp-p

maximum) sine waves, at the programmed frequency.

3.4.2 Model 51 10 Main Outputs

Main output signals available from the Model 51 10 are

fixed amplitude

1 Vrms, (1 OVp-pfor units equipped with

Option 004) sine waves, at the programmed frequency.

3.4.2.1 Model 51 10 Fixed Amplitude Outputs

The Model 51 10 output signal (at the programmed fre-

quency) is available from the front panel BNC jack labeled OUTPUT 50R and

from the rear panel jack labeled FXD OUT. The source impedance is 50R and the amplitude is nominally

1 Vrms with no load, or 0.5 Vrms

into 50R. For units equipped with Option 004, the OUTPUT

509 and FXD OUTsignal amplitudes are increased to 10 Vp-p (3.6 Vrms) with no load, or

5Wp-p into 509 (nominally). Option 004 also increases harmonic components (see paragraph

3.4.3

The rear panel

1.2.5).

Models 51 00 and 51 10 Reference Output Signals

REF

OUT signal can be either a 1 MHz square-wave or an 8 MHz pulse waveform, as determined by the Output Reference Selector Jumper shown in drawing Model either the internal Selector Jumper set to INT), or an external (jumper set to EXT). The Model

to the

generated if the

02-004-31 00, Mainboard Assembly. For the

51 00, the source can be an 8 MHz signal from

8

MHz reference (Input Reference

8

MHz signal

51 10 works identically

51 00, except that no 8 MHz REF OUT signal is

8

MHz reference signal is from an external source. The instrument is shipped with the Output Reference Selector Jumper in the

The output is a buffered

TTL

signal capable of driving

1 MHz position.

30 standard loads.

3.4.1

.I

Model 51 00 Fixed Amplitude Outputs

The Model 5100 front and rear panel jacks labeled

1 'VOLT

P-P

wave signals (at the programmed frequency) which may be used for scope synchronization or frequency monitor-

ing. The source impedance is 50R and the amplitude is nominally

1 Vp-p with no load, or 0.5 Vp-p into 50R. The

LEVEL and ATTENUATION settings have no control of

the output amplitude.

3.4.1.2 Model 51 00 Variable Amplitude Outputs

The Model 51 00 front and rear panel jacks labeled OUT-

PUT and VAR OUT, respectively, provide the main sine wave output signal (at the programmed frequency) from the instrument. The source impedance is

maximum amplitude is

into

50R, as determined by the LEVEL and ATTENUA-

TION control settings.

and FXD OUT, respectively, provide sine

509 and the

10 Vp-p with no load, or 5 Vp-p

3.5 REMOTE SWITCH AND INDICATOR (MODEL 51 00 ONLY)

The Model 51 00 is always operating in either the local

or remote mode, as indicated by the amber REMOTE lamp on the front panel. The REMOTE switch must be in the OUT position for local mode operation. Remote mode operation may be effected in two ways:

1. By setting the REMOTE switch to the IN position.

2. By setting the programming line REMOTE to the

proper state. Thus, the unit may be called into the remote mode by either front- or rear-panel control.

Local mode operation requires that neither

(1) or (2)

above be present.

3.6 LOCAL MODE OPERATION (MODEL 51 00 ONLY)

All local frequency and attenuation control is derived

from the front panel switches.

3.6.1

Local Frequency Control

The Model 5100 output signal frequency is set directly by the ten front panel rotary switches. Any frequency from 0.001 Hz to 2,000,000.000 Hz is available in increments of 0.001 Hz. All switches (except the MHz switch) have 12 positions with no stops to limit rotation. The two unmarked positions on the knobs which correspond to

"1 0" and "1 1 " are actuallyvalid positions with the following restriction: the combined settings of the three switches in each range of 1 000

(mHz, Hz, and kHz) may not exceed 999. For example, if the three "Hz" switches are set left to right as put frequency is given by:

"1 1

"

x

1 = 91 1 Hz. An example of an invalid setting

for the same three switches is

"8", "1 O", "1 1

"8"

x

100 + "1 0" x 10

"9", "109', "1 1" which

",

the out-

+

totals 101 1 Hz, exceeding the limit of 999. The MHz switch has two positions. To set a frequency

of

2,000,000.000 Hz, the MHz switch is set to 1 and

the 100 kHz switch is set to

"1 0". This is the only frequency which requires the use of an unmarked switch position.

When any frequency switch is changed on the Model

51 00, the output signal will momentarily drop

tozero volts

dc before the new frequency appears. The duration of

this so-called "zero phase" portion depends primarily 0n the bounce time of the switch contacts but will be

3-5

ps

always

3.6.2

frequency

start

at

zero

phase.

Local Attenuation and Level Control

waveform

will

The

new

The ATTENUATION switches on the Model 51 00 front

panel may be used to attenuate the

0

to 85 dB in steps of 1 dB. Any combination of switch

OUTPUTsignal from

settings is valid; the total attenuation is equal to the total of the weights of the switches set to the IN position. There is some degree of

rolloff of attenuation at the higher frequencies. Figure 3-2 shows the actual attenuation as a function of frequency.

The LEVEL control on the Model 5100 provides con-

tinuous amplitude control of the OUTPUT signal from

0 dB (fully clockwise) to 10 dB (fully counter-clockwise) attenuation relative to the attenuator setting. An output impedance of 50R is maintained over all ATTENUATION and

LEVELcontrol settings. The maximum amplitude of

the Model 51

OOfront panel OUTPUTand rear panel VAR

OUT jacks is 10 Vp-p.

(DB)

0

-

(MHz)

.2

I

.4

.6

I

.8

I

1

.O

I

1.2

I

1.4

I

1.6

I

1.8

I

2.0

-

0

')

Figure

3-2.

Attenuator Response Curves

\

REMOTE MODE OPERATION (MODELS 51

3.7 AND 51

The programmable functions of these instruments are frequency, zero-phase point, and with Option 002, (see paragraph 5.3) attenuation. Programming data is latched internally at the time of the LOAD pulse and need not be held valid except at that time. The precise switching characteristics of the instruments allow accurate amplitude gating, frequency sweeping, and frequency hopping (FSK).

3.7.1 Programming Lines

All remote programming lines enter the 50-pin connector on the rear panel, and, except for the zero phase line, have the input circuitry shown in figure 3-3. Each programming line must sink a maximum of 4.8 connected to ground potential. If a line is left uncon-

nected, it will be internally pulled to by the 3.3 KR pull up resistor and therefore may be programmed via contact closure to ground for logical and open for logical "1

The programming lines can be divided into two categories: to set data format, initiate loading, etc. The data lines set the value of the frequency or attenuation.

The pin numbers shown on the connector and its mat-

ing plug (supplied) are identified in figure 3-4. Lines through A7 determine the attenuation (Option 002 only);

N1 and N2, the loading format; and Po through Z,, the frequency. REMOTE, LOAD, and ZERO PHASE

lines are control lines.

10)

+

5 V (logical "1

".

controllines and data lines. Control lines are used

3.3

K

pull-up resistor

00

mA when

")

"0"

A1

Y,

and

i

Input Line

(i~~ical)

Figure 3-3. Standard Program Line Circuitry

!

4.8

ma

I

I I

I

L,----------,,-l--,,,II

Max

1

or 2 standard TTL loads

INTERNAL CIRCUITRY

All lines require positive logic with standard TTL levels:

logical

2.0

3.7.1

The REMOTE Line is used as a device select or a load

enable ine. As described in paragraph 3.5, the instrument may be called into the remote mode either by the REMOTE switch on the front panel (Model 51 00 only) or via the programming line REMOTE.

With this line in the logical local mode selection is determined by the REMOTE switch; in the logical the remote mode, regardless of the position of the REMOTE switch.

For the Model 51 10, if the REMOTE line is in the logical

"0" state, it will respond to data sent over the bus. With the REMOTE line at logical defeated, and the unit operates as previously loaded. If this line is not to be used on the Model 51 10, then it should be hardwired to logical

"0" is from 0.0 V to 0.8 V and logical "1 " is from

V

to 5.5 V, all referenced to the GND line.

.I

REMOTE Line

"1 " state, Model 51 00 remotel

"0" state, the instrument is in

"1

",

all programming is

"0"

or common ground.

NOTE

The ZERO PHASE line will operate regardless of the state of the REMOTE Line.

3.7.1.2 ZERO PHASE Line

The ZERO PHASE line circuitry is shown in figure 3-5.

It may be used both as an input and as an output. As an

input, the line is normally at logical

logical

is reset to the zero-phase state, causing the output

signal to go to

"1

point. The minimum duration of the logical

is 125 ns, and there is approximately OUTPUT jack.

Ttie instrument may be used to generate an amplitude

gate waveform by driving the ZERO PHASE line with a

pulse generator; each gated interval is identical in phase

content. All transients are spectrally limited to a 2.5 MHz

bandwidth by the

Every time the instrument changes frequency (except with phase-continuous programming), the internal cir-

cuitry causes the ZERO PHASE line to go to logical

during the processing time of the newly-loaded data. Thus, as an output, this line may be used to monitor the

internal status of the data processing circuitry.

"0" on this line, the internal sample generator

OVdc. When this line is set back to logical

",

the output waveform resumes at the zero-phase

lowpass smoothing filter.

"1

".

By setting a

"0" interval

1.5~s delay to the

"0"

TOP ROW

1 2. 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

I'

\

ATTENUATOR

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

--

I

1

FORMAT

MHz

BOTTOM ROW

I

mHz

FREQUENCY

Notes:

1.

All signals are referenced to pin

2.

All lines are internally pulled to

3.

See figures

3-6

Figure

for programming chart.

3-4.

Rear Panel Programming Connector (Rear View of Instrument)

50

+5V

COM

by

GND.

3.3

kR

resistors and assume logical "1" level

KHz FREQUENCY

1

Hz FREQUENCY

if

connected.

PHASE

O+

7.2

ma

MAX

~OO~~MAX~

:-I

Figure

+5

VDC

8

MHz CLOCK

1

K

I

C

Q

D

FLIP-FLOP

---------------

75451

DRIVER

3-5.

Zero Phase Line Circuitry

I

ACCUMULATOR RESET

7474

INTERNAL ZERO PHASE COMMAND

i

I

\.

"wired-or" bus. Internally, it is pulled to + 5V through 1 kR resistor and to ground through a saturated NPN transistor

The ZERO PHASE line is electrically similar to a DTL

capable of sinking 200 to logical

"0" through a low impedance path to ground

mA. Externally, it may be pulled

bytes sequentially. The weights of the lines may be either

" 1 "

BCD or binary. Positive logic is used: a logical

on any of the lines will cause a contribution to the frequency equal to the weight of that line. Each of the four modes

is described below and summarized in figure 3-6.

(switch, diode, transistor, etc.) and may be set to logical

"1 " by opening this path. Ideally, an external driver should

3.7.1.4 Data Lines

only sink current from the line to ground. However, it must never source more than 200

Phase Control

mA to the line.

The frequency range of the unit is from dc to 2 M.Hz, with

mHz resolution throughout. Frequency data is divided

1

into four ranges: The zero phase line is sampled every 125 ns by the D flip-flop shown in figure 3-5. The output of this flip-flop controls the accumulator reset line. When this line is at

logical

"O", the phase value of the phase accumulator

is set to zero degrees. When the line returns to logical

"I

",

the phase accumulator begins advancing in value

from the zero degree point.

Range Minimum

mHz

OmHz 999mHz

Hz 0 Hz

kHz

0 kHz

Maximum Resolution

1 mHz

999 Hz 1 Hz

999 kHz 1 kHz

There is a time uncertainty of up to 125 ns between the zero phase signal and the accumulator reset signal. The

MHz

0 MHz

1 MHz 1 MHz

duration of the accumulator reset signal will be an

integral number of 125-ns periods. Typically, there is a

delay of 1.5

ps between the zero phase line signal and

the synthesizer output response.

Load Acknowledge

As an output line, the zero phase line will acknowledge the loading of program data as described in paragraph

3.7.2.2. The internal NPN transistor will pull this line to logical

"0" during the processing cycle, causing a zero

phase interval in the output signal.

3.7.1.3 Control Lines

The control lines are: ZERO PHASE, REMOTE, LOAD,

N1 and N2. The ZERO PHASE line is discussed in

The programming chart in figure 3-6 shows how data is

formatted and weighed in each mode.

Binary Word

In this mode, N1 = N2 = logical "0" as shown in the

MODE SELECT column in figure 3-6.

All lines are loaded with a single load pulse. The weight of each program line is shown beneath each line designation. Any binary numberlessthanorequalto999,, = 1111100111,is valid for each of the three frequency ranges (kHz, HZ, and mHz). The lines Y,, Y,,

V,,

S, and S, are unused in this mode and may be left unconnected. Any lines which are always to be logical "0" are simply hardwired to

paragraph 3.7.1 -2. GND.

LOAD Line

The LOAD the programming lines into the internal data register. This

line is normally at logical negative-going pulse causes a load. The positive-going

edge is ignored with the restriction that the pulse width

is 50 ns minimum.

Data Formats

There are four basic formats for loading data: BINARYWORD, BCD-WORD, BINARY-BYTE, and BCD-BYTE. The format is programmable via bits

are entered along with other data at the time of the LOAD

pulse. The word mode permits loading of all data with a single load pulse, while byte mode allows the user with a limited number of programming lines to load four 12-bit

line is used to transfer programming data from

"1 " and the falling edge of a

N1 and N2 which

The binary-word mode is the only programming mode which maintains phase and amplitude continuity between frequencies. Frequency sweeping is easily accomplished by causing repetitive loads of successively higher (or lower) frequencies. Although the frequency changes are indiscrete steps, each

stepcan be as small as 0.001 Hz allowing a close approximation to a linear sweep in most applications.

The delay from the negative edge of the LOAD

pulse.to the change in frequency at the OUTPUT jack is approximately 1.5 ps. LOAD pulses may be accepted at a maximum rate of one per 0.625 ps. Data must be held valid until at least

LOAD pulse. The ZERO PHASE line is logical

0.625~s after the negative edge of the "1 " dur-

ing all binary-word loads. These conditions are indicated

on

the timing diagram in figure

3-7.

MODE

SELECT

ATTENUATOR

I

FREQUENCY

BINARY WORD

BCDWORD

BINARY

BCD

BYTE

0

1

0

11

40

0

40 2

0

4020

1

4020108

20 10

10

20

10

8

DB

8

DB

8

DB

64

2

'-1

1

,

I

j

I

1

I

i

I

i

64

32

4

1

2

1

2

11

2

1

+

MHz

1

800400200100

MHz

1

MHz

512256128

f

KHz

40 10 80

KHz

16

20

4

8

4

8

*

800400200100

512256

128

80

32

Hz

20

Hz

16

10

8

4

8

4 2

1

f

1

2 2

800400200100 40

Ik

*

f

800

.f

*

400

512256

572

256

512

256

512

100

200

100

128

80

128

80

64

mHz

40

mHz

64

mHz

64 128

64

KHz

40 200 80

mHz

40

Hz

32

20

10

16

10

16

32

4

8

4

4 8

4

8

4 8

4

8

1

2

1 20

,

1

SINGLE

LOAD

1

LOAD 2

LOAD

3

4

1

LOAD 2

4

2 8

1

LOAD

3

1

111

I

2

*

1

NOT

LOAD

USED

4

I

8

10

800

400 40

--

-

--

100

80

20 200

KHz

Figure

4

3-6.

Remote Programming Chart

In this mode, N1 = logical "0" and N2 = logical "1

".

Programming lines are weighted in BCD code and are analogous in format to the front panel frequency switches on the Model any of the three ranges (kHz, Hz, and

999;

exceed

otherwise, any combination of weights is

51 00. The total of the weights in

mHz) cannot

valid. For example, the frequency 150 Hz could be programmed with several different sets of data: (1)

+

40Hz + 10Hz1(2)100Hz + 40Hz + 8Hz + 2Hz,

100 Hz

(3) 80 Hz + 40 Hz + 20 Hz + 10 Hz, etc. By properly choosing data

lines, the number of active programming

lines may be minimized in certain applications.

Data must remain valid for at least 4.5

ps after the

negative-going edge of each LOAD pulse. The internal

data processing circuitry requires a maximum of

18.0 ps

to process the BCD data after a load. During the last

13.5

ps of this interval, the ZERO PHASE line will go to zero volts. The instrument is ready to receive a new load after this time, as shown in figure 3-7.

BCD-Byte and Binary-Byte

The byte loading mode is provided expressly for the user who has a limited number of data lines. Four

are required, each byte being loaded in

form. The first byte loads the mode select bits

N2),

the attenuator bits (A1 through A7, Option 002 only)

and the

1 MHz bit

(Z,)

on the lines shown in figure 3-6.

12-bit bytes

12-bit parallel

(N1

and

A LOAD pulse causes loading of this data and initiates

a wait cycle holding the ZERO PHASE line (and OUTPUT

signal) at zero until the next three bytes have been loaded

and processed. Data must be held valid for at least 4.5

ps

after the first LOAD pulse.

The remaining three bytes program the

in that order, as shown in figure 3-6. Each range

mHz, Hzand kHz

(mHz,

Hz, and kHz) is constrained exactly as in the word modes.

The fourth LOAD pulse initiates processing of all loaded data after which the new signal appears at the output jacks. Data must be held valid for at least 375 ns after each of the last three LOAD pulses.

Since the first byte and the remaining three bytes are loaded on two separate sets of lines, the user may tie

these two sets in parallel, allowing a single set of

10 or 12 lines to serve for all byte inputs. ~hese sets of lines are arranged adjacent to each other on the rear panel

connector (see figure 3-3) so that pins may be easily connected to pins #26 through respectively. Pins #36 and

#37

are then included with

#I through #I 0

#35,

the above ten lines to form a total of twelve for BCD bytes.

Note that if binary format is used, these latter two lines may be omitted, thus requiring a total of only ten lines

for data input.

3.7.2

Remote-Local Mode Transitions (Model Only)

51

00

The characteristics of switching between local and

remote modes on the Model

51 00may be useful in some applications. When switching from local to remote modes, no change occurs in frequency (or attenuation)

until the first LOAD pulse is received. If, however, at the

time of entering the remote mode the LOAD line is at

logical

"O", the instrument will thereupon load the pro-

gram data. In order to load new data, either the LOAD

line must go to logical "1

"

and then back to logical "O",

or the instrument must go to local mode and back to

remote mode. Whenever local mode is entered, the instrument immediately returns to the current front panel setting. Therefore, if the user wishes to switch between twofrequencies, he could set the first on the front panel and the second on the program lines. With the LOAD line at logical

"Ow, switching between local and remote modes would then alternate the frequencies. The transition into local mode is identical in character to a BCD-word load and the timing diagram of figure 3-7 applies, substituting the remote condition for the LOAD signal.

Another application may require transitions from one frequency to another without the relatively complex amplitude and frequency transients encountered in rotating the front panel switches to change

frequency.This may be done on the front panel without resorting to remote programming. To change frequency, enter the remote mode with the REMOTE button and set the frequency switches to the new frequency. Changing the switches

will have noeffect. Push the REMOTE button, again bring-

ing the instrument back to local mode. The frequency

will change to the new setting. This routine is equivalent

to remote programming in the BCD-word mode. With Option 002, the attenuator may be controlled in the

same manner as the frequencysetting described above.

BINARY WORD MODE

LOAD PULSE !NTERNAL READY*

HOLD DATA VALID*

ZERO PHASE OUT

OUTPUT SIGNAL

0'625

ps

MAX

--.!

I

!

I

L

I

0.8 ps

TYPICAL

LOGICAL

"1"

-

LOGICAL

-

LOGICAL

7,

"1"

"0"

BCD WORD MODE LOAD PULSE

INTERNAL READY*

HOLD DATA VALID* ZERO PHASE OUT

OUTPUT SIGNAL

BCD OR BINARY BYTE MODE

LOAD PULSE INTERNAL READY*

HOLD DATA VALID* ZERO PHASE OUT

OUTPUT SIGNAL

/VVVVWI

4.5 ps

MAX

I

1

4

II

I

7

II

*;

9

I

Ic

I

p-

I

b-

4

I I

I

'.-4.5~~

'

I

p

0.8 ps

13.5~~

0.8 ps

TYPICAL

<

>

I

tr

11

)>

II

I

-+I

(t.375 ps

I I

SH-5

TYPICAL

d

Sj++

<c

>>

!

i

I

-d

I

11

I1

4

l

I

C

I

(e

1

I

0.8~

<e

2>

.375 ps

-3

TYPICAL

I

II

'1

11

1

I

r.

.375 ps

I

1

I

+

6-

0.8 ps

I

TYPICAL

I

*Not available for customer observation. Shown only to illustrate timing.

NOTES:

1.

All waveforms except output signal are shown with standard TTL levels.

2.

When internal ready is at logical

"1"

a new load pulse will

be accepted.

3.

Data must be held valid during the logical

"1"

portion of

hold data valid.

4.

Positive-going edge of load pulse is ignored except logical

"0"

interval is

Figure

50

nsec min.

3-7.

Loading Timing Diagram

CIRCUIT

DESCRIPTION

4.1 SlNUSOlD GENERATION

Models 5100 and 51 10 utilize direct digital synthesis techniques to generate the output sinusoid. Samples of the sinusoid are digitally generated at an

8

MHz rate and are then converted to analog form by a Digital-to-Analog Converter (DAC) and a smoothing Low Pass Filter (LPF) cutting off at approximately 2.5 MHz. The amplitude of the digital samples is represented with

11 bits (including sign), and the phase accuracy of each sample is

+

0.09'.

4.2 FUNCTIONAL BLOCK THEORY

Figure 4-1 is a composite block diagram of the units. The 8

MHz system clock is derived from either an external signal or a temperature-compensated Crystal-Oscillator Reference (proportional oven control with Option 001). The frequency stability of the output sinusoid is related directly to that of the system clock. Mechanical adjustment of the internal crystal frequency is provided to compensate for long-term aging effects, and the crystal oscillator may also be phase locked to an external 1 MHz reference (which is within

+

2 Hz of the internally derived 1 MHz). Since excellent short-term stability is provided by the internal crystal reference, the function of the external-reference phase-lock loop is only to provide

proper bias to the crystal, and hence, the loop bandwidth

is

fairly

broad

(approximately

lo

Hz).

The frequency value of the output sinusoid is stored in

the Frequency Register in binary form with each 3-decade group (kHz, Hz, and

mHz) represented by a separate 10-bit binary number (see figure 4-2). A separate flip-flop stores the MHz bit. If the unit is remotely programmed in this binary form, then no numerical conversion is required, and the output frequency changes

with no discontinuity in phase or amplitude. The delay

from the programming inputs to the analog output in this mode is approximately 1.5

ps.

4.3 PROGRAMMING

If the unit is programmed in BCD either locally (via the Model 51 00 front panel) or remotely, then BCD-to-binary conversion is required, and the output is reset to zero phase (and thus zero volts) during theconversion period. Remote programming in either BCD or binary can also be accomplished in four 12-bit bytes,

(1 0 bits for binary) if the number of input lines is more important than programming speed.

Instrument schematics are in section

8.

VOLTAGE

CONTROL

UCTERNAL REFERENCE

(1

MCCq

lllMllu

CRYSTAL SAMPLE OSU UTOR REFERENCE LOGIC CONVERTER

.

"","

C

GENERATKN

*

LOW

PASS

FILTER REGISTER

A

PHASE BCDTO

DETECTKN

-

+8

-1

MHZ BINARY

I

L

-,-------

FREQUENCY

BCD l BINARY

Figure 4-1. Direct Digital Synthesis

FiXW

PANEL

51

10

ONLY

r----I

,

.LL

---A

I

PROGRAMMING

I

J

t

INPUT

DIGITAL

ANALOG

READ

ONLY

MEMORY(R0M) ADDRESS AS A

FUNCTION OF

SINEWAVE PHASE

0" 45O

ROM is arranged in 512

1. sine function from

through 51 1 store

Above graph shows how ROM is addressed to produce

2. ROM provides negative operation for

With front panel setting of 4 kHz address is incremented one step per 125 nsec

3.

sampling rate. Each address step corresponds to a phase step of 0.18". During one sine cycle there are 2,000 samples (2,000

4. Each of the nine address bits may be monitored and verified by displaying DAC-1 on scope. See paragraph 6.4 and figure 6.4. DAC-1 has positive edge at

sinewave and negative edge at 180".

put Non-conforming address bits may be due to defective U69,

5. accumulator malfunction.

Signals DAC-4 through DAC-11 are generated directly from the eight output bits of the

6.

ROM. DAC-2 and DAC-3 are synthesized from DAC-4 and ADR 8 through ADR 5. DAC-1 is

derived directly from the accumulator.

90"

x

0" to 90". Addresses 6 through 255 store 0" to 45" and addresses 262

45" through 90".

Address Bits Location Weight

135"

OUTPUT

8 structure. 500 words are used to store relative magnitude of

x

1

80°

SINEWAVE

NOTE

180" to 360".

0.18" = 360")

225"

270'

PHASE

360" sinewave. Inversion after

0" phase of the out-

U78, U85. Otherwise check

Address Examples

38

144

265

31

=

5"

360"

ADR 0 (MSB) ADR 1

ADR 2 ADR 3 ADR 4 ADR 5 ADR 6

7

ADR ADR 8 (LSB)

Logical "1" Logical

"0" = 0.0 to 0.8 Volts.

Figure

=

2.0 to 5.0 Volts.

4-2.

sinehave Generation

5.1 GENERAL

This section contains information pertaining to options

available for Models 51 00 and 51 10.

5.2 OPTION 001, HIGH STABILITY REFERENCE OSCILLATOR

Option 001 is the most stable of the oscillators available for Models 51 00 and 51 10. It uses a crystal with proportional oven control to obtain its excellent stability. See paragraph 1.2.1 0 for temperature stability and aging rate specifications and assembly drawing 02-002-3031 in this section.

5.4 OPTION 004,lO VOLT P-P OUTPUT (Model 51 10 Only)

Option 004 increases the Model 51 10 fixed output amplitude from 1 Vrms to 10 Vp-p. Compatable with Option 002, but not available with Option 01 3.

5.5 OPTION 006, TEMPERATURE COMPENSATED CRYSTAL OSCILLATOR

Though not as stable as Option 001, Option 006 is sufficient for most applications and is standard on the

0

Model 51 00. See paragraph 1.2.1

stability and aging rate specifications.

for temperature

1

5.3 OPTION 002, REMOTE ATTENUATION

With Option 002 installed, attenuation of the OUTPUT signal as described in paragraph 3.6.2 is fully programable. The format is shown in figure 3-6, and loading of the attenuation bits occurs at the same time as the frequency bits. Positive logic, as described in paragraph

3.7.1.3 (Data Formats), is used. Internal registers store

the data and drive miniature relays to switch the appro-

priate resistor networks. The settling time of the relay

contacts is typically less than 5 ms.

Protective circuitry insures that when switching between

two levels of attenuation, the settling of the relays will

never cause attenuation less than either of the two valid levels. Remote attenuator drawings (suffix -3077) are located in section

8.

5.6

OPTION 013, UPPER FREQUENCY RANGE EXTENSION

Option 013 extends the frequency range upper limit

2

from information and drawings.

5.7 OPTION 020, TTL OUTPUT

Option 020 provides a TTL compatable square wave signal at BNC labeled TTL OUTPUT. The TTL output maintains the same frequency range and resolution as the standard Model 51 00 and 51

TTL OUTPUT BNC replaces the VAR OUT BNC on the

Model 51 00. See Appendix B for additional information

and drawings.

MHz to 3 MHz. See Appendix A for additional

10 outputs. The

D

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C

8

THIS

DOCUMENT COWTAtNS PROPRIETARY INFORMATION AND WAVETEK AND REASON EXCECT CALIBRATION. OPERATIOW, AND MAINTENAWE

MSION RWTS BELONQINQ TO

MAY

NOT BE REPRODUCED FOR ANY

WMOUT

WRITTEN A~RIZITIOW.

7

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1

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6

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REFERENCE DESIGNATORS

NONE

NONE NONE

NONE

PART DESCRIPTION

SL

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ASSEMBLY & PARTS LIST

OPTION

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BE

REPRODUCED FOR ANY

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BY

DATE

UP

REFERENCE DESIQNATORS

R25 R26 R27

R28 829 930 R31 RES, CFLH 2.2R OW 5%

WAVETEK

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REFERENCE DESIGNATORS

R10

R1

~13

1321

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R18 R2O

R16

R15 R17

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U4 U8

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K1 K2 K3 K4 K5 K6 K7

PART DESCRIPTION

CAP, TANT, . 1WF

35v CAP,

TANT, 1OUF 20%

20v RESaMLM 113 OHM 1%

1/w

TO

RES, WLH 249 OHM 1%

1/w

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REG, MFLM 432 OHM 1%

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1/8W TO

I

RES, MFLM TO

1

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RES,HFLH 11.3 OHM 1%

1/8U TO

ASSY. PRE WAVE LOAD 5100-3077

PART DESCRIPTION

RES, MLM 23.7 OHH

i/ew

TO

RES,

MU1

1/8W TO RES,

HFL~

1/8W TO

RES, MLM 61.9 OHM 1% 1/BW TO

RES,MFLH 71.9 OM 1%

1/8W TO

RES, HFLM 97.1 OHM 1%

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U: DUAL PRPHL DRIVER

(75451)

ASSY, PC ED PREPPED 3100-3077

U: QUAD 2 IN NAND GATE

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RELAY: XTAL i4onw

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DPDT 5V

ORIO-RFQR-PART-NO

ASSEMBLY NO. 1208-00-2580

ORIQ-WOR-PART-NO

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RNSSCJIRIF

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RN55C71RSF

RNSSC97RbF

SN75431N-3

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110.1150

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110.4321

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111.2610

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WAVEEK NO.

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119.9760

TI

120.4431

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1208-00-2381

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122.7400

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122.7474

TELED

175. 1502

NO.

QN/PT

2

1

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1

3

2

1

2

4

1

4

7

REFERENCE DESIGNATORS

GI

NONE

NONE NONE

NONE

PART DESCRIPTION

ASSY, PRE WAVE LOAD

51

00-3077

INSULATOR: MICA TO-3

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4-40X3/8 XCR: ST PH ZN SL

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ASSY, PRE WAVE LOAD 5100-3077

5

ASSEMBLY NO.

-

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PAGE

2

'4

REV

WAVETEK

FMTS

LIST

3

ATTENUATOR ASSY REflOTE

REMOVE ALL BURRS AND BREAK SHARP EDGES

MATERIAL

I

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APPROV

TOLERANCE

UNLESS

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2

ASSEMBLY No.

DATE

TITLE

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DWG

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004.3077

PARTS LIST

REMOTE ATENUATOR

ASSEMBLY

NO

51 00151 10

CODE

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RES, HFLM 221 OHtl 1% 1/8W TO

RES, MFLtl 432 OHM 1% l/iOW

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OPTION 004 10 VP-P MODEL 51 10

OUTPUT

ORIQ-MFGR-PART-NO

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ASSEMBLY

FOR

NO.

PAGE 1

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UNCEM

002.3034

WAVETEK NO.

110.2210

110.4321

QTY/PT

1

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A

D

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CONFORMANCE

TESTS

B

This section describes procedures for verifying correct operation of the instrument and for making the necessary adjustments for optimum performance. If faulty operation is suspected, the steps in this section should be followed to determine the origin of the problem, Section

7

of this manual contains a troubleshooting routine which

is keyed to the steps in this section. After each of these conformance tests, there is a reference in parenthesis (TS-#) to table

The completion of the conformance cedure returns the instrument lo correct alignment,

instrument

ticn I of this manual.

Equipment required in the procedure:

Item Minimum Use Specification

Variac (variable autotransformer) Current:

Oscilloscope

VOM AC and

RMS Voltmeter Calibrated in dB, Reads from

Frequency

Counter Gating interval. Must Accept

7-1 in section 7,

NOTE

CALIBRA TlON LIMlTS AElD

'TOLERANCES ARE NOT

INSTRUMENT

specifications are given in

SPEClFICA TlONS

Voltage Range:

I

A*

Wideband (25 MHz), Two Channels, Vertical Sensitivity:

-rriggered Sweep, DC Voltage Scales,

20,OOORIV on DC.

+

20 dBm to - 80 dBm.

Range 10 Vp-p sine wave,

I

Hz

to 2 MHz with 1 sec

0

to line,

test pro-

Sec-

20mVlcm,

iftern

Programming Unit

(PGM)

Frequency

Source l61 See paragraph

and

1C

socket numbering,

6.2

POWER SUPPLY

Equipment required for this test: VOM, variac, and osciiioscope, Refer to section for component locations and schematic, Test points are shown in figure

1. Variac initial conditions: Dial set at OV.

2.

Instrument initial conditions: Line cord connected

to variac, power

0

Hz, PGM disconnected.

3.

Connect negative probe of meter to ground bus at point A, figure

B

and increase setting of variac until a reading of

+

2.8 Vdc is reached. (TS-I)

4.

Move positive probe to point C and verify (TS-1)

5.

Move negative probe to point point

6.

Move negative probe to point A and positive probe to point watching the meter climb to approximately at full line voltage, (TS-I)

7.

Scope initial conditions: Vertical sensitivity IVlcm, dc coupled, free running sweep, Connect ground lead to scope probe to point

8.

Connect tip of scope probe to points

reading "clean" with a maximum noise component

200mVp-p,

7.3

E

and verify + 5Vdc. (TS-1)

B.

5.OVdc at each point. The trace must be (TS-2)

Minimum

Capable of setting all data lines individually to TTL generating bounceless LOAD pulse (see paragraph Line).

1 MHz signal with TTL "O'hnd

Use

Specification

"0"

3,7.2,1,

or

"I

'"'and

LOAD

".

for description of part designations

7,

power supply drawings

6-1.

ON,

local mode, frequency setting

6-1. Connect positive probe to point

-t-

5V DC.

D,

positive probe to

Increase setting of variac gradually,

+

SVdc

A.

F,

G,

and H,

of

9. Set vertical sensitivity to 5 Vlcm on scope. Connect

tip of probe to point J and verify

200

mV maximum noise, (TS-2)

-t-

15 Vdc with

10, Connect tip of probe to point K and measure

--

15 Vdc with 200 mV maximum noise. (75-2)

6.3

CLOCK GENERATOR

Equipment required for this test: oscilloscope. Refer to

section

8,

main board drawings for component locations

and schematic.. Test point BC is shown in figure 6-1.

1,

Instrument initial conditions: power ON,

disconnected,

paragraph 3.3)

2.

Scope initial conditions: 5 Vldiv, vertical sensitivity,

8

MHz

clock (internal or external,

connected.

PGM

dc coupling, 0.5 pslcm sweep.

3.

Connect channel A probe to test point DC and verify

a negative pulse waveform with a width of 40 ns and

a

period of 4.5 ps. (75-3)

6.4

FRONT PANEL DATA (MODEL,

51

00

ONLY)

Equipment required: Oscilloscope, Refer to figures 3-1 and 6-1 for part locations, $1 thru S10 are front panel frequency switches right to left.

1.

51

00 initial conditions: Power ON, local mode, fre-

quency setting

2,

Scope initial conditions: Vertical Sensitivity 5 Vldiv,

O

Hz.

dc coupled, sweep 0.5 pslcm, sync triggered on negative slope of channel A.

3, Connect Ch A probe to point DC and verify a negative

pulse waveform with a width of 40 ns and a period of 4,s ps, (TS-3)

4.

Adjust position and sweep controls on scope so that the positive-going edges of two consecutive pulses are aligned with the first and the ninth vertical division lines, See figure

5,

Connect Ch B probe on FPD (Front Panel Data). Signal should be logical

6,

The FPD waveform on Ch B represents the setting

of the front panel switches

6-2,

"1 (TS-6)

St

through $9 in BCD code, serial form. Negative logic is used so that the logical setting. With the scope adjusted as per step first division of FPD represents sion are four subdivisions corresponding to the

"1" condition

in

step 5 reflects the

4,

O

Hz

the

S1, the second divi-

S2, etc. Within each of the nine divisions there

1-2-4-8

code for each switch, left to right.

7,

Rotate S1 through its 12 positions verifying the negative-logic BCD code in the first division of as

described in step

"a" through

"Ii". (TS-7)

6.

See figure

6-3,

waveforms

FPB

8.

Repeat step 7 for switches

6-3 waveforms

6.5

SAMPLE GENERATOR

"imm"

S2

through S9. See figure

through "ow,

etc,

(TS-7)

Equipment required: Oscilloscope. Refer to main board

Assembly in section

8

and figure 6-1 for DIA converter

location and test points.

"1

51

00

initial conditions: Power ON, local mode, fre-

quency set to 4

2,

51 10 initial conditions: power ON, all programming lines at logical

kHz.

PGM

connectedd,

"0"

except 4 kHz

and ZERO PHASE. Enter LOAD pulse.

3.

Scope initial conditions: Vertical sensitivity 5 Vlcm, dc coupled, sync triggered on positive slope of Ch

4.

Connect Ch A probe to DAC-1 and verify a square-

A.

wave with a period of 250 ps, (TS-8)

5.

Adjust sweep af scope to set one full cycle of the

square wave in step See figure 6-3, waveform

6,

Connect Ch B probe to BAC-2 and verify waveform

"'b"

in figure 6-3. (TS-9)

7.

If more than two channels are provided on the scope,

3

to fill 10 horizontal divisions.

"az9*

connect them to consecutive DAC pins allowing easier comparison between signals. If only two channels are available,

Ch B will have to be checked

against CH A only,

8,

Display the signal on DAC-3 and compare with figure 6-3, waveform

9.

Display the signals on DAC-4 through DAC-11 and compare with figure

"cl'+ (TS-9),

6-3,

waveforms "d" through

"k". (TS-I 0)

6.6

DC

OFFSET

Equipment required: Oscilloscope, PGM. Refer to Main

board Assembly, section

8,

for location of parts.

1, 5100 initial conditions: Power ON, local mode, fre-

quency setting nect a jumper across

0

Hz,

LEVEL control fully ccw, con-

R54,

shorting it.

2. 51 10 initial conditions: power ON, PGM connected,

ZERO

jumper between

PHASE line set to logical

LPF IN and LPF GND.

"Ow,

connect a

3, Scope initial conditions: DG coupled, vertical

sensitivity

4.

Connect instrument OUTPUTsignal to scope. Adjust

R29

-

20 mVlcm, free-running sweep.

for minimum dc voltage, (TS-18)

5. Remove jumper. 6, Set LEVEL control fully cw (Model 51 00). Adjust

R55

for minimum dc voltage. (TS-18)

I

i

j

i

I

Figure

6-1.

Motherboard

Assembly

A1

-

Bottom

Side

Figure

6-3.

Waveform

for

FPD

FRONT PANEL FREQUENCY

6.7

Equipment Required: Frequency counter, Refer to figure

6-1

for component locations.

front panel frequency switches numbered right to left.

I,

Initial Conditions: Power quency setting,

2.

Connect frequency counter to OUTPUT in order to

I

monitor frequency,

3.

Rotate ing the correct frequency on the counter, (TS-7)

4,

Repeat step 3 with switches

S4

from position 0 through position

second gate interval.

(MODEL.

S1

through

ON,

local mode,

S5

01

SI

0

through

00

ONLY)

are the ten

O

Hz

fre-

9,

verify-

S9.

(TS-PI)

Remove the HzCARRY jumper shown on main board

5.

assembly drawing. Connect the blue

jumper supplied in the plastic bag from point

MC.

point

6-

Repeat step 3 with quency on the counter in Hz for a setting of

the

51

00.

(TS-7)

7.

Remove the blue mHz CARRY jumper and replace

the small,

8,

Set

1

S1O

MHz

black

to

1

on the counter.

MHz

S1,

S2,

and

t-iz

CARRY jumper,

and

S1

through

(TS-I

6)

mHz CARRY

S3

reading the fre-

S9

to

O

MT

mHz on

Hz.

Read

to

Figure

6-4.

Sample Waveform Generator

6.8

REMOTE MODE

Equipment required: Frequency counter, oscilloscope, and programming unit. A bounceless LOAD pulse is

required. In the procedure below, this programming unit

is referred to as

remote loading instructions, All lines are assumed to be logical

ponent locations.

1, lnstrument initial conditions: Power ON, local mode

2. 3, Set PGM to remote. Verify REMOTE lamp (Model

4, Connect instrument OUTPUT signal to frequency

5.

6-

7,

8,

9

"0" unless specified, Refer to figure 6-1 for com-

(Model 51 00 only). Connect PGM to rear panel connector.

51 00) on front panel is lit, (TS-4b)

counter with Set PGM to binary-word, ZERO PHASE line to logical

"1

",

and REMOTE line to logical "0". Load logical "1" 's for frequency bits corresponding to 1 Hz through 51 the frequencyon the counter after each load. (TS-5)

Set PGM to BCD-word and repeat step 5 with lines corresponding to 1 Hz through 800 kHz. (IS-5)

Remove the HzCARRV jumper shown on Main board assembly drawing, section CARRY jumper supplied in the plastic bag from point

to

MT Set PGM to binary-word and load logical

frequency lines corresponding to 1 51 2

mHz, one at at time, The frequency counter should indicate readings of 1 Hz through 512 Hz, (TS-5)

Set PGM to BCD-word and repeat step 8 with lines corresponding to

10. Set PGM to binary-byte. Set PGM mHz lines to

2

t-

(51

pulses, Set

+

1)and enter one LOAB pulse, Counter should read

341,682

1 1. Set PGM on

i-

40

load pulses. Set mHz lines to (400 + 200 + 100

+

80

should read 1,789,555

12. Remove the blue jumper and replace the black jumper.

PGM, Refer to section 3 for detailed

1

second gate interval,

2

kHz and 1 MHz one at a time. Check

8.

Connect the blue mHz

point MC.

1 mHi through 800 mtlz. (IS-5)

128

+

32

-t- 8 -t

mWz switches to

Hz, (TS-5)

BCB-byte. Set rnHz lines to(400

i-

I0

i-

4

+

l)andMHzlineto1.Enterthree

-t-

8

t-

1) and enter one LOAB pulse, Counter

2) and enter three LOAD

(256

-t-

Hz. (TS-5)

''l

"I'

's

for

mHz through

64

+

16 + 4

-t-

100

NOTE

Steps 13, 14 and 15 pertain only to Model 51 00. For Model 51 10, skip to step

16.

13. Set PGM to binary-word, local, 2 kHz, Set

51

00 to local, 1 kHz, Connect OUTPUT to both frequency counter and oscilloscope. OUTPUT should be

remote mode.

OUTPUT should not change. (TS-5)

14. Enter LOAD pulse. Verify OUTPUT frequency changes to

15. Set PGM ts local mode. Verify OUTPUT frequency changes

Steps 16 and 1 7pertain snly to Model 51 1 0.

For Model 51 00, skip ts paragraph

16,

Set PGM to Binary-word, set and LOAD a frequency of

1 KHz. Connect OUTPUT to both frequency counter and oscilloscope. Output should be 1 KHz sinewave.

17, Set REMOTE line to logical "1

quency of

change.

6.9

INTERNAL OSCILLATOR

Equipment required: Oscilloscope, and an external

1 MHz frequency standard. The waveform of this signal is arbitrary but for each logical maximum limits are

1, lnstrument conditions: Power ON, ZERO PHASE line

2.

3, Connect external 1

4. Connect the REF OUT signal from the instrument

"0"

to logical 51 00 only), frequency setting 0 Hz, input reference selector in in 1 MHz position. See Mainboard Assembly drawing, section

Scope initial conditions: Vertical sensitivity 5 Vlcm, sweep 100 nslcm, sync triggered on Ch A.

and adjust trigger to lock the waveform.

rear panel to Ch

(TS-17)

5.

Locate the proper FREQ ADJ hole on the rear panel. With a small, non-metallic flat-bladed screwdriver, adjust the slug so that the waveform of stationary with respect to Ch

6.

Connect the I MHz standard to the REF the rear panel of the instrument and verify that the

leading edges of the waveforms of Ch A and Ch

are phase-locked at 1 80". (TS-17)

2

to 1 kHz, (TS-5)

2

KHz. Verify output signal does not

and logical "1

"0" (Model 51 I0 only), local mode (Model

I NT position, output reference selector

8.

I

kHz sinewave. Set PGM to

kHz. (TS-5)

",

set and LOAB a fre-

cycle it must enter the limits of

""

voltage levels. The absolute

-t-

5

V.

MHz

standard to Gh A of scope

B,

Verify a 1 MHz square wave,

A. (TS-17)

6.9,

Ch

IN

jack on

€3

is

B

i

I

i

STANDARD ATTENUATOR (MODEL

6.1

O

i

Equipment required: RMS voltmeter. 1 , 51 00 initial conditions: Power ON, local mode, f re-

quency 1

kHz,

attenuation 0 dB,

clockwise.

2,

Connect the meter to the OUTPUT jack and verify a reading of greater than

-t

13 dBm. Note this

reading as the 0 dB reference point.

3.

Add attenuation in steps of 1 dB from 0 dB to and verify the attenuation relative to the reference point. Attenuation error must lie within the limits of

-t-

0.5

dB

up

to 60 dB and

--

2,0,

-t-

51

00

LEVEL

0.5 dB up to

ONLY)

fully

85

dB

85

dB,

6.1

1

PROGRAMMABLE ATTIENUATOR (OPTION EQUIPPED UNITS ONLY)

002

Equipment required: RMS voltmeter, and a programming unit capable of setting the attenuator data lines to logical "O'br logical "1 " as directed,

1

,

Verify local mode operation (Model

forming paragraph

6.1

8,

standard attenuator test.

51

00only) by per-

(7s-19)

2.

Connect connector, verify Power to output

3.

Set to binary-word and remaining PGM lines to logical except 1 kHz

4.

Enter and

PGM

jack.

REMOTE

and

LOAD

to Model 5100 or 51

ON

and meter connected

mode (Model 51

ZERO

00

only). Set

PHASE. Enter load pulse.

logical 1's on lines

10

rear panel

A1

through

PGM

"OO""

to

A7

one at a time, verifying the correct attenuation on the meter within the limits specified in paragraph

6.1

0, step

3,

(TS-I

9)

7.1

INTRODUCTION

In the event of a malfunction, a mechanical inspection is advised before proceeding with troubleshooting procedures. Inspect all socket; check proper insertion of the two plug-in PC cards in the connector sockets.

7.2

TROUBLESHOOTING CHART INSTRLIC"T0NS

If trouble develops, start with the Conformance Test Procedure ancy is found. Refer to the TS (TroubleShooting) procedure which appears in parenthesis after the nonconforming item and start troubleshooting at that portion of the troubleshooting chart, table 7-1.

Set up the Test Conditions,

equipment to the verify results in each Observation row, If the Observation description is verified, continue downward to the

next Observation, changing Test Conditions and

Point as necessary.

If the Observation is not verified, refer

column in that row, Perform each part of the Remedy

instructions in the order shown one at a time and recheck the results with the Observation column until Observation checks.

When the results are corrected, return to the section

procedure and recheck the test which failed previously.

If the test still fails, return to the troubleshooting chart

and resume testing with the last step performed

above.

(CTP)

in section

IC's for proper seating in each

6,

following it until adiscrep-

confiect the appropriate

%st Point (shown in figure 6-1) and

lest

to the Remedy

6

If the trouble is not found after exhausting the steps within

one procedure, do not continue into the next procedure,

Rather, return to the section tests made to that point, hopefully uncovering some earlier discrepancy not noticed before,

If the cause of the problem cannot be found, the factory should be consulted. A complete and accurate description of the problem should be made in order to help locate the cause, If the unit is to be returned to the factory, a written and pictorial report should be enclosed to aid in duplicating the operating conditions under which the unit failed. Send

Customer Service Wavetek San 9045 Balboa Ave, San Diego, CA 921 23 Telephone (61 9) 279-2200

WWX:

7.3

PART DESIGNATION AND

NUMBERING

Part designations may be found on the assembly drawings in section follows:

A1

---

A2

--

A3

-

A4 A5

---

Designations for pins on

UXX-YY

pin number, Pin numbers for top views of the three sizes of

IC package used are shown in figure 7-1.

IC socket numbers on Assemblies A1 and A2 are etched

into the bottom side of the PC board.

all

correspondence to:

Diego, Inc,

(91 0) 335-2007

8.

The assemblies are numbered as

Mainboard Assembly Front Panel Scanner Board Assembly Attenuator Board Assembly Frsnt Panel Assembly Rear Panel Assembly

where

XX

is the ICsocket number and

6

procedure and repeat

iC

SOCKET

IC

sockets are in the form

VY

is

all

the

BEPRESSlON

NOTCH

24

16

I

Figure

TS-I. Low or Unregulated Digital Supply Voltage

"Test

Conditions

I. Power off

--

1.

Power on

2.

Apply SVac across line cord for units that are switched to line power by the power switch on the back panel)

(1

0Vac for

230Vac

sele~tion

Point Observation

A5TI Measure 5Vac PRI #I

0-1

15

A5T1 Measure 5Vac PRI

#2

0-1

1

5

7-1.

DIP

Table

7-1.

Correct

/

Check fuse

Measure O.4Vac

Pin Numbering (Top

Trou bleshooting Chart

Replace if necessary.

Check continuity of line cord, fuse holder, and

power switch

1,

If

voltages are all zero, replace transformer

A5T1.

2,

If one or more voltages are low, check for shorts

or opens in wiring to bridge rectifiers.

3.

Check bridge rectifiers A5CR1, CR2,

View)

S2B,

Remedy

Replace

if

defective.

CR3.

Measure 0.75Vac

Tabla

7-1,

\

TS-1,

Low

or Unregulated Digital Supply Voltage (Cont.)

"Troubleshooting

Chart

(Continued)

1.

If

voltages are

2.

If

one!

all

zero, replace transformer

or more voltages are

low,

check far

switch on the back

7"s-2,

2.

Normal

Low

or Zero Regulator Voltage

line

Measure

0.8Vdc

I,

Check for shorted

C7,

Q5,

Remedy

and

replace.

"Conformance

Test

Procedure, paragraph

6.2,

step 8.

TS-3.

No DCLK at test Point DC (See figure

Table

7-1.

Troubleshooting Chart (Continued)

7.2

for timing signals)

Test

Conditions

1.

(Model 51

Lseal mode

(Model

Disconnected

2,

Power

3.

Clock jumper to

INT

position or inject

8

MHz

signal

00):

5"100):

on

reference

PGM

Test

Point

1

Correct

0

bservation

Negative pulse waveform, Width 40 ns; period 125

Negative pulse waveform. Width 125 ns

Negative pulse waveform. BCLK. Width 40 ns; period 500 ns

Negative pulse waveform, Width 40 ns period

ps

1.5

ns

48

KK.

ns;

period

CCLK.

Remedy

Replace

Rqplae U5

Replace U17. UlS, U19.

U95, U89,

U6,

U7, U8,

U4

U1B

U70,

lJ9,

U7O.

U81,

U22.

U96.

TS-4a,

REMOTE

Lamp

Always

On

Negative pulse waveform, BCLK, Width 40

4.5

ps

Negative pulse

waveform. ECLK.

Width 40 ns; period

4.5

ps

(Model

51 00)

ns;

period

Replace

U29, U 18, U

U19, U 10.

19,

U53.

i

89-6

89-1

70-3

70-8

..40

RCLK ns

-

RCLK

CLK

CT

-

CCLK

7-7

ACLK

-

DCLK

PART NO. PINS TO VCC

1 22-741 0 122-01 06 16, 1 122-7404 122-901 122-7474 14

~40 ns

DESCRIPTION OF IC'S

5

14

14 16

-

PlNS TO

GZ

I

1

IC NO

I

DESCRIPTION OF IC'S

PART

NO. 1 PlNS TO VCC I PlNS TO GND

1

NOTES:

----

Dl,

D2, D3, D4

only during a chans ogrequency. Normally,

"0"

logical To create a continuous chan~of frequency condition

to observe active scanner board from its connector.

are active pulse waveforms asdrawn

and

D2,

D3,

D4

Dl,

are at logical

D2,

D3,

D4

"1".

remove assembly

Dl

is at

A2-

Figure

7-2.

Basic Timing

Signals

Table

7-1.

Troubleshooting Chart (Continued)

TS-4b. REMOTE Lamp Always Off (Model 51 00)

Test

Conditions

REMOTE button

Test

Point

U 22-3

pressed

U70-11

TS-5. Remote Operation lncorrect

Test

Conditions

1. Disconnect

Test

Point

U 1 0-5

Programmer

2. Connect jumper from U31-4 or LD to

U53-10 or DC

3. Remote mode

4. Jumper from U34-7 or W to GND

Correct

0

bservation

Logical "1

"

Logical "0"

Correct

0

bservation

Positive pulse waveform. Width

125 ns; period

4.5~s.

Remedy

1. Replace U22, U10.

2. Test and replace S-2A if necessary. Replace Replace

U19, UlO, U70. L1.

Remedy

Replace U31, U20, U10.

Replace U22, U9, U8, U7, U34,

U4,

U41.

TS-6. lncorrect Static Front Panel Data Stream (Model 5100)

Test

Conditions

1. Local mode

Test

Point

J1-19

Correct

0

bservation

Negative pulse waveform. ACLK Width 40 ns; period

125 ns

2.

0

Hz

front panel

J1-12

Logical "1

"

setting

3. Scope sync as per

CTP

6.4-4"

A2 U 9-8

Negative pulse waveform A4*B3*C3 Width

125 ns; period

4.5

ps

J1-10

Logical "1

"

*Conformance Test Procedure, paragraph 6.4, step 4.

7-6

Remedy

Replace U95, A2U1 thru A2U8, A2U10; go to TS-3.

Replace Replace

U10, A2U3. Go to TS-4a.

A2U9. Verify C3 on J1-1 and A4B3 on

J1-2.

Replace A2U4 through A2U8 until J1-10 is logical "1

".

l'

\

Table

7-1.

Troubleshooting Chart (Continued)

TS-7. Incorrect Front Panel Stream (Model 51 00)

Test

Conditions

1. Local mode

Test

Point

J1-10

Correct

Observation

As per CTP 6.4-7

or -8

2. Scope sync as

CTP

6.4-4"

*Conformance Test Procedure, paragraph 6.4, step 4.

TS-8. Sample Generator Malfunction

Test

Conditions

Model

51 00:

1. Local mode

Model

51 10:

1. PGM connected.

2. ZERO PHASE at logical

Models

51 10:

"1

".

5100

and

Test

Point

U98-11

U25-10

Correct

0

bservation

Negative pulse waveform. Width 40 ns; period

125ns

1. 8 MHz clock

(internal or external)

connected.

2.

4

kHz frequency

U98-9

Logical "1

"

setting.

Remedy

Go through TS-6.

Replace

A2U1 through A2U8 until data is

correct.

Remedy

Replace U95, U89, U96, to to TS-3.

Replace U95.

1

.

Verify A5J1-25 (ZERO PHASE) is logical "1

not, correct it.

2. Replace U79, U98, U50.

".

If

Model

1. .001

51 00:

Hz

front

panel setting

Model

5100:

1. Set PGM to

Binary-word.

2. Set 1

mHz

frequency.

3. Enter LOAD pulse.

#I2

Pins to 15 on

U12, U23, U35, U46, U55,

U63,

U72, U80.

Pins

#I3

to 15 on

U1 U1-12

.

U36-13

Logical "0"

Logical "1

"

Positive pulse

waveform. Width

125 ns; period

ps. See figure

125

7-3.

Go to TS-11.

Replace U2, U13, U24, U15, U26, U25,

U3, U14.

SIGNAL LOCATION

FOR GIVEN FRONT PANEL SETTING:

1

mHz

1

Hz

1

KHz

b

SCALE EXPANSION

NOTES:

1.

For each column, set frequency shown and sync on top waveform. Verify each signal from bottom to top.

2.

If top waveform is missing or incorrect, start with bottom signal and work upwards until incorrect signal is found. Start troubleshooting at this point.

12.5

ps

KEY:

4

Logical

"1"

Figure

7-3.

Accumulator Signals

TS-8.

Sample Generator Malfunction (Cont.)

Table 7-1. Troubleshooting Chart (Continued)

Test

Conditions

Model 51 00:

1. 1

Hz

front panel

setting

Model 51 10:

1.

Set

1

Hz

frequency.

2.

Enter LOAD pulse.

Model 51 00:

1. 1

kHz

front panel

setting

Model 51 10:

1.

Set

1

KHz

frequency.

Enter LOAD pulse.

Test

Point

Pins

#I 2

15

on

U1, U12, U23, U46, U55, U63, U72, U80.

Pins

#I3

to

15

on

U35 U35-12 U64-13

Pins

#I 2

to

15

on

.U1, U12,

U23, U35, U46, U55, U72, U80. Pins

#I 3

to

15

on

U63

Correct

0

bservation

Logical

Logical " 1

"0"

"

Positive pulse

waveform. Width

125

ns; period

ps. See figure

Logical

"0"

125

7-3.

Replace

U36, U47, U56, U38, U49, U25, U37,

U48, U57.

Remedy

TS-9. DAC-I, 2,

Test

Conditions

or 3 Inc

Logical Positive pulse

waveform. Width

125 125

"1

"

ns; period

ps. See figure

Replace U84.

U64, U73, U82, U66, U65, U74, U58,

7-3.

1

kHz

square wave

Test

Point Remedy

Correct

Observation

Replace

U83, U95, U82.

U85, U78, U86, U87, U88., U95, U90, U91, U92, U77, U68, U59, U67, U76, U84, U104, U105, U94.

Table

7-1.

Troubleshooting Chart (Continued)

TS-I 0. DAC-4

Test

Conditions

TS-11.

Incorrect Frequency Register Contents (Model

Test

Conditions

1.

Remove

(scanner assy)

2.

Local mode

1.

Sync on negative

edge of

-

04

U53-12

through

A2U10

or

DAC-11

Test

Point

Test

Point

-

U53-12 04

U60-8

U51-12 U51-6

Incorrect

Negative pulse

or

waveform. width period

Negative pulse

waveform. Width

40 125

blanked

"I"

"0" U53-12. 108

period of

Correct

0

bserva t ion

51 00)

Correct

Observation

i%

4.5

ps;

18

ps

ns; spacing

ns. Pulses

to

logical during logical portion of

There are

pulses within a

U53-12.

Replace

U103, U94.

Replace

U90, U92, U93, U100, U 101, U 102,

U52, U44, U53, U19.

U60, U51, U52, U61, U41, U40, U4.

Remedy

1

.

Sync on negative

edge of

-

D2

2.

U53-14

Set front panel

switches to

555,555.555

1

.

Sync on negative

edge of

-

03

2.

Set front panel

Hz

U53-13

switches to

81 9,819.81 9

Hz

or

U 70-6

U

1-1 2

QH

U80-2

K

or

Same as

U53-12.

Alternating

"1 01 O..."

during logical portion of

pattern

"0"

U53-14.

One alternation per

125

ns. There are

1

's,

eighteen eighteen

and

0's

Alternating

"1 01

O..."

pattern

during logical

portion of

"0"

U53-13.

One alternation per

250

ns. There are

nine

1's

and nine

0's

Replace Replace

U23, U12,

U70, U62.

U39; U80, U72, U63, U55, U46, U35,

Check CTP

Replace

U40.

U32, U30, U43, U54, U44, U42, U33,

Ul

6.4.

.

Table

7-1.

Troubleshooting Chart (Continued)

TS-12. Incorrect Frequency ~egister Contents - Binary-Word Mode

Test

Conditions

1. PGM Disconnected.

2. Connect U34-6, U34-7, and U34-8 together.

3. Connect U31-4.

4. Connect U22-1 to U22-7.

TS-13. Incorrect Frequency Register Contents

U19-4 to

Test

Point

U 1 0-9

U 1 0-5

U70-6

U 60-8 U51-12 U51-6 U51-8

Correct

Observation

Logical "1

Positive pulse waveform. Width

=

Period = 4.5~s.

Logical "0"

Negative pulse

waveform.

=

Width

Period = 4.5~s.

".

125ns;

40ns;

Remove All Jumpers

-

BCD-Word Mode

Replace U22, U10, go to TS-3.

Replace U31,

Replace U70, U62, U53.

Replace U51.

Remedy

U20, U10.

U34, U7, U4, U41, U40, U61, U52, U60,

Test

Conditions

1. PGM Disconnected.

2. Connect jumper between U52-12 and

U 52-7.

3. Sync on negative edge of D4 or

U53-12.

1. Sync on negative edge of U53-14 or

D2.

Test

Point

U 60-8 U51-12

U51-6

U 70-6 U1-12 or

QH

Correct

Observation

Negative pulse

waveform.

Width

=

40ns; spacing = 125ns. Pulses blanked to logical of U53-12. There are 108 pulses within a period of

U53-12.

Same as U53-12.

Pattern of "000000000001 repeated three

times during logical

"0" portion of Bit spacing is 125ns. 36 bits during

"0" portion

"

m.

D2.

Remedy

Replace U60, U51, U52, U61, U41, U40, U4.

Replace U70, U62. Replace

U72, U80, U39.

U1, U12, U23, U35, U46, U55, U63,

Table

7-1.

Troubleshooting Chart (Continued)

TS-13.

lncorrect Frequency Register Contents - BCD-Word Mode (~ont.)

Test

Conditions

1.

Sync on negative

edge of

U53-13

D3.

Follow procedure in paragraph

TS-14.

lncorrect Frequency Register Contents - Byte Modes

Test

Conditions

or

Test

Point

U80-2

or

K

Test

Point

Correct

Observation

Pattern of "1 00001 101 100" repeated three

times during logical

"0"

portion of Bit spacing is 125ns. 36 ing

D3.

Remove All Jumpers

6.8.

Correct

0

bservation

m.

bits dur-

Replace U40, U39.

Replace

U32, U30, U43, U54, U44, U42, U33,

U7, U40, U62, U70, U52, U51, U60.

Remedy

(

Follow procedure in paragraphs

TS-15.

TS-16. 1

No 1 MHz Output

Test

Conditions

MHz Operation lncorrect

Test

Conditions

1. 0

Hz setting

1. 1

MHz setting

U 27-9

Test

Point

Test

Point

6.8-1 0

and

Observation

Logical

6.8-1 1

Correct

"0"

"1

"

Replace

U9, U8, U7, U60.

Remedy

U81, U97.

Remedy

U27, U16, U28.

Replace

U82, U84, U83.

Table

7-1.

Troubleshooting Chart (Continued)

TS-17. Crystal Cannot Be Adjusted Into Proper Range

Test

Conditions

TS-18. Output Amplifier Defective

Test

Conditions

TS-19. Programmable Attenuator (Model 51 00 with Option 002 Only)

Test

Point

L

Test

Point

Correct

Observation

Correct

0

bservation

Refer to the Mainboard schematic 03-004-31 00, sheet 4 in section 8 for dc voltage test points, and verify these voltages.

~

Replace U96, U98, U91, C13.

Replace XTAL Y1.

Replace defective components.

Remedy

Test

Conditions

1. Local mode

(Model 51 00 Only)

1. Disconnect Programmer

2. Connect jumper from U31-4 or LD to

U53-10 or DC

3. Remote mode

4. Jumper from W

to

U34-7 or

GND

Test

Point

J2-4 or AC

A3U8-14

A3U8-3 A3 U 8-6

A3U9-5

Correct

Observation

Logical

+

Logical

Negative pulse waveform. Width

125 ns; period

4.5

5

ps.

"1

VDC

"0"

"

See TS-4.

Replace

Replace A2U8.

Replace A2U9.

A3QI.

Remedy

7-1 3

Table

7-1.

Troubleshooting Chart (Continued)

TS-19.

Programmable Attenuator (Model

Test

Conditions

Remove jumpers above. Test each attenuator bit in local and remote modes as per CTP

TS-20.

6.11

Programmable Attenuator (Model

Test

Point

51 00

with Option

Correct

0

bservation

For errors in attenuation settings of:

1

dB

2

dB

4

dB

8

dB

10

dB

20

dB

40

dB

51 10

with Option

002

Only, Cont.)

Remedy

Replace following parts on assembly

A3-U2, -U1, -U9, -K1. A3-U2, -U3, -U10, -K2. A3-U3, 44, -U10, -K3. A3-U4, 45, -U11, -K4.

A3-U6, -U5, -U11, -K5.

A3-U6, -U7, -U12, -K6. A3-U8, -U7, -U12, -K7.

002

Only)

A3:

Test

Conditions

1.

Power On

1.

Disconnect

Programmer

2. Connect jumper from

U31-4

or

LD

U53-10

3. U22-1

4. U34-7

or

DC

Jumper from

to

U22-7.

Jumper from

or W to

U34-8.

to

Test

Point

A3U8-14

A3 U 9-5

Correct

Observation

+5VDC

Negative pulse

waveform. Width

125

ns; period

4.5

ps.

Replace

Remedy

A301.

A2U9.

8.1

DRAWINGS

The following assembly drawings (with parts lists) and

schematics are in the arrangement shown in the

TENTS"

8.2

When ordering spare parts, please specify part number, circuit reference board, serial number of unit and, if applicable, the function performed.

section under "DRAWINGS."

ORDERING PARTS

"CON-

SECTION

8,

STANDARD CIRCUITRY

PARTS AND SCHEMATICS

8.3

ERRATA

Under Wavetek's product improvement program, the latest electronic designs and circuits are incorporated into each Wavetek instrument as quickly as development

and testing permit. Because of the time needed to com-

pose and print instruction manuals, it is not always possible to include the most recent changes in the initial

printing. Whenever this occurs, errata pages are pre-

pared to summarize the changes made and are inserted inside the shipping carton with this manual. If no such pages exist, the manual is correct as printed.

8

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8

THIS DOCWENT CONTAINS PROPRIETARY INFOR-

MATION AND DESIGN RIGHTS BELONGING

WAVETEK AND MAY NOT

REASON EXCEPT CALIBRATION, OPERATION, AND

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BE

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TO

7

6

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DATE AW

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PART DESCRIPTION

PANEL

ASSEIIBLY FRONT

3100

ATTENVATOR 5100

LOCAL SIDE FRAME ASSY SET

ASSY REAR 3100

PANEL MAINBOARD ASSY 5100 SPK CABLE HSSY:

RGD FMD 3100 LABEL, SERIAL

NUMBER/FILTERS SYNTHESIZERS

OSC: VOLT CONTR

(

A/P CARD GUIDE SUPER KIT TY-WRAP TRIM: FRONT TOP

SUPR/SNUB 912 SPACER: SWITCH NYLON

1/16"

ASSY:

SYNTHESIZER 5100

SHU)

&

8MHZ

ORIG-MFGR-PART-NO

FSS-8660

251-1437

VE2-25 2500-5100-03 TY-323M MP40318-4

FW4-062

ASSEMBLY NO.

MFGR

WVTK

VECT

BIVAR

WVTK

TB

BUKEY

MICRO

PAGE

349.2010

002.3100

1

WAVETEK NO.

001.3100

002.3066

002.3067

002.3086

004.3100

009.0391

1400-01-8660

173.6100

2100-06-0024 2300-3100-03 2800-00-0006

307.0914

QTY/PT

1

4

1

2

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REFERENCE DESIGNATORS

47

51

48

57

NONE

26

NONE

29

28

NONE

1

3

I

WAVETEK

~LIs'T'

-

'

PART DESCRIPTION

I

WIRE: 124 ORANGE

WIRE: Y24 YELLOW

WIRE: Y24 GREEN

SLVNG: PLASTIC FBRCLS 118AWO

M SCR: ST ZN PH 2-56 X 5/16 PH

M SCR: ST ZN 440 X 3/8 PH

M SCR: ST ZN PHP 4-40X7/8 PH

M SCR: ST ZN PH 8-32X1/2 PH

M SCR: ST ZN

6-32X3/8FPH TYPE F

,

NUT: HEX

AF

NUT:

4-40X1/4

ASSY: SYNTHESIZER 3100

AWG STR

AWC STR

AH6 STR

SS

HX ST ZN

AF

SL

2-56X5/32

ORIQ-MFGR-PART-NO

1124

ASSEMBLY NO.

MFGR

WEICO

PACF

WAVETEK

378.1734

378.1744

378.1754

378.5181

381.2052

381.4062

381.4142

381.8082

386.6061

387.2051

387.4080

002.3100

3

NO.

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22 NONE

59

41

45

50

53

49

52

46

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l-ls

PART DESCRiPT ION

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KEY: POLARZG PC CONN

IN-CONT

LABEL: CAUTION FREQ. AD

J.

TIE: CABLE NY NAT

(CLAMP

WIRE: BUSS TINNED 118 AWG

WIRE: 118 AWG STR BLACK

WIRE: W22 BLACK

WIRE: W24 BLACK

WIRE: #24 BROWN

WIRE: 124 BROWN

ASSY: SYNTHESIZER 5100

AWG STR

r\W6 STR

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1124

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MFGR

CTC

sn1n.i

3M

CINCH

PANDT

WEICO

ASSEMBLY NO. 002.3100

PAGE 2

4

WAVETEK NO.

332.0201

359.0006

361.9000

370.0301

371. 1001

377.4002

378.0400

378.1404

378.1604

378.1704

378. 1714

378. 1713

QTY/PT

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1

5

2

1

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1

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REFERENCE DESIGNATORS

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34

35

NONE

36

37

NONE

33

NONE

WAVETEK

m

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PART DESCRIPTION

NUT: HX ST ZN 8-32x114 AF

WASHER: FLAT STL ZN Y4

WASHER: FLAT STL

.

14710 .3120D .028THK

WASHER: SPLT LK STNLS #2

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WASHER: FLT NYL W4 1/4D X l/BT

NUT: CLINCH STL ZN 4-40

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SHRINK TUBING,

ASSY: SYNTHESIZER

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MATERIAL AND BREAK SHARP EDGES

FINISH

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I

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ASSEMBLY NO.

PAGE 4

DATE

WA\/ET~K

TITLE

1'

MODEL NO

DWG

51

00

CODE lOENT 23338

WAVETEK

387.8080

388.0040

388.0060

388.1022

388. 1041

388. 1081

388.3040

389.

6001-20-2000

002.3100

PARTS LIST

CHASSIS

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1002

NO

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NO.

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THIS DOCUMENT CONTAINS PROPRIETARY INFOR.

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C12

C26

C24

C32

C33

C20

C28 C30 C55 C56 C96

C13 C27

C6O C61 C62 C63

C66 C68 C69 C70 C71

CEO C81 CB2 C83 C84 C85

C50 C51 C32 C53 C54

WAVETEK

TITLE

ASSY, PRE WAVE LOAD 5100-3100

PART DESCRIPTION

CAP.MOND. 0. IUF 50V Z5U

CAP MICA FX VAL DIP 22~~ 5% -~O+~OOPP~/C 500v

CAP FX VAL,DP MICA

~IPF

5%

-~O+IOOPP~/C

500v CAP FX VAL. DP MICA

150PF 5% 0 TO +~OPP~/C

CAP MICA FX VAL DIP 820PF 1% 0 T0+70PPM/C 300V

CAP MICA FX VAL DIP T0+70PPM/C500V CAP, PLSTRt . 10UF 10%

600V CAP,

soov

1300PF 1% 0

TANT, . IOUF 20%

35V CAP. TAMT, lOUF 20%

ORIG-MFQR-PART-NO

SR2lSE1042AT

CM05ED220J03

CHOJED510J03

CMOSFD151J03

CDl9FD82lF03

CMObFD132F03

DMT6Pl

T368A104M035AS

T368B iO6M025AS

ASSEMBLY NO.

MFGP

AVX

CDE

C-D

KEM3

KEET

1208-00-2557

PAOE 1

UAVETEK NO.

100.4102

101.0220

101.0310

101. 1150

101.

1621

101.2131

105.4100

109. 4100

109.6100

QTY/PT

35

1

10

2

REVA

I

1

REFERENCE

R23

R

59

R54

R31 R43

R22

A25

R39 R44

1127 1128 ~33

R45 R46 R47

R2O R3 R38

R6l

/

W+',V-eK

'

MUST

DESIGNATORS

PART DESCRIPTION

RES, CFLM 220 OHM 5%

1

/4u

RES, CFLM 390 OHM 5%

1

/4U

RESaCFLM 470 OM 5%

1

/4u

REG, CFLM 560 OM 5% 1

/4u

RES. CFLM 620 OHM 5%

1

/4u

RES,

CFLM

820 OHM 5%

I

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RES, CFLM.

1

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RES.

1

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RES, CFLM 3.3K OHM 3%

1

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RES, CFLM 10K 1

/4W

RES. CFLn 47K OM 5%

1

/4U

TITLE

ASSY,PREUAVELOAD5100-3100

CFLM

1.

OK OHM 5%

2.

ZK

OHM

onn

3%

5%

ORIO-P(I=GJ-PART-NO

CF1/4-4700HUn 5%

CF-071K-5%

ASSEMBLY NO.

0

MFGR

STKPL

DALE

1208-00-2337

UAVETEK NO.

116.

1221

116. 1391

116. 1471

116.

1561

116. 1621

116. 1821

116.2101

116.2221

116.2331

116.3101

116.3471

QTY/PT

1

2

1

2

3

1

REV

REFERENCE DESIGNATORS

U70 U97

U19 U60 U99

U39

U10 U17 U20 U27 U29 U41 U42 U44 U54 UB U85

U15 U2 U24 U26 U36 U38

U13 U43 U47 U49 US6 U64 U66 UbB U73 U75 U77 U82

UB

1

U59 U67 U76 U84 U91 U92 U93

U32 U33 U7 U9

US8 U83

UlOO UlOl Ui02 Ui03 U104 u103

U11 U21 U45 U71

A

WAVETEK

'

PAR7SuST

-

PART DESCRIPTION

TGR U: QUAD 2 IN NAND

BUFFER U: DUAL 4 IN NAND

BUFFER U: DUAL2 IN2UAOI

C

ATE

U: DUAL D TYPE FLIP

U90 U98

FLOP U: 4 BIT FULL ADDER

U: 4 BIT COUNTER U:

QD XOR GATE INVERT

OUTPUT

U: QUAD NOR GATE U: DUAL D TYPE FLIP

FLOP U: DL D TYPE FLIP

(SHTKY)

FLOP U: PULL UP NET 3.3K

2X Xl3

ASSY, PRE UAVE LOAD 5100-3100

ORIG-MFGR-PART-NO MFGR UAVETEK NO. QTY/PT

SN7437N-3

DM7440N/A+ NSC 122. 7440

SN7451N-3 TI 122.7451

SN7474N-3 TI 122.7474

N7483N-B SIG 122.7483

N7493N-B 9014DCQB FAIR 122.9014

DM74H74N/AT NSC 123.7474

N74S74N-B SIG 124.7474

41 14R-002-332

ASSEMBLY NO.

TI 122.7437

SIQ 122.7493

122.9015

BOURN 128.2330

1208-00-2557

PAOE 5

e

3

1

13

18

1 7

A

2

6

5

REV

A

REFERENCE DE~~~~~~~~

I

PART

DESCRIPTION

20v

CAP, ELECT, 47UF 20%

63v

CAP 0 TANT, 68UF 20% 6V CAP, ELECT, 3000UF 30V

(PC)

CAP, ELECT, lOOOOUF

15v (PC)

REG,

tlFLH

453 OHK 1%

l/W

TO

REG,

wLn

I.

12

OOK

l/lW

RES. nFLn 2. OOK 1%

l/lOU T2

I

,

WAV~K

NOTE: UNLESS OTHERWISE SPECIFIED

riEE2~-

8

1

ASSY, PRE UAVE LOAD 5100-3100

ORIC-MFGR-PART-NO MFQR WAVETEK NO.

SIEU

KEnET nEPc0

nEPCO

UNCM

1%

uncw uncw

UnCEM

ASSEMBLY NO.

PAOE

7

1208-00-2557

2Al

6

REFERENCE DESIGNATORS

U79

1

NONE

U31 U89

U1 U12 U14 U23 U25 U3 U34 U: 4 BT SHIFT U35 U37 U46 U48 US US3 US5 U57 U63 U65 U69 U72 U74 U78 U80

U16 U18 U22 U28 U30 U40 U61 U86

US0 U6

U4

US1 U52 U62 U87 U88

1

U96

PART DESCRIPTION

I

RES, VAR CMT 5. OK 3/4" RECT

I

U: DUAL PRPHL DRIVER (75451)

1

ASSY. PC BD PREPPED 5100-3100

U:

HNSTBL IIVBRTR

(74121)

REQISTER

U: QUAD 2 IN NAND GATE

U: HEX INVERTER

U: DL 4 IN NAND

I

WAVETEK

1

UST

I

ASSY, PRE WVE LOAD 5100-3100

5

(74195)

SMT

OR

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--

I

4

ASSEMBLY NO.

MFQR

BOURN

uncm

TI

UVTK

SIC

TI

NSC

TI

I

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1208-00-2557

4

UAVETEK NO.

116.4561

118.2500

119.4990

120.4451

1208-00-2558

122.0100

122.0106

122.7400

122.7404

122.7410

122.7413

I

REFERENCE DESIGNATORS

65

98

-.

.

WAVETEK

UST

3

PART DESCRIPTION ORIG-MFGR-PART-NO MFCR UAVETEK NO. QTY/PT

ED

SIL

FUB 5OPIV

SIL RCT 2OOPIV 1A

(

IN4003

SL

ZR

(

lN968B)

SL

LU

(

1N457)

Q:

SIL NPN MATCHED

PAIR 0: SIL NPN (2N2219)

Q: SIL NPN (2N2222) Q:

SIL

CONN, 22 POS EDOE, PC MT. SCL READOUT

CONN, 44 POS EDGE, PC MT, DBL READOUT

SOCKET: IC ST

CDNN: UU (;LEND) TERM PIN .O25 U239-025-5OOQ A/S 354.0007 SPACER: TXSTR LEAD. 10414

NYL.

ASSY, PRE UAVE LOAD 5100-3100

REMOVE ALL BURRS AND BREAK SHARP EDGES

MATERIAL

FINISH WAVETEK PROCESS .XXX

1.

5A

)

20v 5% 4oonu

LK

~OPIV

Zoonu

PNP (2N2905A)

24PIN DIP

LOU

PROJ ENGR

RELEASE AWROV

TOLERANCE UNLESS OTHERWISE SPECIFIED

t.010

to30

DO

NOT SCALE DWG

ANGLES

.XX

SCALE

ASSEMBLY NO.

DATE

-

21-

TITLE

m

2

I

MOT HOT

MOT TR U

TRU

ROBNU

MILRO

376.2108

1208-00-2557

OF

6

~A~TEK

PARTS

MAIN

51

CODE !DENT

DllG

00

23338

.AN

LIST

BOARD

NO

SHEET 1 OF

1

REV

A

DIEGO CAMORRIA

2

A

,

8

THIS WCUMENT CONTAINS PROPRIETARY INFORMATION AND DESIGN RIGHTS BELONGING

WAVETEK AND MAY NOT BE REPRODUCED FOR ANY

REASON EXCEPT CALIBRATION. OPERATION. AND MAINTENANCE WITHOUT WRITTEN AUTHORIZATION.

7

TO

6

5

4

3

2

REV ECN

1

BY DATE

APP

L

7.

I

-(

R3

-€EEl-

REFERENCE DESICNATORS

NONE

R12 R14

R11 R9

R19

R6 R8

R2 R5

R22

OLD

Me.

5/0340

.

I

j-

-I

R7

1

RIO

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HI3

I-

-fTK-y

i

R19

k

-I

R22

R3 R4 R7

R10

Rl

R13 R21 R23

WAVETEK

RWIS

LET

PART DESCRIPTION

I

SCHEMATICI ATTENUATOR

I

ASSY, LOCAL, FOR 5100's

RES, MFLM 115 OHM lX 1/8W TO

'

RESeMFLR 221 OHM 1%

1/8W TO

RES,MFLM 249 OHM 1%

1/BW TO

RESoMFLM 432 OHM 1%

l/lOW

12

RESnMFLM 887 OHM 1% 1/8W TO

RES, MFLM 2.6K 1% 1/8W TO

RESn MFLM l/BW TO

RESn RFLM 23.7 OHM 1% 1/BW TO

1

I

RES, MFLM 49.9 OHM 1% 1/8W TO

RES, MFLM 51. 1 OHM 1%

ll8W TO

LOCAL ATTENUATOR 51 00

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PART DESCRIPTION

M

4-40X3/8 XCR: ST PH ZN SL

M SCR: ST ZN 8-32X3/8 PH

M

SCR: ST ZN PH

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PART DESCRIPTION

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12

NONE

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PARTS

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STRAIN REL: SVT-3

.

156 PANEL

WIRE: BUSS HD DUN TND #20 AWG

#14 AWO STR

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APPENDIX

A

OPTION

A.l GENERAL

Option 01 3 extends the frequency range upper limit from

2

MHz to 3 MHz. Front panel (Model 51 00 local) and programmed (remote) frequency resolution is 0.001 Hz throughout the range. This option is not available with Option 004.

A.2

OPERATION

With Option 01 3 installed, the front panel

a 2 MHz marking, extending the range by 1 MHz. To obtain 3.0 MHz, set the MHz switch to "2", the 100 KHz switch to "10" and all other switches to

Table A-1. Output Signal Characteristics for Option

RMS FRACTIONAL DEVIATION

10 msec averaging

1 sec averaging 5

01

3,3

MHz

MHz knob has

"0".

DC

FREQUENCY

For remote programming, the WordlByte Line (N1 or

#8)

pin becomes the 2 MHz line. The WordlByte Mode Select capability is retained. This is accomplished by program-

N1, the WordlByte bit, via an internal jumper

ming instead of via pin

The BCD or Binary modes are selected via the N2 pro-

gramming line. The Byte or Word mode is selected via an internal jumper (refer to assembly drawing 02-004-3100).

See table A-1 for new Output signal characteristics.

100

RANGE

on the rear panel programming connector

8

on the programming connector.

01

3

2

KHz

500

KHz

5

x x

MHz

IO-~

3

MHz

PHASE NOISE

30 KHz band centered on carrier excluding

1 Hz centered on carrier

SPURIOUS COMPONENTS

50 ohm load

HARMONIC COMPONENTS

50 ohm load

FREQUENCY RESPONSE

50 ohm load

ATTENUATOR RESPONSE

(to 60 dB)

-50dB

-70dB

-55dB

2.25 dB

+

.5 dB

-50dB

-60dB

-50dB

2

.25 dB

+

.5 dB

-

50 dB

-

45 dB

-40dB

+

.5, -2.5 dB

Not Specified

-40dB

-40 dB

+

.5, - 2.5 dB

Not Specified

WO

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TITLE

11

*ODEL

'PARTS

FREQUENCY

5100-

13

5100-13

ZF-002-3113

23338

LIST

....

.,..

SYNTHESIZER

SERIES

wrrr

1

X

OF

1

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2

Wavetek 5100, 5110 Service manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Artek Media

www.artekmedia.com

GENERAL DESCRIPTION

INSTALLATION

POWER SUPPLY

CLOCK GENERATOR

SAMPLE GENERATOR

Motherboard

REMOTE MODE

SYNTHESIZER

REGULATOR