TEXAS INSTRUMENTS UC1842, UC1843, UC1844, UC1845, UC2842 Technical data

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11

A/B

V

cc

7 12

5 9

GROUND

4 7

RT/C

T

2 3

V

FB

1 1COMP

3 5

CURRENT

SENSE

34 V

2.50 V

OSC

UVLO

S/R

5 V

REF

VREF
Good
Logic

Internal

BIAS

Error
Amp

2R

R

1 V

CURRENT
SENSE
COMPARATOR

PWM
LATCH

S
R

T

8 14

V

REF

5 V
50 mA

7

V

C

106

OUTPUT

85

POWER
GROUND

Note 1:
Note 2:

A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.
Toggle flip flop used only in 1844 and 1845.

CURRENT MODE PWM CONTROLLER

FEATURES DESCRIPTION

• Optimized For Off-line and DC-to-DC

Converters

• Low Start-Up Current (<1 mA)

• Automatic Feed Forward Compensation

• Pulse-by-Pulse Current Limiting

• Enhanced Load Response Characteristics

• Under-Voltage Lockout With Hysteresis

• Double Pulse Suppression

• High Current Totem Pole Output

• Internally Trimmed Bandgap Reference

• 500-kHz Operation

• Low R

Error Amp

O

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

The UC1842/3/4/5 family of control devices provides
the necessary features to implement off-line or
dc-to-dc fixed frequency current mode control
schemes with a minimal external parts count.
Internally implemented circuits include under-voltage
lockout featuring start up current less than 1 mA, a
precision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control,
and a totem pole output stage designed to source or
sink high peak current. The output stage, suitable for
driving N-Channel MOSFETs, is low in the off state.

Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC1842 and UC1844 have UVLO
thresholds of 16 V
off-line applications. The corresponding thresholds
for the UC1843 and UC1845 are 8.4 V and 7.6 V.
The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is
obtained by the UC1844 and UC1845 by the addition
of an internal toggle flip flop which blanks the output
off every other clock cycle.

ON

and 10 V

, ideally suited to

OFF

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

BLOCK DIAGRAM

Copyright © 1997–2007, Texas Instruments Incorporated

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1
2
3
4

8
7
6
5

COMP

V

FB

I

SENSE

RT/C

T

V

REF

V

CC

OUTPUT
GROUND

DIL-8, SOIC-8

N or J PACKAGE, D8 PACKAGE

(TOP VIEW)

NC − No internal connection

1
2
3
4
5
6
7

14
13
12
11
10

9
8

COMP

NC

V

FB

NC

I

SENSE

NC

RT/C

T

SOIC-14, CFP-14

D or W PACKAGE

(TOP VIEW)

V

REF

NC
V

CC

V

C

OUTPUT
GROUND
PWR GND

3 2 1 20 19

9 10 11 12 13

4
5
6
7
8

18
17
16
15
14

V

CC

V

C

NC
OUTPUT
NC

NC

V

FB

NC

I

SENSE

NC

PLCC-20

Q PACKAGE

(TOP VIEW)

NC

COMP

NC

PWR GND

GROUND

NC

NC

NC

R

T

/C

T

V

REF

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

ABSOLUTE MAXIMUM RATINGS

Supply voltage

Output current ± 1 A
Output energy (capacitive load) 5 µ J
Analog inputs (Pins 2, 3) –0.3 V to 6.3 V
Error amp output sink current 10 mA

Power dissipation TA≤ 25 ° C (SOIC-14) 725 mW

Storage temperature range –65 ° C to 150 ° C
Junction temperature range –55 ° C to 150 ° C
Lead temperature (soldering, 10 seconds) 300 ° C

(1) All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for

thermal limitations and considerations of packages.

(1)

UNIT

Low impedance source 30 V
ICC< 30 mA Self Limiting

TA≤ 25 ° C (DIL-8) 1 W

TA≤ 25 ° C (SOIC-8) 650 mW

CONNECTION DIAGRAMS

2

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TempStability +

V

REF

(max)* VREF (min)

TJ(max)* TJ (min)

SLUS223C – APRIL 1997 – REVISED JUNE 2007

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PACKAGE θ

DIL-8 J 28

N 25 110
SOIC-8 D8 42 84-160
SOIC-14 D14 35 50-120
CFP-14 W 5.49 ° C/W 175.4C/W
PLCC-20 Q 34 43-75

(1) θJCdata values stated were derived from MIL-STD-1835B.
(2) Specified θJA(junction to ambient) is for devices mounted to 5 in2FR4 PC board with one ounce copper where noted. When resistance

range is given, lower values are for 5 in2. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages
and 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace.

JC

(1)

DISSIPATION RATINGS

PACKAGE

W 700 mW 5.5 mW/ ° C 452 mW 370 mW 150 mW

TA≤ 25 ° C DERATING FACTOR TA≤ 70 ° C TA≤ 85 ° CPO TA≤ 125 ° C

POWER RATING ABOVE TA≤ 25 ° C POWER RATING WER RATING POWER RATING

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

θ

JA

125-160

(2)

(2)
(2)

(2)

ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply for –55 ° C ≤ TA≤ 125 ° C for the UC184X; –40 ° C ≤ TA≤ 85 ° C for the
UC284X; 0 ° C ≤ TA≤ 70 ° C for the 384X; V

PARAMETER TEST CONDITIONS UNIT

REFERENCE SECTION

Output Voltage TJ= 25 ° C, IO= 1 mA 4.95 5.00 5.05 4.90 5.00 5.10 V
Line Regulation 12 ≤ VIN≤ 25 V 6 20 6 20
Load Regulation 1 ≤ I0≤ 20 mA 6 25 6 25
Temp. Stability See
Total Output Variation Line, load, tempature
Output Noise Voltage 10 Hz ≤ f ≤ 10 kHz, TJ= 25 ° C
Long Term Stability TA= 125 ° C, 1000 Hrs
Output Short Circuit –30 –100 –180 –30 –100 –180 mA

OSCILLATOR SECTION

Initial Accuracy TJ= 25 ° C
Voltage Stability 12 ≤ VCC≤ 25 V 0.2% 1% 0.2% 1%
Temp. Stability T
Amplitude V

(1) Adjust V
(2) These parameters, although specified, are not 100% tested in production.

above the start threshold before setting at 15 V.

CC

(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

MIN

PIN

(2) (3)

≤ TA≤ T

4 peak-to-peak

CC

(4)

MAX

= 15 V

(2)

(1)

; RT= 10 k Ω ; CT= 3.3 nF, TA= TJ.

UC1842/3/4/5
UC2842/3/4/5

MIN TYP MAX MIN TYP MAX

(2)

(2)

(2)

4.9 5.1 4.82 5.18 V

47 52 57 47 52 57 kHz

(2)

UC3842/3/4/5

0.2 0.4 0.2 0.4 mV/ ° C

50 50 µ V

5 25 5 25 mV

5% 5%

1.7 1.7 V

mV

the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.

V

and V

REF(max)

are the maximum and minimum reference voltages measured over

REF(min)

(4) Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

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A +

DVPIN 1
DVPIN 3

, 0 v VPIN 3 v 0.8 V

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –55 ° C ≤ TA≤ 125 ° C for the UC184X; –40 ° C ≤ TA≤ 85 ° C for the
UC284X; 0 ° C ≤ TA≤ 70 ° C for the 384X; V

PARAMETER TEST CONDITIONS UNIT

ERROR AMP SECTION

Input Voltage V
Input Bias Current –0.3 –1 –0.3 –2 µ A
A

VOL

Unity Gain Bandwidth TJ= 25 ° C
PSRR 12 ≤ VCC≤ 25 V 60 70 60 70 dB
Output Sink Current V
Output Source Current V
V

High V

OUT

V

Low V

OUT

CURRENT SENSE SECTION

Gain See
Maximum Input Signal V
PSRR 12 ≤ VCC≤ 25 V
Input Bias Current –2 –10 –2 –10 µ A
Delay to Output V

OUTPUT SECTION

Output Low Level

Output High Level

Rise Time TJ= 25°C, CL= 1 nF
Fall Time TJ= 25 ° C, CL= 1nF

UNDER-VOLTAGE LOCKOUT SECTION

Start Threshold

Min. Operating Voltage After
Turn On

PWM SECTION

Maximum Duty Cycle

Minimum Duty Cycle 0% 0%

TOTAL STANDBY CURRENT

Start-Up Current 0.5 1 0.5 1
Operating Supply Current V
V

Zener Voltager ICC= 25 mA 30 34 30 34 V

CC

PIN 1

2 ≤ VO≤ 4 V 65 90 65 90 dB

PIN 2
PIN 2
PIN 2
PIN 2

(6) (7)

PIN 1

PIN 3

I

= 20 mA 0.1 0.4 0.1 0.4

SINK

I

= 200 mA 1.5 2.2 1.5 2.2

SINK

I

SOURCE

I

SOURCE

X842/4 15 16 17 14.5 16 17.5
X843/5 7.8 8.4 9.0 7.8 8.4 9.0
X842/4 9 10 11 8.5 10 11.5
X843/5 7.0 7.6 8.2 7.0 7.6 8.2

X842/3 95% 97% 100% 95% 97% 100%
X844/5 46% 48% 50% 47% 48% 50%

PIN 2

= 15 V ; RT= 10 k Ω ; CT= 3.3 nF, TA= TJ.

CC

UC1842/3/4/5
UC2842/3/4/5

UC3842/3/4/5

MIN TYP MAX MIN TYP MAX

= 2.5 V 2.45 2.50 2.55 2.42 2.50 2.58 V

(5)

= 2.7 V, V
= 2.3 V, V

= 1.1 V 2 6 2 6

PIN 1

= 5 V –0.5 –0.8 –0.5 –0.8

PIN 1

0.7 1 0.7 1 MHz

= 2.3 V, RL= 15 k Ω to ground 5 6 5 6
= 2.7 V, RL= 15 k Ω to Pin 8 0.7 1.1 0.7 1.1

2.85 3 3.15 2.85 3 3.15 V/V

(6)

= 5 V

= 0 V to 2 V

(5) (6)

(5)

0.9 1 1.1 0.9 1 1.1 V
70 70 dB

150 300 150 300 ns

= 20 mA 13 13.5 13 13.5
= 200 mA 12 13.5 12 13.5

(5)

(5)

= V

= 0 V 11 17 11 17

PIN 3

50 150 50 150
50 150 50 150

mA

V

V

ns

V

mA

(5) These parameters, although specified, are not 100% tested in production.
(6) Parameter measured at trip point of latch with V

(7) Gain defined as:

4

= 0.

PIN 2

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_

+

2.5 V

2

1

V

FB

COMP

Z

F

Z

I

0.5 mA

V

CC

<17 mA

<1 mA

V

OFF

V

ON

V

CC

7

V

CC

ON/OFF Command
to REST of IC

UC1842
UC1844

UC1843
UC1845

V

ON

V

OFF

16 V
10 V

8.4 V

7.6 V

Peak Current (IS) is Determined By The Formula

ERROR
AMP

2R

R

1 V

5

COMP
CURRENT

SENSE
GND

I

S

R

C

R

S

CURRENT
SENSE
COMPARATOR

,1.0 V

RS

I

SMAX

1

3

5

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

ERROR AMP CONFIGURATION

Error amp can source or sink up to 0.5 mA.

UNDER-VOLTAGE LOCKOUT

During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be
shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage
currents.

CURRENT SENSE CIRCUIT

A small RC filter may be required to suppress switch transients.

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8

4

5

V

REF

RT/C

T

GROUND

R

T

C

T

For RT> 5 K f

~

1.72

RTC

T

30

10

3

1

0.3

t

d

− ms

1 2.2 4.7 10 22 47 100

CT − nF

Deadtime vs CT (RT >5 kW)

R

T

− (k )W

100

30

10

3

100 1 k 10 k 100 k 1 M

f − Frequency − Hz

Timing Resistance vs Frequency

4

3

2

1

0

.01 .02 .03 .04 .05 .07 .1 .2 .3 .4 .5 .7 1

SINK SAT (VOL)

SOURCE SAT
(V

CC − VOH)

VCC = 15 V

TA = 25°C

TA = −55°C

Output Current, Source or Sink − A

Saturation Voltage − V

80

60

40

20

0

0

−45

−90

−135

−180

Voltage Gain − dB

Phase Margin − °

Av

θ

10 100 1 k 10 k 100 k 1 M 10 M

f − Frequency − Hz

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OSCILLATOR SECTION

OUTPUT SATURATION CHARACTERISTICS

ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE

6

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4.7 kW

1 kW

ERROR AMP

ADJUST

4.7 kW

5 kW

I

SENSE

ADJUST

2N2222

100 kW

R1

1

2

3

4

8

7

6

5

COMP

UC1842

V

FB

I

SENSE

RT / C

T

C

T

0.1 mF

0.1 mF

A

1 kW

1 W

V

REF

V

CC

OUTPUT

GROUND

V

REF

V

CC

OUTPUT

GROUND

8

3

1 kW

330 W

SHUTDOWN

500 W

To Current
SENSE RESISTOR

V

REF

I

SENSE

1

SHUTDOWN

COMP

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OPEN-LOOP LABORATORY FIXTURE

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas
capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

SHUTDOWN TECHNIQUES

Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling V
this pint the reference turns off, allowing the SCR to reset.

below the lower UVLO threshold. At

CC

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R1

5 Ω 1 W

117 VAC

VARO
VM 68

C1
250 µF
250 V

R2

56 kΩ

2 W

R12

4.7 kΩ
2 W

C9
3300 pF
600 V

N

P

D4
1N3613

D2
1N3612

D3
1N3612

NC

R3
20 kΩ

R4

4.7 kΩ

C4
47 µF
25 V

R9

68 Ω

3 W

C3

22 µF

C2

100 µF

25 V

7

2
1

8

4

5

3

6

UC3844

R5 150 kΩ

C14

100 pF

R6
10 kΩ

C5

0.01 µF
C6

0.0022 µF

USD1120

R7

22 Ω

R8

1 kΩ

C7
470 pF

R13
20 kΩ

R10

0.55 Ω
1 W

Q1
UFN833

T1 D6

U9D946

L1

N5

C10

4700 µF

10 V

C11
4700 µF
10 V

+6 V

COM

+12 V

±12 V COM

−12 V

D7

UF81002

N12
N12

C12
2200 µF
16 V

C13
2200 µF
16 V

D8

UES1002

C8
680 pF
600 V

D8
1N3613

R11

2.7 kΩ
2 W

8

4

3

V

REF

RT / C

T

I

SENSE

UC1842/3

0.1 mF

R

T

C

T

R1

R2

C

I

SENSE

R

SENSE

UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OFFLINE FLYBACK REGULATOR

Power Supply Specifications

1. Input Voltages

a. 5VAC to 130VA (50 Hz/60 Hz)

2. Line Isolation: 3750 V

3. Switchng Frequency: 40 kHz

4. Efficiency at Full Load 70%

5. Output Voltage:

a. +5 V, ± 5%; 1A to 4A load

Ripple voltage: 50 mV P-P Max

b. +12 V, ± 3%; 0.1A to 0.3A load

Ripple voltage: 100 mV P-P Max

c. –12 V, ± 3%; 0.1A to 0.3A load

Ripple voltage: 100 mV P-P Max

SLOPE COMPENSATION

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50%.

8

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