TEXAS INSTRUMENTS UC2849, UC3849 Technical data

www.ti.com

Pinnumbersreferto24-pinpackages.

SECONDARY SIDE AVERAGE CURRENT MODE CONTROLLER

FEATURES DESCRIPTION

• Practical Secondary Side Control of Isolated

Power Supplies

• 1 MHz Operation

• Differential AC Switching Current Sensing

• Accurate Programmable Maximum Duty Cycle

• Multiple Chips Can be Synchronized to

Fastest Oscillator

• Wide Gain Bandwidth Product (70 MHz, Acl

>10) Current Error and Current Sense
Amplifiers

• Up to Ten Devices Can Easily Share a

Common Load

UC2849
UC3849

SLUS360C – JULY 1995 – REVISED AUGUST 2007

The UC3849 family of average current-mode
controllers accurately accomplishes secondary side
average current mode control. The secondary-side
output voltage is regulated by sensing the output
voltage and differentially sensing the ac switching
current. The sensed output voltage drives a voltage
error amplifier. The ac switching current, monitored
by a current sense resistor, drives a high bandwidth,
low offset current sense amplifier. The outputs of the
voltage error amplifier and current sense amplifier
differentially drive a high bandwidth, integrating
current error amplifier. The sawtooth waveform at the
current error amplifier output is the amplified and
inverted inductor current sensed through the resistor.
This inductor current down-slope compared to the
PWM ramp achieves slope compensation, which
gives an accurate and inherent fast transient
response to changes in load.

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 1995–2007, Texas Instruments Incorporated

www.ti.com

DIL-24, SOIC-24 (TopView)

NandDWPackages

QPackage

PLCC-28(TopView)

UC2849
UC3849

SLUS360C – JULY 1995 – REVISED AUGUST 2007

DESCRIPTION (cont.)

The UC3849 features load share, oscillator synchronization, undervoltage lockout, and programmable output
control. Multiple chip operation can be achieved by connecting up to ten UC3849 chips in parallel. The SHARE
bus and CLKSYN bus provide load sharing and synchronization to the fastest oscillator respectively. The
UC3849 is an ideal controller to achieve high power, secondary side average current mode control.

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (V
Output current source or sink 0.3 A
Analog input voltages –0.3 to 7
ILIM, KILL, SEQ, ENBL, RUN –0.3 to 7
CLKSYN current source 12
RUN current sink 15
SEQ current sink 20
RDEAD current sink 20
Share bus voltage (voltage with respect to GND) 0 to 6.2
ADJ voltage (voltage with respect to GND) 0.9to 6.3 V
VVEE (voltage with respect to GND) –1.5
Storage temperaturee –65 to 150
Junction temperature –65 to 150 ° C
Lead temperature (soldering, 10 sec.) 300

(1) All voltages with respect to VEE except where noted; all currents are positive into, negative out of the specified terminal.

RECOMMENDED OPERATING CONDITIONS

Input voltage 8 20 V
Sink/source output current 250 mA

(1)

VALUE UNIT

) 20 V

CC

MIN MAX UNIT

V

mA

2

Submit Documentation Feedback

www.ti.com

SLUS360C – JULY 1995 – REVISED AUGUST 2007

RECOMMENDED OPERATING CONDITIONS (continued)

MIN MAX UNIT

Timing resistor (RT) 1 200 k Ω
Timing capacitor (CT) 75 2000 pF

UC2849
UC3849

ELECTRICAL CHARACTERISTICS

(1)

Unless otherwise stated these specifications apply for TA= –40 ° C to 85 ° C for UC2849; and 0 ° C to 70 ° C for UC3849; V
12 V, VEE = GND, Output no load, CT= 345 pF, RT = 4530 Ω , RDEAD = 511 Ω , R

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Current Sense Amplifier

Ib 0.5 3 μ A

V

IO

Avo 60 90 dB

(2)

GBW
V

OL

V

OH

CMRR –0.2 < Vcm < 6.5 V 80
PSRR 10 V < VCC < 20 V 80

Current Error Amplifier

Ib 0.5 3 μ A
V

IO

Avo 60 90 dB

(2)

GBW
V

OL

V

OH

CMRR –0.1 < Vcm < 6.5 V 80
PSRR 10 V < VCC < 20 V 80

Voltage Error Amplifier

Ib 0.5 3 μ A
V

IO

Avo 60 90 dB

(2)

GBW
V

OL

V

OH

V

– ILIM Tested ILIM = 0.5 V, 1.0 V, 2.0 V –100 100 mV

OH

CMRR –0.1 < Vcm < 6.5 V 80
PSRR 10 V < VCC < 20 V 80

(1) Unless otherwise specified all voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
(2) Ensured by design not 100% tested in production.
(3) If a closed loop gain greater than 1 is used, the possible GBW will increase by a factor of ACL + 10; where ACL is the closed loop gain.

TA= 25 ° C 3
Over Temperature 5

Acl = 1, RIN= 1 k Ω , CC = 15 pF, f = 200 kHz

(3)

IO= 1 mA, voltage above VEE 0.5
IO= 0 mA 3.8 V
IO= –1 mA 3.5

Acl = 1, RIN= 1 k Ω , CC = 15 pF, f = 200 kHz

(3)

IO= 1 mA, voltage above VEE 0.5
IO= 0 mA 3.8 V
IO= –1 mA 3.5

f = 200 kHz 4.5 7 MHz
IO= 175 μ A, voltage above VEE 0.3 0.6
ILIM > 3 V 2.85 3 3.15

CLKSYN

= 1 k Ω , TA= TJ.

4.5 7 MHz

3 20 mV

4.5 7 MHz

2 5 mV

=

CC

mV

dB

dB

V

dB

Submit Documentation Feedback

3

www.ti.com

UC2849
UC3849

SLUS360C – JULY 1995 – REVISED AUGUST 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated these specifications apply for TA= –40 ° C to 85 ° C for UC2849; and 0 ° C to 70 ° C for UC3849; V
12 V, VEE = GND, Output no load, CT= 345 pF, RT = 4530 Ω , RDEAD = 511 Ω , R

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2X Amplifier and Share Amplifier

V offset (b; y = mx + b) 20 mV
GAIN (m; y = mx + b) Slope with AV

(2)

GBW
R

SHARE

Total offset –75 0 75 mV
V

OL

V

OH

VCC = 0, V
Negative supply is VEE, GND Open,

VAO = GND
VAO = voltage amplifier Vol, volts above VEE 0.05 0.45 0.6
IO= 0 mA, ILIM = 3 V, VAO = voltage amp V
IO= –1mA, ILIM = 3 V, VAO = voltage amp V

Adjust Amplifier

V

IO

gm I

V

OL

V

OH

= –10 μ A to 10 μ A, V

OUT

I

= 0 0.9 1 1.1

OUT

I

= 50 μ A 0.85 1 1.15

OUT

I

= 0 , V

OUT

I

= –50 μ A, V

OUT

Oscillator

Frequency 450 500 550 kHz
Max duty cycle 80% 85% 90%
OSC range amplitude 2 2.5 2.8 V

Clock Driver/SYNC (CLKSYN)

V

OL

V

OH

I

SOURCE

R

CLKSYN

V

TH

R

V

= 200 Ω 3.2

CLKSYN

= 0, V

CC

VREF Comparator

Turn-on threshold 4.72
Hysteresis 0.4

= 1 V and 2 V 1.98 2.02 V

OUT

/I

SHARE

SHARE

OH

OH

= 3.5 V, C

OUT

= 6.5 V 5.7 6 6.3

SHARE

= 6.5 V 5.7 6 6.3

SHARE

CLKSYN/ICLKSYN

= 1 μ F –1 mS

ADJ

CLKSYN

= 1 k Ω , TA= TJ.

100 kHz
200 k Ω

5.7 6 6.3 V

5.7 6 6.3

40 60 80 mV

0.02 0.2

3.6 V

25 mA
10 k Ω

1.5 V

=

CC

V

V

4

Submit Documentation Feedback

www.ti.com

SLUS360C – JULY 1995 – REVISED AUGUST 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated these specifications apply for TA= –40 ° C to 85 ° C for UC2849; and 0 ° C to 70 ° C for UC3849; V
12 V, VEE = GND, Output no load, CT= 345 pF, RT = 4530 Ω , RDEAD = 511 Ω , R

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC Comparator

Turn-on threshold 7.9 8.3 9.5
Hysteresis 0.4

KILL Comparator

Voltage threshold 3 V

Sequence Comparator

Voltage threshold 2.5
SEQ SAT 0.25

ENABLE Comparator

Voltage threshold 2.5
RUN SAT 0.25

Reference

VREF V

Line regulation 10 < VCC < 20 3 15
Load regulation 0 < IO< 10 mA 3 15
Short circuit I VREF = 0 V 30 60 90 mA

Output Stage

Rise time CL= 100 pF 10 20
Fall time CL= 100 pF 10 20

V

OH

V

OL

Virtual Ground

V

-VEE 0.2 0.75 V

GND

Icc

Icc (run) 21 33 mA

TA= 25 ° C 4.95 5 5.05
VCC = 15 V 4.9 5.1

VCC > 11 V, IO= –10 mA 8.0 8.4 8.8
IO= –200 mA 7.8
IO= 200 mA 3.0
IO= 10 mA 0.5

VEE is externally supplied, GND is floating and used as
signal GND

CLKSYN

= 1 k Ω , TA= TJ.

UC2849
UC3849

=

CC

V

V

V

mV

ns

V

Submit Documentation Feedback

5

www.ti.com

Frequency [

1

T

CHARGE

) T

DISCHARGE

Maximum Duty Cycle [

T

CHARGE

T

CHARGE

) T

DISCHARGE

UC2849
UC3849

SLUS360C – JULY 1995 – REVISED AUGUST 2007

Pin Descriptions

ADJ: The output of the transconductance (gm = –1 ms) amplifier adjusts the control voltage to maintain equal

current sharing. The chip sensing the highest output current will have its output clamped to 1 V. A resistor
divider between VREF and ADJ drives the control voltage (VA+) for the voltage amplifier. Each slave unit's ADJ
voltage increases (to a maximum of 6 V) its control voltage (VA+) until its load current is equal to the master.
The 60-mV input offset on the gm amplifier specifies that the unit sensing the highest load current is chosen as
the master. The 60-mV offset ensures by design to be greater than the inherent offset of the gm amplifier and
the buffer amplifier. While the 60-mV offset represents an error in current sharing, the gain of the current and 2X
amplifiers reduces it to only 30 mV. This pin needs a 1- μ F capacitor to compensate the amplifier.to the master.

CA–: The inverting input to the current error amplifier. This amplifier needs a capacitor between CA– and CAO
to set its dominant pole.

CAO: The output of the current error amplifier which is internally clamped to 4 V. It is internally connected to the
inverting input of the PWM comparator.

CS–, CS+: The inverting and non-inverting inputs to the current sense amplifier. This amplifier is not internally
compensated so the user must compensate externally to attain the highest GBW for the application.

CLKSYN: The clock and synchronization pin for the oscillator. This is a bidirectional pin that can be used to
synchronize several chips to the fastest oscillator. Its input synchronization threshold is 1.4 V. The CLKSYN
voltage is 3.6 V when the oscillator capacitor (CT) is being discharged, otherwise it is 0 V. If the recommended
synchronization circuit is not used, a 1 k Ω or lower value resistor from CLKSYN to GND may be needed to
increase fall time on CLKSYN pin.

CSO: The output of the current sense amplifier which is internally clamped to 4 V.
ENBL: The active low input with a 2.5-V threshold enables the output to switch. SEQ and RUN are driven low

when ENBL is above its 2.5-V threshold.
GND: The signal ground used for the voltage sense amplifier, current sense amplifier, current error amplifier,

voltage reference, 2X amplifier, and share amplifier. The output sink transistor is wired directly to this pin.
KILL: The active low input with a 3.0-V threshold stops the output from switching. Once this function is activated

RUN must be cycled low by driving KILL above 3.0 V and either resetting the power to the chip (VCC) or
resetting the ENBL signal.

ILIM: A voltage on this pin programs the voltage error amplifier’s Voh clamp. The voltage error amplifier output
represents the average output current. The Voh clamp consequently limits the output current. If ILIM is tied to
VREF, it defaults to 3.0 V. A voltage less than 3.0 V connected to ILIM clamps the voltage error amplifier at this
voltage and consequently limits the maximum output current.

OSC: The oscillator ramp pin which has a capacitor (CT) to ground and a resistor (RDEAD) to the RDEAD pin
programs its maximum duty cycle by programming a minimum dead time. The ramp oscillates between 1.2 V to

3.4 V when an RDEAD resistor is used. The maximum duty cycle can be increased by connecting RDEAD to
OSC which changes the oscillator ramp to vary between 0.2 V and 3.5 V. In order to ensure zero duty cycle in
this configuration VEE should not be connected to GND.

The charge time is approximately T
The dead time is approximately T

The C

capacitance should be increased by approximately 40 pF to account for parasitic capacitance.

T

CHARGE

DISCHARGE

= R

• C

when the RDEAD resistor is used.

T

T

= 2 • RDEAD • CT.

OUT: The output of the PWM driver. It has an upper clamp of 8.5 V. The peak current sink and source are 250
mA. All UVLO, SEQ, ENBL, and KILL logic either enable or disable the output driver.

(1)

(2)

6

Submit Documentation Feedback

www.ti.com

VREF

2 R

T

UC2849
UC3849

SLUS360C – JULY 1995 – REVISED AUGUST 2007

RDEAD: The pin that programs the maximum duty cycle by connecting a resistor between it and OSC. The

maximum duty cycle is decreased by increasing this resistor value which increases the discharge time. The
dead time, the time when the output is low, is 2 • RDEAD • CT. The C
approximately 40 pF to account for parasitic capacitance.

RT: This pin programs the charge time of the oscillator ramp. The charge current is

The charge time is approximately T
The dead time is approximately T

CHARGE

DISCHARGE

≈ R

• C

when the RDEAD resistor is used.

T

T

≈ 2 • RDEAD • CT.

RUN: This is an open collector logic output that signifies when the chip is operational. RUN is pulled high to
VREF through an external resistor when VCC is greater than 8.4 V, VREF is greater than 4.65 V, SEQ is greater
than 2.5 V, and KILL lower than 3.0 V. RUN connected to the VA+ pin and to a capacitor to ground adds an RC
rise time on the VA+ pin initiating a soft start.

SEQ: The sequence pin allows the sequencing of startup for multiple units. A resistor between VREF and SEQ
and a capacitor between SEQ and GND creates a unique RC rise time for each unit which sequences the output
startup.

SHARE: The nearly dc voltage representing the average output current. This pin is wired directly to all SHARE
pins and is the load share bus.

VA+, VA–: The inverting and non-inverting inputs to the voltage error amplifier.
VAO: The output of the voltage error amplifier. Its Voh is clamped with the ILIM pin.
VCC: The input voltage of the chip. The chip is operational between 8.4 V and 20 V.
VEE: The negative supply to the chip which powers the lower voltage rail for all amplifiers. The chip is

operational if VEE is connected to GND or if GND is floating. When voltage is applied externally to VEE, GND
becomes a virtual ground because of an internal diode between VEE and GND. The GND current flows through
the forward biased diode and out VEE. GND is always the signal ground from which the voltage reference and
all amplifier inputs are referenced.

VREF: The reference voltage equal to 5.0 V.

capacitance should be increased by

T

(3)

Submit Documentation Feedback

7