Texas Instruments TPSM84424EVM, TPSM84624EVM, TPSM84824EVM User Manual

User's Guide

SNVU581A–November 2017–Revised March 2018

Using the TPSM84824, TPSM84624, and TPSM84424EVM

The TPSM84824, TPSM84624, and TPSM84424 evaluation module (EVM) is designed as an easy-to-use
platform that facilitates an extensive evaluation of the features and performance of the TPSM84x24 power
module. This guide provides information on the correct usage of the EVM and an explanation of the
numerous test points on the board.

Contents

1 Description.................................................................................................................... 2

2 Getting Started ............................................................................................................... 2

3 Test Point Descriptions ..................................................................................................... 3

4 Performance Data ........................................................................................................... 4

5 Bill of Materials (BOM) ...................................................................................................... 6

6 Schematic..................................................................................................................... 8

7 PCB Layout................................................................................................................... 9

List of Figures

1 EVM User Interface.......................................................................................................... 2

2 Efficiency (V
3 Efficiency (V

4 EN Start-up Waveforms..................................................................................................... 4

5 EN Shutdown Waveforms .................................................................................................. 4

6 Transient Performance...................................................................................................... 4

7 TPSM84824EVM Schematic ............................................................................................... 8

8 Topside Component Layout (Top View) .................................................................................. 9

9 Topside Copper (Top View) ................................................................................................ 9

10 Layer 2 Copper (Top View) ............................................................................................... 10

11 Layer 3 Copper (Top View) ............................................................................................... 10

12 Bottom-Side Copper (Top View) ......................................................................................... 11

13 Bottom-Side Component Layout (Bottom View) ....................................................................... 11

= 12 V)....................................................................................................... 4

IN

= 5 V) ........................................................................................................ 4

IN

1 Output Voltage and Switching Frequency Jumper Settings............................................................ 3

2 Test Point Descriptions ..................................................................................................... 3

3 EVM Bill of Materials ........................................................................................................ 6

Trademarks

All trademarks are the property of their respective owners.

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

Copyright © 2017–2018, Texas Instruments Incorporated

List of Tables

Using the TPSM84824, TPSM84624, and TPSM84424EVM

1

Description

1 Description

This EVM features the TPSM84824/624/424 synchronous buck power module configured for operation
with a 4.5-V to 17-V input voltage range. The output voltage can be set to one of six popular values by
using a configuration jumper. Similarly, the switching frequency can be set to one of six values with a
jumper. Additionally, the RTT resistor value, which selects the TurboTrans feature for improved transient
response, is also selectable using a jumper. The full output current rating of the device can be supplied by
the EVM. Input and output capacitors are included on the board to accommodate the entire range of input
and output voltages. Monitoring test points are provided to allow measurement of efficiency, power
dissipation, input ripple, output ripple, line and load regulation, and transient response. Control test points
and component footprints are provided for use of the ENABLE, PGOOD, and CLK features of the device.
The EVM uses a recommended PCB layout that maximizes thermal performance and minimizes output
ripple and noise.

2 Getting Started

Figure 1 highlights the user interface items associated with the EVM. The VIN Power terminal block (J1) is

used for connection to the host input supply and the VOUT Power terminal block (J2) is used for
connection to the load. These terminal blocks can accept up to 16-AWG wire.

www.ti.com

Figure 1. EVM User Interface

The S+ and S- test points for both VIN and VOUT, located near the power terminal blocks are intended to
be used as voltage monitoring points where voltmeters can be connected to measure VIN and VOUT. Do

not use these S+ and S- monitoring test points as the input supply or output load connection
points. The PCB traces connecting to these test points are not designed to support high currents.

The VIN Scope (J3) and VOUT Scope (J4) test points can be used to monitor VIN and VOUT waveforms
with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a
low-inductance ground lead (ground spring) mounted to the scope probe barrel. The two sockets of each
test point are on 0.1 inch centers. The scope probe tip should be inserted into the socket marked with a
white dot, and the scope ground lead should be inserted into the other socket.

The control test points located to the left of the device are made available to test the features of the
device. The UVLO feature can be adjusted by changing resistors R24 and R25 on the bottom of the
board. An external voltage can be applied to the PULL_UP test point for the PGOOD signal. Refer to the

Test Points Descriptions section of this guide for more information on the individual control test points.

2

Using the TPSM84824, TPSM84624, and TPSM84424EVM

Copyright © 2017–2018, Texas Instruments Incorporated

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

www.ti.com

The Fsw SELECT jumper (P1), the VOUT SELECT jumper (P2) and the RTT SELECT jumper (P3) are
provided for selecting the desired output voltage, the appropriate switching frequency and the appropriate
TurboTrans resistor value. Before applying power to the EVM, ensure that the jumpers are present and
properly positioned for the intended output voltage, switching frequency, and TurboTrans resistor value.
Refer to Table 1 for the recommended jumper settings. Always remove input power before changing the
jumper settings.

Table 1. Output Voltage and Switching Frequency Jumper Settings

VOUT Select Fsw Select RTT Select

1 V 350 kHz 2 kΩ

1.2 V 450 kHz 3 kΩ

1.8 V 600 kHz 6 kΩ

3.3 V 1000 kHz 11 kΩ
5 V 1250 kHz 18 kΩ

7.5 V 1350 kHz 28 kΩ

3 Test Point Descriptions

Wire-loop test points and two scope probe test points have been provided as convenient connection
points for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A
description of each test point follows:

Test Point Descriptions

Table 2. Test Point Descriptions

VIN S+ Input voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency.
VIN S– Input voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency.
VOUT S+ Output voltage monitor. Connect the positive lead of a DVM to this point for measuring efficiency, line

VOUT S– Output voltage monitor. Connect the negative lead of a DVM to this point for measuring efficiency, line

AGND Analog ground test point.
PGND Power ground test point.
VIN Scope (J3) Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage.
VOUT Scope (J4) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple

ENABLE Enable test point. Connect this test point to AGND to disable the device. Leave this test point open to

PGOOD Monitors the power good signal of the device. This is an open drain signal.
PULL_UP Test point provided for applying a pull-up voltage for the PGOOD signal. A 100-kΩ pull-up resistor (R26) is

CLK Synchronization clock input test point. An AC coupling capacitor (C13) is present on the EVM between this

(1)

Refer to the product datasheet for absolute maximum ratings associated with above features.

regulation, and load regulation.

regulation, and load regulation.

voltage and transient response.

enable the device.The UVLO resistor divider (R24 and R25) is connected at this point.

present on the EVM between this test point and the PGOOD signal.

test point and the SYNC pin of the device. Pads for a termination resistor (R27) are present between this
test point and PGND. An external clock signal can be applied to this point to synchronize the device to an
appropriate frequency.

(1)

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

Copyright © 2017–2018, Texas Instruments Incorporated

Using the TPSM84824, TPSM84624, and TPSM84424EVM

3

Output Current (A)

Efficiency (%)

0 1 2 3 4 5 6 7 8

40

45

50

55

60

65

70

75

80

85

90

95

100

D001

V

OUT

, F

SW

9.0 V, 1.3 MHz

7.5 V, 1.3 MHz

5.0 V, 1.2 MHz

3.3 V, 1.0 MHz

2.5 V, 800 kHz

1.8 V, 600 kHz

1.2 V, 450 kHz

1.0 V, 400 kHz

0.8 V, 300 kHz

Output Current (A)

Efficiency (%)

0 1 2 3 4 5 6 7 8

40

45

50

55

60

65

70

75

80

85

90

95

100

D002

V

OUT

, F

SW

3.3 V, 1.0 MHz

2.5 V, 800 kHz

1.8 V, 600 kHz

1.2 V, 450 kHz

1.0 V, 400 kHz

0.8 V, 300 kHz

Performance Data

4 Performance Data

Figure 2 through Figure 5 demonstrate the TPSM84824EVM performance. For more data regarding the

TPSM84824, TPSM84624, or the TPSM84424, please see the product data sheet.

Figure 2. Efficiency (VIN= 12 V) Figure 3. Efficiency (VIN= 5 V)

www.ti.com

Figure 4. EN Start-up Waveforms

4

Using the TPSM84824, TPSM84624, and TPSM84424EVM

Copyright © 2017–2018, Texas Instruments Incorporated

Figure 5. EN Shutdown Waveforms

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

www.ti.com

Performance Data

Figure 6. Transient Performance

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

Copyright © 2017–2018, Texas Instruments Incorporated

Using the TPSM84824, TPSM84624, and TPSM84424EVM

5

Bill of Materials (BOM)

5 Bill of Materials (BOM)

See Table 3 for the TPSM84824EVM, TPSM84624EVM, or TPSM84424 bill of materials.

www.ti.com

Table 3. EVM Bill of Materials

Designator Qty Value Description

C1, C2 2 10µF CAP, CERM, 10 µF, 25 V,+/- 10%, X7R, 1210 1210 GRM32DR71E106KA12L MuRata

C3, C4, C5, C6 4 47µF CAP, CERM, 47 µF, 10 V,+/- 10%, X7R, 1210 1210 GRM32ER71A476KE15L MuRata

C12 1 100µF CAP, AL, 100 µF, 50 V, +/- 20%, 0.162 ohm, TH EEUFC1H101B Panasonic
C13 1 47pF CAP, CERM, 47 pF, 50 V,+/- 1%, C0G/NP0, 0603 0603 GRM1885C1H470FA01J MuRata

J1, J2 2 Terminal Block, 5.08 mm, 2x1, Brass, TH

J3, J4 2 Socket Strip, 2x1, 100mil, Black, Tin, TH

P1, P2, P3 3 Header, 100mil, 6x2, Tin, TH

R1 1 10.0k RES, 10.0 k, 1%, 0.063 W, 0402 0402 CRCW040210K0FKED Vishay-Dale
R5 1 15.0k RES, 15.0 k, 1%, 0.1 W, 0603 0603 CRCW060315K0FKEA Vishay-Dale
R6 1 10.0k RES, 10.0 k, 1%, 0.1 W, 0603 0603 CRCW060310K0FKEA Vishay-Dale
R7 1 4.99k RES, 4.99 k, 1%, 0.1 W, 0603 0603 CRCW06034K99FKEA Vishay-Dale
R8 1 2.21k RES, 2.21 k, 1%, 0.1 W, 0603 0603 CRCW06032K21FKEA Vishay-Dale

R9 1 1.37k RES, 1.37 k, 1%, 0.1 W, 0603 0603 CRCW06031K37FKEA Vishay-Dale
R10 1 866 RES, 866, 1%, 0.063 W, 0603 0603 CRCW0603866RFKEA Vishay-Dale
R11 1 143k RES, 143 k, 1%, 0.1 W, 0603 0603 CRCW0603143KFKEA Vishay-Dale
R12 1 110k RES, 110 k, 1%, 0.1 W, 0603 0603 CRCW0603110KFKEA Vishay-Dale
R13 1 82.5k RES, 82.5 k, 1%, 0.1 W, 0603 0603 CRCW060382K5FKEA Vishay-Dale
R14 1 48.7k RES, 48.7 k, 1%, 0.1 W, 0603 0603 CRCW060348K7FKEA Vishay-Dale
R15 1 38.3k RES, 38.3 k, 1%, 0.1 W, 0603 0603 CRCW060338K3FKEA Vishay-Dale
R16 1 35.7k RES, 35.7 k, 1%, 0.1 W, 0603 0603 CRCW060335K7FKEA Vishay-Dale

R17, R28 2 2.00k RES, 2.00 k, 1%, 0.1 W, 0603 0603 CRCW06032K00FKEA Vishay-Dale

R18 1 3.01k RES, 3.01 k, 1%, 0.1 W, 0603 0603 CRCW06033K01FKEA Vishay-Dale
R19 1 6.04k RES, 6.04 k, 1%, 0.1 W, 0603 0603 CRCW06036K04FKEA Vishay-Dale
R20 1 11.3k RES, 11.3 k, 1%, 0.1 W, 0603 0603 CRCW060311K3FKEA Vishay-Dale
R21 1 18.2k RES, 18.2 k, 1%, 0.1 W, 0603 0603 CRCW060318K2FKEA Vishay-Dale
R22 1 28.0k RES, 28.0 k, 1%, 0.1 W, 0603 0603 CRCW060328K0FKEA Vishay-Dale
R23 1 0 RES, 0, 5%, 0.1 W, 0603 0603 ERJ-3GEY0R00V Vishay-Dale
R24 1 86.6k RES, 86.6 k, 1%, 0.1 W, 0603 0603 CRCW060386K6FKEA Vishay-Dale

Package

Reference

2x1 5.08 mm

Terminal Block

Socket Strip,

100mil, 2pin

Header, 6x2,

100mil, Tin

Part Number Manufacturer

ED120/2DS On-Shore Technology

310-43-102-41-001000 Mill-Max

PEC06DAAN Sullins Connector Solutions

6

Using the TPSM84824, TPSM84624, and TPSM84424EVM

SNVU581A–November 2017–Revised March 2018

Submit Documentation Feedback

Copyright © 2017–2018, Texas Instruments Incorporated