Texas Instruments TPSM846C23, TPSM846C23DEVM-807 User Manual
User's Guide
SLVUB26C–May 2017–Revised June 2018
Operating TPSM846C23 in Parallel
This user’s guide contains information for the TPSM846C23DEVM-807 evaluation module (PWR807).
Also included are the performance specifications, schematic, bill of materials (BOM), and layout of the
EVM.
Contents
1 Description.................................................................................................................... 2
2 Getting Started ............................................................................................................... 2
3 Test Point Descriptions ..................................................................................................... 4
4 Operation Notes.............................................................................................................. 5
5 Performance Data ........................................................................................................... 6
6 Schematic..................................................................................................................... 7
7 Bill of Material ................................................................................................................ 8
8 PCB Layout................................................................................................................... 9
List of Figures
1 EVM User Interface.......................................................................................................... 2
2 Efficiency...................................................................................................................... 6
3 Power Dissipation............................................................................................................ 6
4 Output Voltage Ripple....................................................................................................... 6
5 TPSM846C23DEVM-807 Schematic...................................................................................... 7
6 Top Components ............................................................................................................ 9
7 Topside Copper .............................................................................................................. 9
8 Layer 2 Copper .............................................................................................................. 9
9 Layer 3 Copper .............................................................................................................. 9
10 Layer 4 Copper .............................................................................................................. 9
11 Layer 5 Copper .............................................................................................................. 9
12 Bottom-Side Copper ....................................................................................................... 10
13 Bottom Components ....................................................................................................... 10
1 Test Points.................................................................................................................... 4
2 TPSM846C23DEVM-807 Bill of Material ................................................................................. 8
Trademarks
PMBus is a trademark of SMIF, Incorporated.
All other trademarks are the property of their respective owners.
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List of Tables
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Operating TPSM846C23 in Parallel
1
Description
1 Description
The TPSM846C23 is a PMBus™ enabled, synchronous buck power module designed to provide up to 35
A of output current. The TPSM846C23 can be paralleled with two devices to achieve output current up to
70 A. The TPSM846C23 is a highly-integrated, PMBus-enabled DC-DC power module that combines a
35-A DC/DC converter with power MOSFETs, a shielded inductor, some input and output capacitors, and
passives into a low profile package. The input voltage range is 4.5 V to 15 V. The output voltage range is
0.35 V to 2 V. The PMBus interface provides for converter configuration as well as monitoring of key
parameters including output voltage, output current, and the internal die temperature, as well as many
user-programmable configuration options.
This evaluation module is designed to demonstrate the ease-of-use and small printed-circuit-board area
that may be achieved when paralleling two TPSM846C23 power modules. Monitoring test points are
provided to allow measurement of efficiency, power dissipation, input ripple, output ripple, line and load
regulation, and transient response. Additionally, control test points are provided for use of the power good,
and synchronization features of the device. The EVM uses a recommended PCB layout that maximizes
thermal performance and minimizes output ripple and noise.
2 Getting Started
Figure 1 highlights the user interface items associated with the EVM. The polarized input power terminal
block (TB1) is used for connection to the host input supply. TB2 and TB3 allow 4 terminals for VOUT and
TB4 and TB5 allow 4 terminals for PGND for connection to the load. These terminal blocks can except up
to 12 AWG wire.
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Figure 1. EVM User Interface
The VIN Monitor (VIN and PGND) and VOUT Monitor (VS+ and VS–) test points located near the input
terminal block and the output terminal blocks are intended to be used as voltage monitoring points where
voltmeters can be connected to measure the input and output voltages. Do not use these VIN and VOUT
monitoring test points as the input supply or output load connection points. The PCB traces
connecting to these test points are not designed to support high currents.
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The VIN Scope (J1) and VOUT Scope (J2) test points can be used to monitor VIN and VOUT waveforms
with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a
low-inductance ground lead (ground spring) mounted to the scope probe barrel. The two sockets of each
test point are on 0.1 inch centers. The scope probe tip should be inserted into the socket labeled VIN or
VOUT, and the scope probe ground lead should be inserted into the hole of the socket labeled PGND.
The test points located directly below the device are made available to test the features of the device. Any
external connections made to these test points should be referenced to one of the AGND test points
located along the bottom of the EVM. Refer to the Test Point Descriptions section of this guide for more
information on the individual control test points.
The PMBus connector (P1) is provided to connect the USB-to-GPIO interface pod to the EVM. The USBto-GPIO interface pod connects the EVM to a computer USB port which allows the TI “Fusion” Graphical
User Interface (GUI) to communicate and control the EVM. To download the latest software visit,
http://www.ti.com/tool/fusion_digital_power_designer.
The ALERT, DATA, CLK, and CNTL test points are used to monitor and control the module via PMBus.
Reference the TPS546C23 PG1.0 Supported PMBus Commands document for details on the supported
PMBus commands.
The Vout Gain jumper (P4) is used to set the output voltage. Select X1 for an output voltage between
0.35 V–1.65 V and select X2 for output voltages between 0.70 V–2 V. The default loading is the X1
position.
The Comp Select jumper (P2) sets the proper frequency compensation for the total amount of output
capacitance present on the V
capacitance loaded on the board. Locations are provided on the board to add another 2000 µF of output
capacitance (C28–C31). The default jumper load is the 2000 µF position.
When two TPSM846C23 devices are paralleled, the SYNC pins of the Master and the Slave must be
supplied with a 50% duty cycle external clock signal at the desired switching frequency. A 500-kHz clock
is present on the EVM which supplies the required 50% duty cycle signal. The Master device (U1) locks to
the rising edge of the clock and the Slave device (U2) locks to the falling edge of the clock.
Resistors R5, R6, R7, and R8 set the PMBus address for the modules. The master module PMBus
address is 54 decimal (36 hex) and the slave address is 52 decimal (34 hex).
bus. The EVM is shipped with approximately 2000 µF of output
OUT
Getting Started
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Test Point Descriptions
3 Test Point Descriptions
Wire-loop test points and scope probe test points are provided as convenient connection points for digital
voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A description of each test
point follows:
VIN Input voltage monitor. Connect DVM to this point for measuring efficiency.
VS+ Supply path output voltage monitor. Connect DVM positive lead to this point for line regulation and load
regulation.
VS– Return path output voltage monitor. Connect DVM negative lead to this point for measuring line regulation
and load regulation.
VOUT Output voltage monitor. Connect DVM to this point and PGND for measuring efficiency.
PGND Input and output voltage monitor grounds. Reference the VIN and VOUT DVMs to these ground points.
VIN MON (J1) Input voltage scope monitor. Connect an oscilloscope to this set of points to measure input ripple voltage.
VOUT MON (J2) Output voltage scope monitor. Connect an oscilloscope to this set of points to measure output ripple voltage
and transient response.
AGND Analog ground point. Use any of the AGND test points as the ground reference for the control signals.
ALERT PMBus ALERT line, used to monitor the ALERT signal.
CLK PMBus CLK line, used to monitor the CLK signal.
DATA PMBus DATA line, used to monitor the DATA signal.
CNTL Control pin. Pull to AGND to stop power conversion. Float or pull to 3.3 V to enable power conversion. An
internal 10-kΩ pullup resistor to 3.3 V is present on the EVM.
EXT CLK External clock input. This is the input to a D flip-flop. Apply an external clock at a frequency that is twice the
required switching frequency. Remove R13 before applying the clock signal.
SYNC SYNC monitor pin. This pin is the output of a D flip-flop which supplies a clock to both devices.
PGOOD Monitors the power good signal of the device. This is an open drain signal that has an on-board 10-kΩ pullup
resistor the 3.3 V.
DIFFO Output of remote sense differential amplifier.
Signal Signal injection point for Bode plot analyzer. Inject from Signal to CHB.
CHA Input signal monitoring point for Bode plot analyzer.
CHB Output signal monitoring point for Bode plot analyzer.
PH1 Switch node of the TPSM846C23 Master device (U1). Use an unshielded scope probe to monitor this point.
PH2 Switch node of the TPSM846C23 Slave device (U2). Use an unshielded scope probe to monitor this point.
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Table 1. Test Points
NOTE: Refer to the product data sheet (SLVSDF3) for absolute maximum ratings associated with
features in Table 1.
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Operating TPSM846C23 in Parallel
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SLVUB26C–May 2017–Revised June 2018
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4 Operation Notes
In order to operate the EVM, apply a valid input voltage of 4.5 V to 15 V. The undervoltage lock-out
(UVLO) can be programmed the PMBus commands.
The output voltage is set at the factory to 0.6 V. It can be programmed over the allowable V
using the PMBus VOUT_COMMAND.
The Power Good (PGOOD) indicator of the EVM will assert high when the output voltage is within ±5% of
the programmed output voltage value. A 10-kΩ pull-up resistor (R18) is populated between the PGOOD
pin and the 3V3 pin.
The TPSM846C23DEVM-807 is set-up to operate at 500 kHz. A clock circuit is present on the bottom of
the EVM. The clock circuit produces a 500 kHz, 50% duty cycle clock that feeds both devices. If another
switching frequency is required, R23 must be removed from the clock circuit on the bottom of the EVM
and an external clock must be connected to the EXT CLK test point. The external clock applied to EXT
CLK test point must be 2× the required frequency. The device can be synchronized to an external clock
over the frequency range of 300 kHz to 1 MHz. Refer to the product data sheet for further information on
synchronization.
The TPSM846C23DEVM-807 includes both input and output capacitors. The EVM includes footprints for
adding additional input and output capacitors to the EVM. Adding additional capacitance will improve
transient response. The actual capacitance required will depend on the input and output voltage conditions
of the particular application, along with the desired transient response. Refer to the product data sheet for
further information on input and output capacitance and transient response.
This EVM is designed to be used with the USB-to-GPIO pod which enables communication over the
PMBus.
Jumper settings should not be changed while the module is powered. Permanent damage may occur.
Operation Notes
range by
OUT
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