TEXAS INSTRUMENTS TPS92010 Technical data

2

4

8

6

LPM

VDD

FB

GND

TPS92010

Primary Secondary

Feedback

+

5GD

7VSD1 SS

3 PCS

TL431

UDG-09220

TPS92010

www.ti.com

8-PIN HIGH-EFFICIENCY, OFFLINE LED LIGHTING CONTROLLER

Check for Samples: TPS92010

1

FEATURES

2

• LED Lighting Current Driver Controller with
Energy Saving Features

• Quasi-Resonant Mode Operation for Reduced
EMI and Low Switching Losses (Low Voltage
Switching)

• Low Standby Current for Deep Dimming
Efficiency Power Consumption

• Low Startup Current: 25 μA Maximum

• Programmable Line and Load Overvoltage
Protection

– Provides Open LED Protection

• Internal Overtemperature Protection

• Current Limit Protection
– Cycle-by-Cycle Power Limit
– Primary-Side Overcurrent Hiccup Restart

Mode

• 1-A Sink TrueDrive™, –0.75-A Source Gate
Drive Output

• Programmable Soft-Start

.

SLUSA14 –DECEMBER 2009

.

APPLICATIONS

• Residential LED Lighting Drivers for A19
E12/E26/27, GU10, MR16, PAR30/38 Integral
Lamps

• Drivers for Wall Sconces, Pathway Lighting
and Overhead Lighting

• Drivers for Wall Washing, Architectural and
Display Lighting

DESCRIPTION

The TPS92010 is a PWM controller with advanced
energy features to provide high efficiency driving for
LED lighting applications.

The TPS92010 incorporates frequency fold back and
low power mode operation to reduce the operation
frequency at light load and no load operations.

The TPS92010 is offered in the 8-pin SOIC (D)
package. Operating junction temperature range is
–40°C to 105°C.

1

2TrueDrive is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2009, Texas Instruments Incorporated

TPS92010

SLUSA14 –DECEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VDD Supply voltage range IDD< 20 mA 27 V
I

DD

I

GD(sink)

I

GD(source)

V

VSD

I

VSD(source)

V

LPM

T

J

T

stg

T

LEAD

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal.

Supply current 20 mA
Output sink current (peak) 1.2
Output source current (peak) –0.8
Analog inputs FB, PCS, SS –0.3 to 6.0

VDD = 0 V to 30 V 30 V
Power dissipation SOIC-8 package, TA= 25°C 650 mW
Operating junction temperature range –55 to 150
Storage temperature –65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300

(1)

TPS92010 UNIT

A

–1.0 to 6.0

V

–1.0 mA

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

VDD Input voltage 21 V
I
T

Output sink current 0 A

GD

Operating junction temperature –40 105 °C

J

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN MAX UNIT

Human body model 2000
CDM 1500

V

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TPS92010

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SLUSA14 –DECEMBER 2009

ELECTRICAL CHARACTERISTICS

VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
VSD to -0.1 V, FB = 4.8 V, LPM = not connected, 1-nF capacitor from GD to GND, PCS = GND, TA= –40°C to 105°C,
(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OVERALL

I

STARTUP

I

LPM

I

DD

UNDERVOLTAGE LOCKOUT

VDD

(uvlo)

ΔVDD

(uvlo)

PWM (Ramp)

D

MIN

D

MAX

OSCILLATOR (OSC)

f

QR(max)

f

QR(min)

f

SS

dTS/dFB VCO gain TSfor 1.6 V < VFB< 1.8 V –38 –30 –22 μs/V

FEEDBACK (FB)

R

FB

V

FB

LOW POWER MODE

R

DS(on)

I

LPM(leakage)

PEAK CURRENT SENSE (PCS)

A

PCS(FB)

V

PCS(os)

(1) R

PCST

and C

Startup current VDD = V

–0.3 V 12 25

UVLO

Standby current VFB= 0 V 350 550

Operating current mA

Not switching 2.5 3.5
130 kHz, QR mode 5.0 7.0

VDD clamp FB = GND, IDD= 10 mA 21 26 27 V

Startup threshold 10.3 13.0 15.3
Stop threshold 6.3 8 9.3 V
Hysteresis 4.0 5.0 6.0

(1)

Minimum duty cycle VSS= GND, VFB= 2 V 0%
Maximum duty cycle QR mode, fS= max, (open loop) 99%

Maximum QR and DCM frequency 117 130 143
Minimum QR and FFM frequency VFB= 1.3 V 32 40 48 kHz
Soft start frequency VSS= 2.0 V 32 40 48

Feedback pullup resistor 12 20 28 kΩ
FB, no load QR mode 3.30 4.87 6.00
Low power mode ON threshold VFBthreshold 0.3 0.5 0.7
Low power mode OFF threshold VFBthreshold 1.2 1.4 1.6 V
Low power mode hysteresis VFBthreshold 0.9
Burst hysteresis VFBduring low power mode 0.13 0.25 0.42

LPM on resistance V
LPM leakage/off current VFB= 0.44 V, V

(1)

Gain, FB = ΔVFB/ ΔV

PCS

= 1 V 1.0 2.4 3.8 kΩ

LPM

= 15 V –0.1 2.0 μA

STATUS

QR mode 2.5 V/V
Shutdown threshold VFB= 2.4 V, VSS= 0 V 1.13 1.25 1.38 V
PCS to output delay time (power limit) PCS = 1.0 V
PCS to output delay time (over current

fault)

PCS = 1.45 V

PULSE

PULSE

175 300
100 150

PCS discharge impedance PCS = 0.1 V, VSS= 0 V 25 115 250 Ω
PCS offset SS mode, VSS≤ 2.0 V, via FB 0.35 0.40 0.45 V

are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.

PCST

μA

ns

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Link(s): TPS92010

TPS92010

SLUSA14 –DECEMBER 2009

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
VSD to -0.1 V, FB = 4.8 V, LPM = not connected, 1-nF capacitor from GD to GND, PCS = GND, TA= –40°C to 105°C,
(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

POWER LIMIT (PL)

I

PL(Pcs)

V

PL

SOFT START (SS)

I

SS(chg)

I

SS(dis)

V

SS

VALLEY SWITCHING DETECT (VSD)

I

VSD(line)

V

VSD(on)

V

VSD(load)

THERMAL PROTECTION (TSP)

GATE DRIVE

t

RISE

t

FALL

(2) R
(3) Specified by design. Not production tested.

PCST

and C

(2)

PCS current I

= -300 μA –165 –150 –135 μA

VSD

PCS working range QR mode, peak PCS voltage 0.70 0.81 0.92
PL threshold Peak CS voltage + PCS offset 1.05 1.20 1.37

Softstart charge current VSS= GND –8.3 –6.0 –4.5 μA
Softstart discharge current VSS= 0.5 V 2.0 5.0 10 mA
Switching ON threshold Output switching start 0.8 1.0 1.2 V

Valley switching detect I
VSD voltage at OUT = HIGH –125 –25 mV
Load overvoltage protection V

(3)

threshold, GD = HI –512 –450 –370 μA

VSD

VFB= 4.8 V, VSS= 5.0 V,

I

, = –300 μA

VSD(on)

threshold, GD = LO 3.37 3.75 4.13 V

VSD

Thermal shutdown (TSP) temperature 140
Thermal shutdown hysteresis 15

Rise time 10% to 90% of 13 V typical out clamp 50 75
Fall time 10 20

are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.

PCST

V

°C

ns

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2

4

7

6

VSD

VDD

FB

GND

5GD

8LPM1 SS

3 PCS

C

SS

3.3 nF

C

VDD

100 nF

UDG-09221

TPS92010

C

BIAS

1 mF

R

GD

10 W

C

GD

1.0 nF

R

VSD

500 W

C

FBT

47 pF

LPM

V

VSD

V

DD

V

GD

[A]

C

PCST

560 pF

[A]

R

PCST

37.4 kW

+

V

FB

V

PCS

GND

I

PCS

I

VDD

TPS92010

www.ti.com

A. R

PCST

tests.

and C

SLUSA14 –DECEMBER 2009

OPEN LOOP TEST CIRCUIT

are not connected for maximum and minimum duty cycle tests, current sense tests and power limit

PCST

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Product Folder Link(s): TPS92010

UDG-09222

2

1

6

5.0

VREF

SS

VDD

4

GND

5

GD

FB

1.5
R

8

3 PCS

UVLO

+

20

kW

7

VSD

On-Chip
Thermal

Shutdown

REF

26 V

R

LPM

13/8 V

+

400 mV

REF

+

Q

Q

SET

CLR

D

REF

GAIN = 1/2.5

+

Modulation

Comparison

TPS92010

Fault Logic

LINE_VSD

LOAD_VSD

REF_OK

RUN

UVLO

PCS

OVR_T
LPM
SS_DIS

Low Power Mode

FB_CLAMP

OSC_CL
FB

QR DETECT
LOAD_VSD
LINE_VSD

QR_DONE

___

GD

PCS

OSCILLATOR

QR_DONE

CLK

RUN
SS_OVR
OSC_CL

PL

1.2 V

SS_OVR LOW PWR LOW POWER

VDD

TPS92010

SLUSA14 –DECEMBER 2009

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BLOCK DIAGRAM

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PCS

1

GND

2

3

4

SS

FB

VDD

8

GD

7

6

5

LPM

VSD

TPS92010

www.ti.com

SLUSA14 –DECEMBER 2009

ORDERING INFORMATION

T

A

–40°C to 105°C SOIC (D)

(1) SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled

quantities for TPS92010DR is 2,500 devices per reel.

PACKAGES PART NUMBER

(1)

TPS92010D

DEVICE INFORMATION

TPS92010 (TOP VIEW)

PIN FUNCTIONS

PIN

NAME NO.

FB 2 I

GND 4 –

GD 5 O

LPM 8 O

PCS 3 I protection. The PCS voltage input originates across a current sense resistor and ground. Power limit is

SS 1 I placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge the

VDD 6 I as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To prevent

VSD 7 I The valley switching detect (VSD) pin senses line, load and resonant conditions using the primary bias winding.

I/O DESCRIPTION

Feedback input or control input from the output sensing network to the PWM comparator used to control the peak
current in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated
voltage. The voltage of this pin controls the mode of operation in one of the three modes: quasi resonant (QR),
frequency foldback mode (FFM) and low power mode (LPM).

Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the
capacitor as close to these two pins as possible.

1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and switches
between GND and the lower of VDD or the 13-V internal output clamp.

The low power mode pin is an ACTIVE HIGH open drain signal that indicates the device has entered low power
mode. LPM pin is high during UVLO, (VDD < startup threshold), and softstart, (SS < FB).

Peak current sense input, also programs power limit and is used to control modulation and activate overcurrent
programmed with an effective series resistance between this pin and the current sense resistor.

Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should be

SS pin to GND through an internal MOSFET with an R
comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.

Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD pin,
hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.

of approximately 100 Ω. The internal modulator

DS(on)

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Product Folder Link(s): TPS92010