Texas Instruments TPS9103PWR, TPS9103PWLE Datasheet

TPS9103

POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Charge Pump Provides Negative Gate Bias
for Depletion-Mode GaAs Power Amplifiers

D

Buffered Clock Output to Drive Additional
External Charge Pump

D

135-mΩ High-Side Switch Controls Supply
Voltage to the GaAs Power Amplifier

D

Power-Good Circuitry Prevents High-Side
Switch Turn-on Until Negative Gate Bias is
Present

D

Charge Pump Can Be Driven From the
Internal Oscillator or An External Clock

D

10-µA Maximum Standby Current

D

Low-Profile (1.2-mm Max Height), 20-Pin
TSSOP Package

description

The TPS9103 is a highly integrated power supply for depletion-mode GaAs power amplifiers (PA) in cellular
handsets and other wireless communications equipment. Functional integration and low-profile packaging
combine to minimize circuit-board area and component height requirements. The device includes: a p-channel
MOSFET configured as a high-side switch to control the application of power to the P A; a driver for the high-side
switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent
turn-on of the high-side switch until gate bias is present. The high-side switch has a typical on-state resistance
of 135 mΩ.

The TPS9103 is available in a 20-pin thin shrink small-outline package (TSSOP) or in chip form. Contact factory
for die sales. The device operates over a junction temperature range of –25°C to 125°C.

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

TSS0P

(PW)

CHIP FORM

(Y)

–25°C to 85°C TPS9103PWLE TPS9103Y

The PW package is only available left-end taped and reeled
(indicated by the LE suffix on the device type).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

GATE_BIAS

V

CC

C1–

C1+
BATT_IN
BATT_IN
BATT_IN

PGP

PG

GND

V

DD

CLK
BCLK
GND
BATT_OUT
BATT_OUT
BATT_OUT
SW_EN
OSC_EN
EN

PW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

12

33

REF

+

OSC

Inverting

Charge

Pump

0.6R

5, 6, 7

2

18

20

11

8

10, 17

4
3

14, 15, 16

13

9

19

1

BATT_OUT

SW_EN

PG

CLK

GATE_BIAS

BATT_IN

V

CC

BCLK

V

DD

EN

OSC_EN

PGP

C1+
C1–

GND

V

ref

UVLO

UVDLO

V

CC

PG
Comparator

R

TPS9103

POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS9103Y chip information

This chip, when properly assembled, displays characteristics similar to the TPS9103. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform. Contact factory for die sales.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.

83

116

(6)(7)

TPS9103Y

C1+
C1–

BATT_IN

PGP

EN

OSC_EN

SW_EN

CLK

GATE_BIAS

BATT_OUT

BCLK

PG

VCCV

DD

202

GND

10, 17

1

14, 15, 16

18

4
3

5, 6, 7

8

9
11
12
13
19

(2)(3)

(1 )

(20)

(19)

(18)

(4)

(5)

(6)

(7)

(17)

(16)

(15)

(14)

(8) (9) (10) (11) (12) (13)

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

DESCRIPTION

GATE_BIAS 1 Negative gate-bias output voltage
V

CC

2 Logic supply voltage
C1– 3 External capacitor connection (inverting charge pump)
C1+ 4 External capacitor connection (inverting charge pump)
BATT_IN 5 High-side switch input voltage
BATT_IN 6 High-side switch input voltage
BATT_IN 7 High-side switch input voltage
PGP 8 Program input for power-good threshold
PG 9 Power-good output
GND 10 Ground
EN 11 Chip-enable input
OSC_EN 12 Oscillator-enable input
SW_EN 13 High-side switch enable input
BATT_OUT 14 High-side switch output voltage
BATT_OUT 15 High-side switch output voltage
BATT_OUT 16 High-side switch output voltage
GND 17 Ground
BCLK 18 Buffered clock output
CLK 19 Clock (bidirectional)
V

DD

20 Charge-pump supply voltage

TPS9103

POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

high-side switch and driver (BATT_IN, BATT_OUT, SW_EN)

The high-side switch is a p-channel MOSFET with a maximum on-state resistance of 180 mΩ
(V

I(BATT_IN)

= 6 V and VCC = 3.3 V). The driver pulls the gate of the high-side switch to GA TE_BIAS instead of
ground to reduce the MOSFET on-state resistance. Gate breakdown considerations limit the voltage between
BA TT_IN and GATE_BIAS to 15 V. Extremely fast switching times are not required in this application, and the
high-side switch/driver is designed to provide 2 µs maximum switching times with minimum power consumption.
The GaAs depletion-mode MOSFETs in the PA are protected from damage at power-up by internal logic that
inhibits the driver until negative gate bias is available. The control input SW_EN is compatible with 3-V and 5-V
CMOS logic; a logic-high input turns the high-side switch on.

oscillator (OSC_EN

, CLK)

The internal oscillator drives the charge pump at 50 kHz with a nominal duty cycle of 50% when both the EN
and OSC_EN inputs are logic lows. CLK outputs the internal oscillator signal (no buffer). A logic-high input to
OSC_EN

disables the internal oscillator and allows the charge pump to operate from an external clock
connected to CLK. When an external clock with negative overshoot is applied, a Schottky diode must be added
to limit the amplitude of the overshoot.

charge pump (GATE_BIAS, C1+, C1–)

The inverting charge pump generates the negative gate-bias voltage output at GATE_BIAS.

chip enable (EN

)

A logic high on EN

shuts down the internal functions of the TPS9103 and turns the bias system off, reducing

the supply current to less than 10 µA. A low input on EN

causes normal operation to resume.

power good (PG, PGP)

PG output is logic high when GATE_BIAS is in regulation. PG output is logic low when GATE_BIAS is not in
regulation. The high-side switch is disabled and PG is forced to logic low whenever the magnitude of
GATE_BIAS is less than 0.6 × V

DD

. A modified threshold for the power-good function can be achieved by

programming PGP with an external resistor.

undervoltage lockout for V

CC

and V

DD

(UVLO and UVDLO)

Undervoltage lockout prevents operation at supply voltages too low for proper operation. When UVLO or
UVDLO is active, all power-switch drives are forced to the off state and bias is removed from unneeded
functions. Hysteresis is provided to minimize cycling on and off because of source impedance loading when the
supply voltage is close to the threshold.

buffered clock output (BCLK)

The buffered clock output is a driver for an external charge pump. When the optional external charge pump is
not needed, BCLK should be left unconnected. For more details, see the application section.

supply input for inverting charge pump (V

DD

)

V

DD

is the supply voltage for the inverting charge pump. In normal operation, V

DD

is connected to VCC. If the

negative gate-bias needs to be larger than V

CC

(i.e., more negative), then a higher voltage supply needs to be

connected to V

DD

. This can be supplied from an external charge pump driven from BCLK.

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

PW 645 mW 6.5 mW/°C 353 mW 255 mW

Maximum values are calculated using a derating factor based on R

θJA

= 154°C/W for the package. These devices are

mounted on an FR4 board with no special thermal considerations.

400

300

100

0

25 35 45 55

– Maximum Continuous Dissipation – mW

500

600

700

65 75 85

200

PW Package
R

θJA

= 154°C/W

P

D

TA – Free-Air Temperature – °C

Figure 1. Dissipation vs Free-Air Temperature

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

High-side switch input voltage range, BATT_IN (see Note 1) –0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, V

CC

, VDD –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential voltage, |BATT_IN|–|GATE_BIAS| 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, SW_EN, EN

, CLK, OSC_EN, PG –0.3 V to V

CC

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . .

GA TE_BIAS –5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, PG 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, BCLK 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, GATE_BIAS 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, BATT_OUT 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current, BATT_OUT 4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum external clock frequency, CLK 100 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Junction temperature range, T

J

–25°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to device GND.

2. Differential voltage calculated: |VImax| + |GATE_BIAS|

TPS9103

POWER SUPPLY FOR GaAs POWER AMPLIFIERS

SLVS131A – OCTOBER 1995 – REVISED JULY 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Input voltage, BATT_IN 3 9 V
Supply voltage, V

CC, VDD

2.7 5.5 V

Output voltage, GATE_BIAS, V

O

–2 –5 V
Continuous output current, GATE_BIAS 0 10 mA
Continuous output current, BATT_OUT 0 2 A
Charge-pump capacitor value at C1+/C1– 0.33 µF
External clock frequency, CLK 25 75 kHz
High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

SW_EN, EN, OSC_EN, CLK

0.8 V

Input current, I

I

–1 1 µA
Operating junction temperature, T

J

–25 125 °C

electrical characteristics over recommended operating junction temperature range,
BATT_IN = 6 V, V

CC

= V

DD

= 3.3 V, I

O(BATT_OUT)

= 0.5 A, I

O(GATE_BIAS)

= 2 mA,

EN

= OSC_EN = 0 V, SW_EN = VCC, C1 = 0.33 µF (unless otherwise noted)

charge pump

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage –3 –3.10 –3.3 V
Output resistance 95 Ω

high-side switch

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA = 25°C 135 180
TA = –25°C to 85°C 210

D

ran-to-source on-state resistance

TA = 25°C,

V

I(BATT_IN)

= 3 V

160 220

m

Ω

TA = –25°C to 85°C, BATT_IN = 3 V 260
TA = 25°C,

V

I(BATT_IN)

= 9 V,

SW_EN = 0 V 1

Leakage current

TA = 85°C,

V

I(BATT_IN)

= 9 V,

SW_EN = 0 V 10

µ

A

Delay to high-level output SW_EN from 0 to V

CC

0.2 2 µs

Delay to low-level output SW_EN from VCC to 0 0.9 2 µs

oscillator

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Frequency VCC = 2.7 V to 5.5 V 35 50 60 kHz
Duty cycle VCC = 2.7 V to 5.5 V 40% 50% 60%

buffered clock output (BCLK)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output resistance 10 Ω
High-level output voltage I(BCLK) = 30 mA VCC –0.3 V
Low-level output voltage I(BCLK) = 30 mA 0.3 V