Texas Instruments TPS79301DBVREP, TPS79301MDBVREP, TPS79318DBVREP, TPS79325DBVREP, TPS793285DBVREP Schematic [ru]

...
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FEATURES

324
5
DBV PACKAGE
(TOP VIEW)
1IN
EN
OUT
BYPASS
Fixed Option
324
6
DBV PACKAGE
(TOP VIEW)
1IN
EN
OUT
BYPASS
5
FB
Adjustable Option
Controlled Baseline
Enhanced Diminishing Manufacturing Sources
Enhanced Product-Change Notification
Qualification Pedigree
200-mA Low-Dropout Regulator With EN
Available in 1.8 V, 2.5 V, 2.8 V, 2.85 V, 3 V,
High PSRR (70 dB at 10 kHz)
Ultralow Noise (32 µ V)
Fast Start-Up Time (50 µ s)
Stable With a 2.2- µ F Ceramic Capacitor
Excellent Load/Line Transient
Very Low Dropout Voltage
5-Pin SOT23 (DBV) Package

APPLICATIONS

VCOs
RF
Bluetooth™, Wireless LAN
(1) Component qualification in accordance with JEDEC and
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
ULTRALOW-NOISE, HIGH-PSRR, FAST RF 200-mA
LOW-DROPOUT LINEAR REGULATORS
One Assembly/Test Site, One Fabrication
Site
(DMS) Support
(1)
3.3 V, 4.75 V, and Adjustable
(112 mV at Full Load, TPS79330)
industry standards to ensure reliable operation over specified temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. time.
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006

DESCRIPTION

The TPS793xx family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in a small-outline SOT23 package. Each device in the family is stable, with a small 2.2- µ F ceramic capacitor on the output. The TPS793xx family uses an advanced, proprietary, BiCMOS fabrication process to yield extremely low dropout voltages (e.g., 112 mV at 200 mA, TPS79330). Each device achieves fast start-up times (approximately 50 µ s with a 0.001- µ F bypass capacitor), while consuming very low quiescent current (170 µ A typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 µ A. The TPS79328 exhibits approximately 32 µ V bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR and low-noise features, as well as the fast response
of output voltage noise with a 0.1- µ F
RMS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
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10 100 1 k 10 k
10
40
80
100 k 1 M 10 M
Ripple Rejection − dB
f − Frequency − Hz
TPS79328
RIPPLE REJECTION
vs
FREQUENCY
IO = 10 mA
50
0
VI = 3.8 V Co = 10 µF C
(byp)
= 0.01 µF
IO = 200 mA
20
30
60
70
90
100
0
0.05
0.1
0.15
0.2
0.25
0.3
100 1 k 10 k 100 k
f − Frequency − Hz
IO = 1 mA
VI = 3.8 V Co = 2.2 µF C
(byp)
= 0.1 µF
IO = 200 mA
TPS79328
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
V/ HzOutput Spectral Noise Density −
µ
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
T
J
–40 ° C to 125 ° C
–55 ° C to 125 ° C 1.2 to 5.5 V TPS79301MDBVREP
(1) The DBVR indicates tape and reel of 3000 parts. (2) Product preview
VOLTAGE PACKAGE PART NUMBER SYMBOL
1.2 to 5.5 V TPS79301DBVREP
1.8 V TPS79318DBVREP
2.5 V TPS79325DBVREP
2.8 V TPS79328DBVREP
2.85 V TPS793285DBVREP 3 V TPS79330DBVREP
3.3 V TPS793333DBVREP
4.75 V TPS793475DBVREP
AVAILABLE OPTIONS
(1) (1) (1) (1) (2)
SOT23
(DBV)
(1) (2)
(1) (2)
(1) (1)
(1)
PGVE PHHE
PGWE
PGXE
PHIE PGYE PHUE
PHJE
PMBM
2
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TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)
Input voltage range Voltage range at EN VI+ V
Voltage on OUT –0.3 6 V Peak output current Internally limited
ESD rating
Continuous total power dissipation
T
Operating virtual junction temperature range –55 125 ° C
J
T
Storage temperature range –65 150 ° C
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal
(2)
(1)
MIN MAX UNIT
–0.3 6 V –0.3
Human-Body Model (HBM) 2 kV Changed-Device Model (CDM) 500 V
0.3
See Dissipation
Rating Table

Dissipation Ratings

BOARD PACKAGE R
(1)
Low K
(2)
High K
(1) The JEDEC low K (1s) board design used to derive this data was a 3-in × 3-in, two layer board with 2-oz copper traces on top of the
board.
(2) The JEDEC high K (2s2p) board design used to derive this data was a 3-in × 3-in, multilayer board with 1-oz internal power and ground
planes and 2-oz copper traces on top and bottom of the board.
DBV 63.75 ° C/W 256 ° C/W 3.906 mW/ ° C 391 mW 215 mW 156 mW DBV 63.75 ° C/W 178.3 ° C/W 5.609 mW/ ° C 561 mW 308 mW 224 mW
θ JC
R
θ JA
DERATING TA≤ 25 ° C TA= 70 ° C TA= 85 ° C
FACTOR ABOVE POWER POWER POWER
TA= 25 ° C RATING RATING RATING
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LineReg. (mV) +ǒ%ńV
Ǔ
V
O
ǒ
V
Imax
* 2.7 V
Ǔ
100
1000
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, EN = VI, TJ= –55 to 125 ° C and TJ= –40 to 125 ° C, VI= V 1 V, IO= 1 mA, Co= 10 µ F, C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input voltage
I
I
Continuous output current
O
T
Operating junction temperature –55 125 ° C
J
Output voltage V
Quiescent current (GND current) µ A
Load regulation 0 µ A < IO< 200 mA, TJ= 25 ° C 5 mV
Output voltage line regulation ( VO/VO)
Output noise voltage (TPS79328) µ V
Time, start-up (TPS79328) C
Output current limit VO= 0 V Standby current EN = 0 V, 2.7 V < VI< 5.5 V 0.07 1 µ A High-level enable input voltage 2.7 V < VI< 5.5 V 2 V Low-level enable input voltage 2.7 V < VI< 5.5 V 0.7 V Input current (EN) EN = 0 –1 1 µ A
(1)
TPS79301
TPS79318
TPS79325
TPS79328
TPS793285
TPS79330
TPS79333
TPS793475
= 0.01 µ F (unless otherwise noted)
(byp)
(2)
0 µ A < IO< 200 mA, TJ= –40 to 125 ° C,
1.22 V VO≤ 5.2 V 0 µ A < IO< 200 mA, TJ= –55 to 125 ° C, 1.025
1.22 V VO≤ 5.2 V TJ= 25 ° C 1.8 0 µ A < IO< 200 mA, 2.8 V < VI< 5.5 V 1.764 1.836 TJ= 25 ° C 2.5 0 µ A < IO< 200 mA, 3.5 V < VI< 5.5 V 2.45 2.55 TJ= 25 ° C 2.8 0 µ A < IO< 200 mA, 3.8 V < VI< 5.5 V 2.744 2.856 TJ= 25 ° C 2.85 0 µ A < IO< 200 mA, 3.85 V < VI< 5.5 V 2.793 2.907 TJ= 25 ° C 3 0 µ A < IO< 200 mA, 4 V < VI< 5.5 V 2.94 3.06 TJ= 25 ° C 3.3 0 µ A < IO< 200 mA, 4.3 V < VI< 5.5 V 3.234 3.366 TJ= 25 ° C 4.75 0 µ A < IO< 200 mA, 5.25 V < VI< 5.5 V 4.655 4.845 0 µ A < IO< 200 mA, TJ= 25 ° C 170 0 µ A < IO< 200 mA 220
(4)
VO+ 1 V < VI≤ 5.5 V, TJ= 25 ° C 0.05 VO+ 1 V < VI≤ 5.5 V 0.12
BW = 200 Hz to 100 kHz, IO= 200 mA, TJ= 25 ° C
RL= 14 , Co= 1 µ F, TJ= 25 ° C
2.7 5.5 V 0 200 mA
(3)
(3)
C
= 0.001 µ F 55
(byp)
C
= 0.0047 µ F 36
(byp)
C
= 0.01 µ F 33
(byp)
C
= 0.1 µ F 32
(byp)
C
= 0.001 µ F 50
(byp)
= 0.0047 µ F 70 µ s
(byp)
C
= 0.01 µ F 100
(3)
(byp)
0.98 Vo 1.02 Vo
0.97 Vo
285 600 mA
Vo
+
O(typ)
%/V
RMS
(1) To calculate the minimum input voltage for your maximum output current, use the following formula:
VI(min) = VO(max) + V
(2) Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that
the device operate under conditions beyond those specified in this table for extended periods of time.
(3) The minimum IN operating voltage is 2.7 V or V
output current is 200 mA.
(4) If VO≤ 2.5 V, then V
If VO≥ 2.5 V, then V
4
(max load)
DO
+ 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum
O(typ)
= 2.7 V, V
Imin
= VO+ 1 V, V
Imin
= 5.5 V:
Imax
= 5.5 V.
Imax
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TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range, EN = VI, TJ= –55 to 125 ° C and TJ= –40 to 125 ° C, VI= V 1 V, IO= 1 mA, Co= 10 µ F, C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input current (FB) (TPS79301) FB = 1.8 V 1 µ A
Power-supply ripple rejection
Dropout voltage
UVLO threshold V UVLO hysteresis TJ= 25 ° C V
(5)
TPS79328 dB
TPS79328
TPS793285
TPS79330 mV
TPS79333
TPS793475
= 0.01 µ F (unless otherwise noted)
(byp)
f = 100 Hz, TJ= 25 ° C, IO= 10 mA 70 f = 100 Hz, TJ= 25 ° C, IO= 200 mA 68 f = 10 Hz, TJ= 25 ° C, IO= 200 mA 70 f = 100 Hz, TJ= 25 ° C, IO= 200 mA 43 IO= 200 mA, TJ= 25 ° C 120 IO= 200 mA 200 IO= 200 mA, TJ= 25 ° C 120 IO= 200 mA 200 IO= 200 mA, TJ= 25 ° C 112 IO= 200 mA 200 IO= 200 mA, TJ= 25 ° C 102 IO= 200 mA 180 IO= 200 mA, TJ= 25 ° C 77 IO= 200 mA 125
CC
rising 2.25 2.65 V
rising 100 mV
CC
O(typ)
+
(5) IN voltage equals V
100 mV; The TPS79325 dropout voltage is limited by the input voltage range limitations.
O(typ)
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_
+
Thermal
Shutdown
Bandgap
Reference
V
IN
Current
Sense
R2
V
IN
EN
V
OUT
SHUTDOWN
V
ref
UVLO
ILIM
External to the Device
R1
UVLO
250 k
Bypass
FB
_
+
Thermal
Shutdown
V
IN
Current
Sense
R1
R2
V
IN
EN
V
OUT
SHUTDOWN
V
ref
UVLO
ILIM
Bandgap
Reference
UVLO
250 k
Bypass
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAM ADJUSTABLE VERSION

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM FIXED VERSION
TERMINAL FUNCTIONS
TERMINAL
NAME ADJ FIXED
BYPASS 4 4
EN 3 3 I FB 5 N/A I Feedback input voltage for the adjustable device
GND 2 2 Regulator ground IN 1 1 I Input to the device OUT 6 5 O Regulated output of the device
6
I/O DESCRIPTION
An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise.
Enable input that enables or shuts down the device. When EN goes to a logic high, the device is enabled. When the device goes to a logic low, the device is in shutdown mode.
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2.795
2.796
2.797
2.798
2.799
2.8
2.801
2.802
2.803
2.804
2.805
0 50 100 150 200
IO − Output Current − mA
TPS79328
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VI = 3.8 V Co = 10 µF TJ = 25° C
− Output Voltage − V V
O
2.775
2.78
2.785
2.79
2.795
2.8
2.805
−40−25−10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
TPS79328
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
− Output Voltage − V
V
O
IO = 200 mA
IO = 1 mA
VI = 3.8 V Co = 10 µF
0
50
100
150
200
250
−40−25−10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
TPS79328
GROUND CURRENT
vs
JUNCTION TEMPERATURE
Ground Current − Aµ
IO = 1 mA
VI = 3.8 V Co = 10 µF
IO = 200 mA
0
0.05
0.1
0.15
0.2
0.25
0.3
100 1 k 10 k 100 k
f − Frequency − Hz
IO = 1 mA
VI = 3.8 V Co = 2.2 µF C
(byp)
= 0.1 µF
IO = 200 mA
TPS79328
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
V/ HzOutput Spectral Noise Density −
µ
0
0.05
0.1
0.15
0.2
0.25
0.3
100 1 k 10 k 100 k
V/ HzOutput Spectral Noise Density −
µ
f − Frequency − Hz
IO = 1 mA
IO = 200 mA
TPS79328
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
VI = 3.8 V Co = 10 µF C
(byp)
= 0.1 µF
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
100 1 k 10 k 100 k
f − Frequency − Hz
V/ HzOutput Spectral Noise Density −
TPS79328
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
VI = 3.8 V IO = 200 mA Co= 10 µF
C
(byp)
= 0.1 µF
C
(byp)
= 0.001 µF
µ
C
(byp)
= 0.0047 µF
C
(byp)
= 0.01 µF
100 1 M10 1 k
f − Frequency − Hz
10 k
− Output Impedance −Z o
OUTPUT IMPEDANCE
vs
FREQUENCY
100 k
IO = 1 mA
0
0.5
1
1.5
2
2.5
0
IO = 100 mA
10 M
VI = 3.8 V Co = 10 µF TJ = 25° C
0.001 0.01 0.1
RMS − Root Mean Squared Output Noise −
ROOT MEAN SQUARED OUTPUT NOISE
vs
BYPASS CAPACITANCE
(RMS)
Vµ
C
(byp)
− Bypass Capacitance − µF
0
10
20
30
40
50
60
VO = 2.8 V IO = 200 mA Co = 10 µF
BW = 100 Hz to 100 kHz
0
20
40
60
80
100
120
140
160
180
−40−25−10 5 20 35 50 65 80 95 110 125
IO = 200 mA
IO = 10 mA
VI = 2.7 V Co = 10 µF
TJ − Junction Temperature − °C
− Dropout Voltage − mV
V
DO
TPS79328
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS

Figure 1. Figure 2. Figure 3.
Figure 4. Figure 5. Figure 6.
Figure 7. Figure 8. Figure 9.
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10 100 1 k 10 k
20
60
100
100 k 1 M 10 M
Ripple Rejection − dB
f − Frequency − Hz
TPS79328
RIPPLE REJECTION
vs
FREQUENCY
VI = 3.8 V Co = 2.2 µF C
(byp)
= 0.01 µF
IO = 10 mA
IO = 200 mA
40
70
90
30
50
80
10
0
10 100 1 k 10 k
20
60
100
100 k 1 M 10 M
Ripple Rejection − dB
f − Frequency − Hz
TPS79328
RIPPLE REJECTION
vs
FREQUENCY
VI = 3.8 V Co = 2.2 µF C
(byp)
= 0.1 µF
IO = 10 mA
IO = 200 mA
40
70
90
30
50
80
10
0
10 100 1 k 10 k
10
40
80
100 k 1 M 10 M
Ripple Rejection − dB
f − Frequency − Hz
TPS79328
RIPPLE REJECTION
vs
FREQUENCY
IO = 10 mA
50
0
VI = 3.8 V Co = 10 µF C
(byp)
= 0.01 µF
IO = 200 mA
20
30
60
70
90
100
t − Time − µs
TPS79328
LOAD TRANSIENT RESPONSE
0
0 15010050 200 250 350300 400 450
20
0
−20
V
O
Output Voltage − mV
− Change In
100
500
− Output Current − mA I
O
VI = 3.8 V Co = 10 µF
−40
200
300
di dt
+
0.02A
µs
1mA
TPS79328
LINE TRANSIENT RESPONSE
V
O
t − Time − µs
0 302010 40 50 7060 80 90 100
− Output Voltage − mV
IO = 200 mA Co = 2.2 µF C
(byp)
= 0.01 µF
V
I
− Input Voltage −
0
-20
3.8
dv
dt
+
0.4 V
µs
mV
20
4.8
3
TPS79328
OUTPUT VOLTAGE, ENABLE VOLTAGE
vs
TIME (START-UP)
V
O
t − Time − µs
0 604020 80 100 140120 160 180 200
− Output Voltage − V
VI = 3.8 V VO = 2.8 V I
O
= 200 mA Co = 2.2 µF TJ = 25°C
Enable Voltage − V
1
2
0
0
2
C
(byp)
= 0.0047 µF
C
(byp)
= 0.01 µF
4
C
(byp)
= 0.001 µF
500 mV/div
1s/div
POWER UP / POWER DOWN
V
I
V
O
VO = 3 V RL = 15
100
50
0 20 40 60 80 100 120
DC Dropuoy Voltage − mV
150
200
DC DROPOUT VOLTAGE
vs
OUTPUT CURRENT
250
140 160180 200
0
I
O
− Output Current − mA
TJ = 125°C
TJ = 25°C
TJ = −55°C
0
50
100
150
200
2.5 3 3.5 4 4.5 5
TPS79301
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
VI − Input Voltage − V
− Dropout Voltage − mV
V
DO
IO = 200 mA
TJ = 25°C
TJ = −40°C
TJ = 125°C
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
Figure 10. Figure 11. Figure 12.
TYPICAL CHARACTERISTICS (continued)
Figure 13. Figure 14. Figure 15.
8
Figure 16. Figure 17. Figure 18.
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2
3
4
1.5 2.5 3.52 3
TJ = 25°C
IO = 200 mA
− Minimum Required Input Voltage − V
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
VO − Output Voltage − V
V
I
1.75 2.25 2.75 3.25
2.8
TJ = 125°C
TJ = −40°C
0.01
0.1
10
100
0 0.02 0.04 0.06 0.08 0.2
I
O
− Output Current − A
ESR − Equivalent Series Resistance −
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
1
Region of Instability
Region of Stability
Co = 2.2 µF VI = 5.5 V, VO 1.5 V TJ = −40°C to 125°C
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
0.01
0.1
10
100
0 0.02 0.04 0.06 0.08 0.2
I
O
− Output Current − A
ESR − Equivalent Series Resistance −
1
Region of Instability
Region of Stability
Co = 10 µF V
I
= 5.5 V
TJ = −40°C to 125°C
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
TYPICAL CHARACTERISTICS (continued)
Figure 19. Figure 20. Figure 21.
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0.1 µF
BYPASS
OUT
1
3
IN
EN
2
4
5
V
I
V
O
2.2 µF
+
TPS793xx
0.01 µF
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006

APPLICATION INFORMATION

The TPS793xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (170 µ A typically), and enable-input to reduce supply currents to less than 1 µ A when the regulator is turned off.
A typical application circuit is shown in Figure 22 .
Figure 22. Typical Application Circuit

External Capacitor Requirements

A 0.1- µ F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS793xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source.
Like all LDOs, the TPS793xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 2.2- µ F. Any 2.2- µ F or larger ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS793xx has a BYPASS pin that is connected to the voltage reference through a 250-k internal resistor. The 250-k internal resistor, in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the BYPASS pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus, creating an output error. Therefore, the bypass capacitor must have minimal leakage current.
For example, the TPS79328 exhibits only 32 µ V
of output voltage noise using a 0.1- µ F ceramic bypass
RMS
capacitor and a 2.2- µ F ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the BYPASS pin that is created by the internal 250-k resistor and external capacitor.

Board Layout Recommendation to Improve PSRR and Noise Performance

and V
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IN
, with each ground plane connected only at the
OUT
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for V GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the GND pin of the device.
10
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P
D(max)
+
TJmax * T
A
R
θJA
P
D
+
ǒ
VI* V
O
Ǔ
I
O
VO+ V
ref
ǒ
1 )
R1 R2
Ǔ
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP
TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)

Power Dissipation and Junction Temperature

Specified regulator operation is ensured to a junction temperature of 125 ° C; the maximum junction temperature should be restricted to 125 ° C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P equal to P
The maximum power dissipation limit is determined using the following equation:
Where:
TJmax = Maximum allowable junction temperature R θ
JA
T
= Ambient temperature
A
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit.
.
D(max)
= Thermal resistance, junction to ambient, for the package, see the dissipation rating table
, and the actual dissipation, PD, which must be less than or
D(max)
(1)
(2)

Programming the TPS79301 Adjustable LDO Regulator

The output voltage of the TPS79301 adjustable regulator is programmed using an external resistor divider as shown in Figure 23 . The output voltage is calculated using:
Where:
V
= 1.2246 V typical (the internal reference voltage)
ref
(3)
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11
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R1 +
ǒ
V
O
V
ref
* 1Ǔ R2
C1 +
(3 x 10–7) x (R1 ) R2)
(R1 x R2)
22 pF 15 pF 15 pF
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE
R1 R2
2.5 V
3.3 V
3.6 V
C1
31.6 k 51 k 59 k
30.1 k
30.1 k
30.1 k
V
O
V
I
OUT
FB
R1
R2
EN
IN
0.7 V
2 V
TPS79301
1 µF
BYPASS
0.01 µF
1 µF
C1
TPS79301-EP , , TPS79318-EP , , TPS79325-EP , , TPS79328-EP TPS793285-EP , TPS79330-EP , TPS79333-EP , TPS793475-EP
SGLS163B – APRIL 2003 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)

Programming the TPS79301 Adjustable LDO Regulator (continued)

Resistors R1 and R2 should be chosen for approximately 50- µ A divider current. Lower-value resistors can be used for improved noise performance, but the solution consumes more power. Higher resistor values should be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially increases/decreases the feedback voltage and, thus, erroneously decreases/increases VO. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 50 µ A, C1 = 15 pF for stability, and then calculate R1 using:
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For voltages >1.8 V, the approximate value of this capacitor can be calculated as:
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration) or if an output voltage <1.8 V is chosen, then the minimum recommended output capacitor is 4.7 µ F instead of 2.2 µ F.
(4)
(5)

Regulator Protection

The TPS793xx features internal current limiting and thermal protection. During normal operation, the TPS793xx limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum voltage ratings of the device. If the temperature of the device exceeds approximately 165 ° C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140 ° C, regulator operation resumes.
12
Figure 23. TPS79301 Adjustable LDO Regulator Programming
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
PACKAGING INFORMATION
Orderable Device Status
TPS79301DBVREP ACTIVE SOT-23 DBV 6 3000 Green (RoHS
TPS79301MDBVREP ACTIVE SOT-23 DBV 6 3000 Green (RoHS
TPS79318DBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS
TPS79333DBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS
TPS793475DBVREP ACTIVE SOT-23 DBV 5 3000 Green (RoHS
V62/03634-01YE ACTIVE SOT-23 DBV 6 3000 Green (RoHS
V62/03634-02XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS
V62/03634-07XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS
V62/03634-08XE ACTIVE SOT-23 DBV 5 3000 Green (RoHS
V62/03634-09XE ACTIVE SOT-23 DBV 6 3000 Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PGVE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PMBM
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHHE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHUE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHJE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PGVE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHHE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHUE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PHJE
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PMBM
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2015
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS79333-EP :
Catalog: TPS79333
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions arenominal
Device Package
TPS79301DBVREP SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS79301MDBVREP SOT-23 DBV 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS79318DBVREP SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TPS79333DBVREP SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS793475DBVREP SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Oct-2015
*All dimensions arenominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS79301DBVREP SOT-23 DBV 6 3000 182.0 182.0 20.0
TPS79301MDBVREP SOT-23 DBV 6 3000 203.0 203.0 35.0
TPS79318DBVREP SOT-23 DBV 5 3000 182.0 182.0 20.0 TPS79333DBVREP SOT-23 DBV 5 3000 182.0 182.0 20.0
TPS793475DBVREP SOT-23 DBV 5 3000 182.0 182.0 20.0
Pack Materials-Page 2
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